EDBT 2026 Demo / reviewers in the wild / expert
Dhairya Malhotra
dblp:98/9134
· DBLP profile ↗
8ranked-venue papers
2as first author
1since 2021 · last 2021
0000-0001-9567-1322ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7 · 1 first-author · 1 since 2021Theory of computation · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
5 papers |
High-performance computing · 32% Hardware accelerators and domain-specific architectures · 16% Performance modeling and evaluation · 12% |
Topics — the 18 heaviest of 19, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
accelerator integration |
0.7 | 2 | 2021 | Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods · IEEE Trans. Parallel Distributed Syst. 2021 A Volume Integral Equation Stokes Solver for Problems with Variable Coefficients · SC 2014 |
Performance modeling and evaluation › numerical algorithms
fast multipole method |
0.5 | 1 | 2021 | Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods · IEEE Trans. Parallel Distributed Syst. 2021 |
High-performance computing
scientific computing systems |
0.4 | 2 | 2016 | A parallel arbitrary-order accurate AMR algorithm for the scalar advection-diffusion equation · SC 2016 Petascale Direct Numerical Simulation of Blood Flow on 200K Cores and Heterogeneous Architectures · SC 2010 |
High-performance computing
performance optimization at scale |
0.3 | 2 | 2014 | A Volume Integral Equation Stokes Solver for Problems with Variable Coefficients · SC 2014 Petascale Direct Numerical Simulation of Blood Flow on 200K Cores and Heterogeneous Architectures · SC 2010 |
High-performance computing › scientific computing systems
adaptive mesh refinement |
0.2 | 1 | 2016 | A parallel arbitrary-order accurate AMR algorithm for the scalar advection-diffusion equation · SC 2016 |
Parallel and multicore computing
parallel programming models |
0.2 | 1 | 2016 | A parallel arbitrary-order accurate AMR algorithm for the scalar advection-diffusion equation · SC 2016 |
GPUs and heterogeneous computing
GPU computing |
0.2 | 2 | 2014 | A Volume Integral Equation Stokes Solver for Problems with Variable Coefficients · SC 2014 Petascale Direct Numerical Simulation of Blood Flow on 200K Cores and Heterogeneous Architectures · SC 2010 |
High-performance computing
numerical linear algebra |
0.2 | 1 | 2014 | A Volume Integral Equation Stokes Solver for Problems with Variable Coefficients · SC 2014 |
Storage systems
i/o optimization |
0.2 | 1 | 2013 | Algorithms for high-throughput disk-to-disk sorting · SC 2013 |
Processor architecture and microarchitecture
latency hiding |
0.2 | 1 | 2013 | Algorithms for high-throughput disk-to-disk sorting · SC 2013 |
Memory systems › memory access optimization
DRAM access reduction |
0.1 | 1 | 2021 | Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods · IEEE Trans. Parallel Distributed Syst. 2021 |
Memory systems › processing-in-memory
near-DRAM acceleration |
0.1 | 1 | 2021 | Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods · IEEE Trans. Parallel Distributed Syst. 2021 |
Memory systems
processing-in-memory |
0.1 | 1 | 2021 | Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods · IEEE Trans. Parallel Distributed Syst. 2021 |
High-performance computing › scientific computing systems › computational fluid dynamics
blood flow simulation |
0.1 | 1 | 2010 | Petascale Direct Numerical Simulation of Blood Flow on 200K Cores and Heterogeneous Architectures · SC 2010 |
High-performance computing › scientific computing systems
computational fluid dynamics |
0.1 | 1 | 2010 | Petascale Direct Numerical Simulation of Blood Flow on 200K Cores and Heterogeneous Architectures · SC 2010 |
GPUs and heterogeneous computing › CPU-GPU heterogeneous computing
CPU-GPU parallelism |
0.1 | 1 | 2010 | Petascale Direct Numerical Simulation of Blood Flow on 200K Cores and Heterogeneous Architectures · SC 2010 |
GPUs and heterogeneous computing
heterogeneous architecture |
0.1 | 1 | 2010 | Petascale Direct Numerical Simulation of Blood Flow on 200K Cores and Heterogeneous Architectures · SC 2010 |
Processor architecture and microarchitecture
multithreading |
0.0 | 1 | 2010 | Petascale Direct Numerical Simulation of Blood Flow on 200K Cores and Heterogeneous Architectures · SC 2010 |
Methods — techniques the papers use, named apart from their topics
software pipelining · 0.5software blocking · 0.5simulation · 0.5semi-lagrangian scheme · 0.2method of characteristics · 0.2chebyshev octree · 0.2volume integral equation · 0.2fast multipole method · 0.2adaptive discretization · 0.2asynchronous data transfer · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body MethodsabstractIn this article, we study performance and energy saving benefits of hardware acceleration under different hardware configurations and usage scenarios for a state-of-the-art Fast Multipole Method (FMM), which is a popular N-body method. We use a dedicated Application Specific Integrated Circuit (ASIC) to accelerate General Matrix-Matrix Multiply (GEMM) operations. FMM is widely used in applications and is representative example of the workload for many HPC applications. We compare architectures that integrate the GEMM ASIC next to, in or near main memory with an on-chip coupling aimed at minimizing or avoiding repeated round-trip transfers through DRAM for communication between accelerator and CPU. We study tradeoffs using detailed and accurately calibrated x86 CPU, accelerator and DRAM simulations. Our results show that simply moving accelerators closer to the chip does not necessarily lead to performance/energy gains. We demonstrate that, while careful software blocking and on-chip placement optimizations can reduce DRAM accesses by 2X over a naive on-chip integration, these dramatic savings in DRAM traffic do not automatically translate into significant total energy or runtime savings. This is chiefly due to the application characteristics, the high idle power and effective hiding of memory latencies in modern systems. Only when more aggressive co-optimizations such as software pipelining and overlapping are applied, additional performance and energy savings can be unlocked by 37 and 35 percent respectively over baseline acceleration. When similar optimizations (pipelining and overlapping) are applied with an off-chip integration, on-chip integration delivers up to 20 percent better performance and 17 percent less total energy consumption than off-chip integration. Mochamad Asri, Dhairya Malhotra, George Biros, Lizy Kurian John, Andreas Gerstlauer |
IEEE Trans. Parallel Distributed Syst. | 2 |
| 2016 | A parallel arbitrary-order accurate AMR algorithm for the scalar advection-diffusion equationabstractWe present a numerical method for solving the scalar advection-diffusion equation using adaptive mesh refinement. Our solver has three unique characteristics: (1) it supports arbitrary-order accuracy in space; (2) it allows different discretizations for the velocity and scalar advected quantity; (3) it combines the method of characteristics with an integral equation formulation; and (4) it supports shared and distributed memory architectures. In particular, our solver is based on a second-order accurate, unconditionally stable, semi-Lagrangian scheme combined with a spatially-adaptive Chebyshev octree for discretization. We study the convergence, single-node performance, strong scaling, and weak scaling of our scheme for several challenging flows that cannot be resolved efficiently without using high-order accurate discretizations. For example, we consider problems for which switching from 4th order to 14th order approximation results in two orders of magnitude speedups for a computation in which we keep the target accuracy in the solution fixed. For our largest run, we solve a problem with one billion unknowns on a tree with maximum depth equal to 10 and using 14th-order elements on 16,384 x86 cores on the “STAMPEDE“ system at the Texas Advanced Computing Center. Arash Bakhtiari, Dhairya Malhotra, Amir Raoofy, Miriam Mehl, Hans-Joachim Bungartz, George Biros |
SC | 2 |
| 2016 | Algorithm 967: A Distributed-Memory Fast Multipole Method for Volume PotentialsabstractThe solution of a constant-coefficient elliptic Partial Differential Equation (PDE) can be computed using an integral transform: A convolution with the fundamental solution of the PDE, also known as a volume potential. We present a Fast Multipole Method (FMM) for computing volume potentials and use them to construct spatially adaptive solvers for the Poisson, Stokes, and low-frequency Helmholtz problems. Conventional N-body methods apply to discrete particle interactions. With volume potentials, one replaces the sums with volume integrals. Particle N-body methods can be used to accelerate such integrals. but it is more efficient to develop a special FMM. In this article, we discuss the efficient implementation of such an FMM. We use high-order piecewise Chebyshev polynomials and an octree data structure to represent the input and output fields and enable spectrally accurate approximation of the near-field and the Kernel Independent FMM (KIFMM) for the far-field approximation. For distributed-memory parallelism, we use space-filling curves, locally essential trees, and a hypercube-like communication scheme developed previously in our group. We present new near and far interaction traversals that optimize cache usage. Also, unlike particle N-body codes, we need a 2:1 balanced tree to allow for precomputations. We present a fast scheme for 2:1 balancing. Finally, we use vectorization, including the AVX instruction set on the Intel Sandy Bridge architecture to get better than 50% of peak floating-point performance. We use task parallelism to employ the Xeon Phi on the Stampede platform at the Texas Advanced Computing Center (TACC). We achieve about 600 gflop /s of double-precision performance on a single node. Our largest run on Stampede took 3.5s on 16K cores for a problem with 18 e +9 unknowns for a highly nonuniform particle distribution (corresponding to an effective resolution exceeding 3 e +23 unknowns since we used 23 levels in our octree). Dhairya Malhotra, George Biros |
ACM Trans. Math. Softw. | 1 |
| 2014 | Performance analysis of HPC applications with irregular tree data structuresabstractAdaptive mesh refinement (AMR) numerical methods utilizing octree data structures are an important class of HPC applications, in particular the solution of partial differential equations. Much effort goes into the implementation of efficient versions of these types of programs, where the emphasis is often on increasing multi-node performance when utilizing GPUs and coprocessors. By contrast, our analysis aims to characterize these workloads on traditional CPUs, as we believe that single-threaded intra-node performance of critical kernels is still a key factor for achieving performance at scale. Especially irregular workloads such as AMR methods, however, exhibit severe underutilization on general purpose processors. In this paper, we analyze the single core performance of two state-of-the-art, highly scalable adaptive mesh refinement codes, one based on the Fast Multipole Method (FMM) and one based on the Finite Element Method (FEM), when running on a x86 CPU. We examined both scalar and vectorized implementations to identify performance bottlenecks. We demonstrate that vectorization can provide a significant benefit in achieving high performance. The greatest bottleneck to peak performance is the high fraction of non-floating point instructions in the kernels. Ahmed Khawaja, Andreas Gerstlauer, Lizy Kurian John, Dhairya Malhotra, George Biros |
ICPADS | 5 |
| 2014 | A Volume Integral Equation Stokes Solver for Problems with Variable CoefficientsabstractWe present a novel numerical scheme for solving the Stokes equation with variable coefficients in the unit box. Our scheme is based on a volume integral equation formulation. Compared to finite element methods, our formulation decouples the velocity and pressure, generates velocity fields that are by construction divergence free to high accuracy and its performance does not depend on the order of the basis used for discretization. In addition, we employ a novel adaptive fast multipole method for volume integrals to obtain a scheme that is algorithmically optimal. Our scheme supports non-uniform discretizations and is spectrally accurate. To increase per node performance, we have integrated our code with both NVIDIA and Intel accelerators. In our largest scalability test, we solved a problem with 20 billion unknowns, using a 14-order approximation for the velocity, on 2048 nodes of the Stampede system at the Texas Advanced Computing Center. We achieved 0.656 peta FLOPS for the overall code (23% efficiency) and one peta FLOPS for the volume integrals (33% efficiency). As an application example, we simulate Stokes ow in a porous medium with highly complex pore structure using a penalty formulation to enforce the no slip condition. Dhairya Malhotra, Amir Gholami, George Biros |
SC | 1 |
| 2013 | HykSort: a new variant of hypercube quicksort on distributed memory architecturesabstractIn this paper, we present HykSort, an optimized comparison sort for distributed memory architectures that attains more than 2× improvement over bitonic sort and samplesort. The algorithm is based on the hypercube quicksort, but instead of a binary recursion, we perform a k-way recursion in which the pivots are selected accurately with an iterative parallel select algorithm. The single-node sort is performed using a vectorized and multithreaded merge sort. The advantages of HykSort are lower communication costs, better load balancing, and avoidance of O(p)-collective communication primitives. We also present a staged communication samplesort, which is more robust than the original samplesort for large core counts. We conduct an experimental study in which we compare hypercube sort, bitonic sort, the original samplesort, the staged samplesort, and HykSort. We report weak and strong scaling results and study the effect of the grain size. It turns out that no single algorithm performs best and a hybridization strategy is necessary. As a highlight of our study, on our largest experiment on 262,144 AMD cores of the CRAY XK7 "Titan" platform at the Oak Ridge National Laboratory we sorted 8 trillion 32-bit integer keys in 37 seconds achieving 0.9TB/s effective throughput. Hari Sundar, Dhairya Malhotra, George Biros |
ICS | 2 |
| 2013 | Algorithms for high-throughput disk-to-disk sortingabstractIn this paper, we present a new out-of-core sort algorithm, designed for problems that are too large to fit into the aggregate RAM available on modern supercomputers. We analyze the performance including the cost of IO and demonstrate the fastest (to the best of our knowledge) reported throughput using the canonical sortBenchmark on a general-purpose, production HPC resource running Lustre. By clever use of available storage and a formulation of asynchronous data transfer mechanisms, we are able to almost completely hide the computation (sorting) behind the IO latency. This latency hiding enables us to achieve comparable execution times, including the additional temporary IO required, between a large sort problem (5TB) run as a single, in-RAM sort and our out-of-core approach using 1/10th the amount of RAM. In our largest run, sorting 100TB of records using 1792 hosts, we achieved an end-to-end throughput of 1.24TB/min using our general-purpose sorter, improving on the current Daytona record holder by 65%. Hari Sundar, Dhairya Malhotra, Karl W. Schulz |
SC | 2 |
| 2010 | Petascale Direct Numerical Simulation of Blood Flow on 200K Cores and Heterogeneous ArchitecturesabstractWe present a fast, petaflop-scalable algorithm for Stokesian particulate flows. Our goal is the direct simulation of blood, which we model as a mixture of a Stokesian fluid (plasma) and red blood cells (RBCs). Directly simulating blood is a challenging multiscale, multiphysics problem. We report simulations with up to 200 million deformable RBCs. The largest simulation amounts to 90 billion unknowns in space. In terms of the number of cells, we improve the state-of-the art by several orders of magnitude: the previous largest simulation, at the same physical fidelity as ours, resolved the flow of O(1,000-10,000) RBCs. Our approach has three distinct characteristics: (1) we faithfully represent the physics of RBCs by using nonlinear solid mechanics to capture the deformations of each cell; (2) we accurately resolve the long-range, N-body, hydrodynamic interactions between RBCs (which are caused by the surrounding plasma); and (3) we allow for the highly non-uniform distribution of RBCs in space. The new method has been implemented in the software library MOBO (for “Moving Boundaries”). We designed MOBO to support parallelism at all levels, including inter-node distributed memory parallelism, intra-node shared memory parallelism, data parallelism (vectorization), and fine-grained multithreading for GPUs. We have implemented and optimized the majority of the computation kernels on both Intel/AMD x86 and NVidia's Tesla/Fermi platforms for single and double floating point precision. Overall, the code has scaled on 256 CPU-GPUs on the Teragrid's Lincoln cluster and on 200,000 AMD cores of the Oak Ridge national Laboratory's Jaguar PF system. In our largest simulation, we have achieved 0.7 Petaflops/s of sustained performance on Jaguar. Abtin Rahimian, Ilya Lashuk, Shravan K. Veerapaneni, Aparna Chandramowlishwaran, Dhairya Malhotra, Logan Moon, Rahul S. Sampath, Aashay Shringarpure, Jeffrey S. Vetter, Richard W. Vuduc, Denis Zorin, George Biros |
SC | 5 |