Reservoir Computing (RC) is a class of machine learning approaches that is suitable for prediction tasks with low computational complexity. In this paper, an RC-based symbol detection for MIMO- OFDM systems is presented where RC is realized through the echo state network (ESN). Detailed energy-efficiency analysis is conducted to characterize the energy-efficiency of the introduced symbol detector. To be specific, the transmit power, the circuit power, and the computational power at both transmitter and receiver are jointly considered for the energy-efficiency analysis. The overall system energy-efficiency as well as the receiver energy-efficiency of the introduced RC-based symbol detector are compared with those of the popular linear minimum mean squared error (LMMSE)-based approach. Simulation and numerical results show that the RC-based symbol detector is a ``green'' solution compared to the traditional LMMSE-based method with lower energy consumption per information bit.

In this research, we present a Conductive-Bridge RAM (CBRAM)-based neuromorphic system which efficiently addresses time series prediction. We propose a new (i) voltage-mode, stochastic, multiweight synapse circuit based on experimental bi-stable CBRAM devices, (ii) a voltage-mode neuron circuit based on the concept of charge sharing, and (iii) an optimized training methodology powered by a stochastic implementation of the Least-Mean-Squares (SLMS) training rule. To validate the proposed design, we use time series prediction for short-term electrical load forecasting in smart grids. Our system is able to forecast hourly electrical loads with a mean accuracy of 96%, an estimated power dissipation of 15 μW, and area of 14.5 μm 2 at 65 nm CMOS technology.

Reservoir Computing (RC) is a recent neurologically inspired concept for processing time dependent data that lends itself particularly well to hardware implementation by using the device physics to conduct information processing. In this paper, we apply RC to channel estimation in Orthogonal Frequency Division Multiplexing (OFDM) systems. Due to the multipath propagation environment between a transmitter and receiver, the received signal undergoes attenuation, time delay and phase shift. For mitigating these random effects and decoding the transmitted signal at the receiver, accurate channel estimation is vital. Statistical approaches for channel estimation assume that accurate channel information is available at the receiver. However, the time-variance of the channel complicates the channel estimation process by making the current estimation outdated. Recurrent Neural Networks (RNNs), which are analogous to the functioning of the human brain, are therefore utilized for channel prediction. Training algorithms for RNNs are categorized as gradient-descent methods, which often results in high computational complexity and leads to non-convergence due to the presence of bifurcations. In this paper, an Echo State Network (ESN), which is a class of RC approach, has been used for training a RNN to estimate the channel state information. Using this approach, the training and hence, the implementation complexity is significantly reduced. Simulation results show significant improvement in channel estimation accuracy for the proposed method.

Echo state networks (ESNs) are gaining popularity as a method for recognizing patterns in time series data. ESNs are random, recurrent neural network topologies that are able to integrate temporal data over short time windows by operating on the edge of chaos. In this paper, we explore the design of a hardware ESN with bi-stable memristor-based synapses. Hybrid CMOS/memristor hardware implementations of ESNs are able to exploit non-linear device physics, improving power consumption, and boosting performance over software approaches. However, the digital nature of most experimental memristors places a limit on the precision of weight states in the ESN's readout layer. In spite of this, we show that ESNs with only 5 different readout layer weight states can acheive 67% accuracy in spoken digit recognition tasks.

Echo state neural networks (ESNs) provide an efficient classification technique for spatiotemporal signals. The feedback connections in the ESN topology enable feature extraction of both spatial and temporal components in time series data. This property has been used in several application domains such as image and video analysis, anomaly detection, and speech recognition. In this research, we explore a hardware architecture for realizing ESN efficiently in power-constrained devices. Specifically, we propose a scalable computational architecture applied to speech-emotion recognition. Two different topologies are explored, with memristive synapses. The simulation results are promising with a classification accuracy of ≈ 96% for two distinct emotion statuses.

Neuromorphic computing is a novel paradigm that inspired from the dynamic behavior of the biological brain. The encoding capability plays a vital role in information processing, especially for neural network based systems. In this paper, a compact, low power, and robust spiking-time-dependent encoder is designed with an accommodative Leaky Integrate and Fire (LIF) model based neuron cluster and a chaotic circuit with ring oscillators. Novel and fundamental methodologies, which represent data by using spike timing dependent encoding, has been developed. The information in signal amplitude has been mapped into a spike time sequence efficiently by time encoding, which represents the input data and offers perfect recovery for band limited stimuli. Time dependent temporal scales have been adopted to pattern the neural activities across multiple timescales and encode the sensory information. Furthermore, chaotic circuit based Pseudorandom Time Series Generator (PTSG) is designed to generate sampling clock. High resolution is provided with chaotic based sampling in the proposed encoding circuit. Detailed post layout simulation results and analysis of the designed circuit are presented.

This article presents our research towards developing novel and fundamental methodologies for data representation using spike-timing-dependent encoding. Time encoding efficiently maps a signal's amplitude information into a spike time sequence that represents the input data and offers perfect recovery for band-limited stimuli. In this article, we pattern the neural activities across multiple timescales and encode the sensory information using time-dependent temporal scales. The spike encoding methodologies for autonomous classification of time-series signatures are explored using near-chaotic reservoir computing. The proposed spiking neuron is compact, low power, and robust. A hardware implementation of these results is expected to produce an agile hardware implementation of time encoding as a signal conditioner for dynamical neural processor designs.

Information security has emerged as an important system and application metric. Classical security solutions use algorithmic mechanisms that address a small subset of emerging security requirements, often at high-energy and performance overhead. Further, emerging side-channel and physical attacks can compromise classical security solutions. Hardware security solutions overcome many of these limitations with less energy and performance overhead. Nanoelectronics-based hardware security preserves these advantages while enabling conceptually new security primitives and applications. This tutorial paper shows how one can develop hardware security primitives by exploiting the unique characteristics such as complex device and system models, bidirectional operation, and nonvolatility of emerging nanoelectronic devices. This paper then explains the security capabilities of several emerging nanoelectronic devices: memristors, resistive random-access memory, contact-resistive random-access memory, phase change memories, spin torque-transfer random-access memory, orthogonal spin transfer random access memory, graphene, carbon nanotubes, silicon nanowire field-effect transistors, and nanoelectronic mechanical switches. Further, the paper describes hardware security primitives for authentication, key generation, data encryption, device identification, digital forensics, tamper detection, and thwarting reverse engineering. Finally, the paper summarizes the outstanding challenges in using emerging nanoelectronic devices for security.

Hardware security has emerged as an important field of study aimed at mitigating issues such as piracy, counterfeiting, and side channel attacks. One popular solution for such hardware security attacks are physical unclonable functions (PUF) which provide a hardware specific unique signature or identification. The uniqueness of a PUF depends on intrinsic process variations within individual integrated circuits. As process variations become more prevalent due to technology scaling into the nanometer regime, novel nanoelectronic technologies such as memristors become viable options for improved security in emerging integrated circuits. In this paper, we provide an overview of memristor based PUF structures and circuits that illustrate the potential for nanoelectronic hardware security solutions.

Hardware security has emerged as an important field of study aimed at mitigating issues such as piracy, counterfeiting, and side channel attacks. One popular solution for such hardware security attacks are physical unclonable functions (PUF) which provide a hardware specific unique signature or identification. The uniqueness of a PUF depends on intrinsic process variations within individual integrated circuits. As process variations become more prevalent due to technology scaling into the nanometer regime, novel nanoelectronic technologies such as memristors become viable options for improved security in emerging integrated circuits. In this paper, we describe a novel memristive PUF (M-PUF) architecture that utilizes variations in the write-time of a memristor as an entropy source. The results presented show strong statistical performance for the M-PUF in terms of uniqueness, uniformity, and bit-aliasing. Additionally, nanoscale M-PUFs are shown to exhibit reduced area utilization as compared to CMOS counterparts.

Scientists have dreamed of an information system with cognitive human-like skills for years. However, constrained by the device characteristics and rapidly increasing design complexity under the traditional processing technology, little progress has been made in hardware implementation. The recently popularized memristor offers a potential breakthrough for neuromorphic computing because of its unique properties including nonvolatily, extremely high fabrication density, and sensitivity to historic voltage/current behavior. In this work, we first investigate the memristor-based synapse design and the corresponding training scheme. Then, a case study of an 8-bit arithmetic logic unit (ALU) design is used to demonstrate the hardware implementation of reconfigurable system built based on memristor synapses.

The value memristor devices offer to the neuromorphic computing hardware design community rests on the ability to provide effective device models that can enable large scale integrated computing architecture application simulations. Therefore, it is imperative to develop practical, functional device models of minimum mathematical complexity for fast, reliable, and accurate computing architecture technology design and simulation. To this end, various device models have been proposed in the literature seeking to characterize the physical electronic and time domain behavioral properties of memristor devices. In this work, we analyze some promising and practical non-quasi-static linear and non-linear memristor device models for neuromorphic circuit design and computing architecture simulation.