Equivalence checking (EC) and functional Engineering Change Order (ECO) on large-scale designs becomes a crucial industrial topic as the design scale expands. In this topic, we are especially interested in how to partition the large-scale problems into smaller EC and ECO problem with lower complexity. In this contest, we ask the participants to design the algorithm to insert the corresponding cuts as the partitioned points on given two designs as simplifying the EC and ECO problems. The team correctly simplifying the problem most wins the contest. The benchmark suites are extracted from the real designs in our interesting applications. We look forward to triggering the academic area to investigate on this problem.

Efficiently solving numerous relevant circuit satisfiability (CircuitSAT) problems becomes a crucial industrial topic as the design scale expands. In this topic, we are especially interested in: how to select the best setting of the Boolean satisfiability (SAT) solver based on sample problems, and what is the most useful conjunctive normal form (CNF) encoding for some particular designs and particular applications. From practical experience, the run time yielded by solving SAT problems using the default setting is far from best run time; same is true for CNF encoding. In this contest, we ask the participants to design the algorithm for exploring the best setting based on some sample cases, and we determine the contest winners by evaluating the run time for solving the remaining problems. The benchmark suites are extracted from the real designs in our applications of interest. We look forward to triggering the academic area in further investigating this problem.

As technology advances, there is an increasing need in the industrial domain for an algorithm that can map macro blocks. This type of algorithm would solve several front-end problems. For example, existing structural or functional algorithms cannot solve the challenge of mapping large-scale functions without boundary information. Fortunately, in practical problems, we only consider the target mapping functions that are the constructs of the datapath, and these macro blocks are easily recognized through their special arithmetic signatures. In this problem, the contestants need to design a mapping algorithm that recognizes macro blocks and replaces the mapped region with the macro blocks. Therefore, we can fairly evaluate the quality of the mapping algorithm as the size reduction of the revised netlist. Under our well-designed benchmarks, we will clearly differentiate the capability of proposed algorithms with several indexes. We look forward to triggering the academic area to investigate on this problem.

High-density probing is a main trend of the test technology. The warping issues of probe card are caused by the high-density test. The metal backer and patches are applied to solve this problem and the optimized sizes of backer and patches are decided by the proposed flow. Using the probe card with optimized backer and patches, the stability of test can be ensured and the test yields are increased. 26.56% test-yield improvement can be obtained.

Functional engineering change order (ECO) is a popular technique for rectifying design errors after synthesis and placement stages. We present a new approach to generating the patch circuits for multierror circuit rectification. In this paper, we propose a two-phase approach of: 1) discovering the functional matches in two circuits followed by 2) determining the final patch circuits from the matches. The ECO engine in this paper discovers functional and structural matches in two circuits by coordinating the SAT-sweeping and the cut-matching algorithms. Then, the patch selection is conducted by the combinational equivalence checking technique and a linear-time selection heuristic. The experimental results on public benchmark and industrial circuits demonstrate that this ECO engine outperforms state-of-the-art interpolation-based engines.

Functional ECO has been an indispensible technique in modern VLSI design flow. This paper proposes an ECO engine in a two-phase approach: a matching phase for rectification pair identification and a replacement phase for pair selection and patch minimization. The rectification pair identification algorithm explores rectification pairs between the original circuit and the golden circuit. The rectification pair selector determines final patches through a linear-time heuristic. A gate-recycle process performs patch minimization for final refinement. The experiments show that this ECO engine outperforms a state-of-the-art interpolation-based engine in both patch quality and runtime.