This paper provides a case study for enhancing Threshold Logic (TL) performance by exploiting the back-gate bias control offered by 22nm Fully Depleted Silicon-on-Insulator (FDSOI) technology across three process corners and five temperatures under transient noise. The paper demonstrates how back-gate biasing changes the threshold voltage and reduces the offset from 500µV to 400µV. Moreover, the improvement of 200µV in symmetric offset range and 100µV in input resolution are observed in comparison to conventional biasing. These improvements come at the cost of increased energy dissipation at temperatures higher than 27°C. The accuracy detection is slightly better under conventional biasing with an improvement of 30µV differential input range at 125°C. The back gate biasing results in a marginal shift of the graph by 0.03% at −55°C to a maximum of 8% at 125°C in comparison to the conventional biasing.

This paper compares the cross-technology performance of an improved Adiabatic Capacitive Neuron (ACN) design variant. Performance is compared across three commercially available CMOS technologies: two bulk 180nm and 130nm and a 22nm, ultra-low-power Fully-Depleted Silicon-On-Insulator (FDSOI) technology for extreme-edge neuromorphic computing. For comparison, we implement an ACN that is functionally equivalent to a software-trained Artificial Neuron (AN) with binary inputs and outputs, as well as positive, real-valued weights. The paper also demonstrates how back-gate biasing in FDSOI can be used to manipulate the threshold voltage and thus reduce threshold and leakage losses, further enhancing the energy performance of the adiabatic components of the ACN. Simulation results demonstrate that the 22nm technology node dramatically outperforms its 180nm and 130nm counterparts in energy savings, especially at frequencies of 10MHz and above. At 100MHz the synapse energy savings are 4.8x and 3.5x, while the threshold logic savings are 10x and 4.5x when compared to 180nm and 130nm technologies respectively.

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1k$\Omega$ and 10M$\Omega$ with a minimum voltage range of ±1.5V on the device.

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with ‘memimpedace’ elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at$100^{o}C$across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance’s quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).

In recent years, RRAM technology has been actively developed as a means of reducing power dissipation and area in a host of circuits, most notably artificial neuron synapses. However, further reduction in energy consumption may be possible by transitioning to capacitive synapses and combining them with adiabatic technique. In this work, we present and analyse the function and power dissipation of an artificial neuron with capacitive synapses where the synaptic tree is fed by a regenerative clock. Whilst the weights are fixed in this case, developments into memcapacitor technology offer the promise of tuneability in the future. In our example, a 4-synapse design was used as a proof-of-concept baseline at various frequencies. Our simulation at 1 MHz indicates a æ 91% reduction of energy when using Regenerative Capacitive Synapses vs. standard, nonregenerative ones, which translates into a æ 35% drop in overall artificial neuron energy dissipation. The higher the ratio of synapses/soma, the higher the power savings, which is important for building larger and more complex neurons in silico.

Adiabatic logic is an energy-efficient technique, however, the time required in the design, validation, and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a hardware description language (HDL)-based modeling approach for 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that captures the timing errors and detects the circuit's invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the proposed approach were done on the ISO-14443 standard benchmark circuit, a 16-bit cyclic redundancy check (CRC) circuit. The system modeled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability for the design and verification of large adiabatic systems.

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.

Energy plays an important role in NFC passive tags as they are powered by radio waves from the reader. Hence reducing the energy consumption of the tag can bring large interrogation range, increase security and maximizes the reader's battery life. The ISO 14443 standard utilizes Manchester coding for the data transmission from passive tag to the reader in the majority of the cases for NFC passive communications. This paper proposes a novel method of Manchester encoding using the adiabatic logic technique for energy minimization. The design is implemented by generating replica bits of the actual transmitted bits and then flipping the replica bits, for generating the Manchester coded bits. The proposed design was implemented using two adiabatic logic families namely; Positive Feedback Adiabatic Logic (PFAL) and Improved Efficient Charge Recovery Logic (IECRL) which are compared in terms of energy for the range of frequency variations. The energy comparison was also made including the power-clock generator designed using 2-stepwise charging circuit (SWC) with FSM controller. The simulation results presented for 180nm CMOS technology at 1.8V power supply shows that IECRL shows approximately 40% less system energy compared to PFAL family.