Demo Data from EDBT 2026 / reviewers in the wild / expert
Frédéric Didier
dblp:99/1444
· DBLP profile ↗
10ranked-venue papers
3as first author
4since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 4 · 3 since 2021Theory of computation · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 2 · 1 first-authorSystems, architecture and hardware · 1 · 1 since 2021Security and privacy · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% | |
| Theoretical computer science
2 papers |
Automated reasoning and model checking · 94% Coding theory · 6% | |
| Network and information security
1 paper |
Cryptographic protocols and secure computation · 100% |
Topics — the 8 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.9 | 1 | 2025 | TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell Methodology · DAC 2025 |
Electronic design automation › physical design
placement |
0.9 | 1 | 2025 | TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell Methodology · DAC 2025 |
Electronic design automation › physical design
routing |
0.9 | 1 | 2025 | TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell Methodology · DAC 2025 |
Electronic design automation › physical design › cell layout
transistor placement |
0.9 | 1 | 2025 | TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell Methodology · DAC 2025 |
Automated reasoning and model checking › satisfiability
maximum satisfiability |
0.2 | 1 | 2015 | Exploiting the Structure of Unsatisfiable Cores in MaxSAT · IJCAI 2015 |
Automated reasoning and model checking › satisfiability
MaxSAT solving |
0.2 | 1 | 2015 | Exploiting the Structure of Unsatisfiable Cores in MaxSAT · IJCAI 2015 |
Automated reasoning and model checking › satisfiability
unsatisfiable cores |
0.2 | 1 | 2015 | Exploiting the Structure of Unsatisfiable Cores in MaxSAT · IJCAI 2015 |
Coding theory
network coding |
0.0 | 1 | 2012 | Invertible Extractors and Wiretap Protocols · IEEE Trans. Inf. Theory 2012 |
Methods — techniques the papers use, named apart from their topics
constraint programming · 0.9SAT · 0.9symbol-fixing sources · 0.3randomness extraction · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Parallelising Lazy Clause Generation with Trail Sharing
Toby O. Davies, Frédéric Didier, Laurent Perron, Peter J. Stuckey |
CPAIOR (1) | 2 |
| 2025 | TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell MethodologyabstractIn advanced technology nodes, benefits from scaling have become limited in terms of power, performance, and area (PPA), necessitating improvements through design-technology cooptimization (DTCO). While the standard-cell methodology is widely used in modern VLSI design, it inherently constrains the potential of DTCO due to its abstraction at the logic level, limiting optimization at the physical level. To bridge this gap, transistor-level design methodology is desired to break the abstraction of standard cells. Existing research has explored large-scale transistor placement, but a gap remains in developing a routing framework that efficiently addresses transistor-level routing challenges. This paper proposes a pioneering transistorlevel routing framework for large-scale transistor placements, along with an efficient CP-SAT (Constraint ProgrammingSATisfiability) formulation for routing in lower layers. Experimental results demonstrate that the proposed routing framework enables transistor-level designs to achieve significantly reduced total wirelength and high utilization rates for designs with hundreds to thousands of transistors, outperforming traditional standard-cell-based approaches in advanced technology nodes. Chen-Hao Hsu, David Z. Pan, Laurent Perron, Frédéric Didier, Hao Chen 0059 |
DAC | 4 |
| 2024 | ViolationLS: Constraint-Based Local Search in CP-SAT
Toby O. Davies, Frédéric Didier, Laurent Perron |
CPAIOR (1) | 2 |
| 2023 | The CP-SAT-LP Solver (Invited Talk)
Laurent Perron, Frédéric Didier, Steven Gay |
CP | 2 |
| 2015 | Exploiting the Structure of Unsatisfiable Cores in MaxSAT
Carlos Ansótegui, Frédéric Didier, Joel Gabàs |
IJCAI | 2 |
| 2012 | Invertible Extractors and Wiretap ProtocolsabstractA wiretap protocol is a pair of randomized encoding and decoding functions such that knowledge of a bounded fraction of the encoding of a message reveals essentially no information about the message, while knowledge of the entire encoding reveals the message using the decoder. In this paper, the notion of efficiently invertible extractors is studied and it is shown that a wiretap protocol can be constructed from such an extractor. Then, invertible extractors for symbol-fixing, affine, and general sources are constructed and used to create wiretap protocols with asymptotically optimal trade-offs between their rate (ratio of the length of the message versus its encoding) and resilience (ratio of the observed positions of the encoding and the length of the encoding). The results are further applied to create wiretap protocols for challenging communication problems, such as active intruders who change portions of the encoding, network coding, and intruders observing arbitrary Boolean functions of the encoding. Mahdi Cheraghchi, Frédéric Didier, Amin Shokrollahi 0001 |
IEEE Trans. Inf. Theory | 2 |
| 2011 | Approximation of event probabilities in noisy cellular processes
Frédéric Didier, Thomas A. Henzinger, Maria Mateescu, Verena Wolf 0001 |
Theor. Comput. Sci. | 1 |
| 2009 | Invertible extractors and wiretap protocolsabstractA wiretap protocol is a pair of randomized encoding and decoding functions such that knowledge of a bounded fraction of the encoding of a message reveals essentially no information about the message, while knowledge of the entire encoding reveals the message using the decoder. In this paper we study the notion of efficiently invertible extractors and show that a wiretap protocol can be constructed from such an extractor. We will then construct invertible extractors for symbol-fixing, affine, and general sources and apply them to create wiretap protocols with asymptotically optimal trade-offs between their rate (ratio of the length of the message versus its encoding) and resilience (ratio of the observed positions of the encoding and the length of the encoding). We will then apply our results to create wiretap protocols for challenging communication problems, such as active intruders who change portions of the encoding, network coding, and intruders observing arbitrary boolean functions of the encoding. Mahdi Cheraghchi, Frédéric Didier, Amin Shokrollahi 0001 |
ISIT | 2 |
| 2007 | Finding low-weight polynomial multiples using discrete logarithmabstractFinding low-weight multiples of a binary polynomial is a difficult problem arising in the context of stream ciphers cryptanalysis. The best algorithms to solve this problem are based on a time memory tradeoff. Staying in this category, we will present a new approach using discrete logarithm rather than a direct representation of the involved polynomials. This provides an alternative to the previously known algorithms which improves in some case the computational complexity. Frédéric Didier, Yann Laigle-Chapuy |
ISIT | 1 |
| 2006 | Computing the Algebraic Immunity Efficiently
Frédéric Didier, Jean-Pierre Tillich |
FSE | 1 |