Over the years, interest in computational storage devices has been growing steadily. This is largely due to the rise of data-intensive applications, such as machine learning, online video distribution, astrophysics, and genomics. Moving compute operations closer to the data provides benefits in terms of scaling possibilities and energy efficiency. The development of computational storage devices has been limited by the need for specialized and complex hardware. In this work, we propose a portable Linux-based firmware framework for the development of NVMe computational storage devices. Our firmware runs on a variety of hardware platforms ranging from expensive FPGA solutions to inexpensive off-the-shelf single board computers. The firmware leverages the vast Linux software ecosystem to facilitate the development and prototyping of novel computational storage devices. We benchmark our firmware on multiple hardware platforms and demonstrate its versatility through several computational examples including a content-aware disk image search engine based on natural language processing and AI-driven image recognition.

We introduce giotto-tda, a Python library that integrates high-performance topological data analysis with machine learning via a scikit-learn-compatible API and state-of-the-art C++ implementations. The library's ability to handle various types of data is rooted in a wide range of preprocessing techniques, and its strong focus on data exploration and interpretability is aided by an intuitive plotting API. Source code, binaries, examples, and documentation can be found at https://github.com/giotto-ai/giotto-tda.

In this demo we propose an automated flow that allows the transparent execution of ordinary code on a heterogeneous platform including an FPGA. Our solution requires no change in the code, not even pragma indications to guide the optimization, and dynamically adapts its behaviour to the available data and the workload of the system. Thus, the developer does not need to be aware of the target platform details, nor she has to forecast usage patterns to prevent performance bottlenecks, as the system transparently identifies parallelizable, computationally-intensive code fragments and dispatches them to a data flow overlay architecture built on top of the FPGA. Since the bitstream we use is fixed, and contrary to HLS, we can alter the functionalities offered by the FPGA on-the-fly to adapt them to current usage. Finally, since we operate at the LLVM's Intermediate Representation (IR) level, our approach is language-agnostic.

In this paper we propose a novel parallel hardware architecture for two binary matrix inversion and vector decoding algorithms, for hard Raptor decoder. We compare the achieved performance to a software based implementation in an embedded processor. We demonstrate the superiority of our proposed architecture in terms of performance (by a factor 12), power and energy dissipation (by a factor of 15). We also include the hardware resource requirements in the comparison. Furthermore, the proposed hardware architecture is parameterized and easily scalable. The data processing word size has been successfully extended up to 1024 bits and fitted within the chosen FPGA hardware platform.

Modern wireless systems have to achieve very high data rates over noisy channels. Channel codes are usually used to guarantee reliable communication, but validating a system with extremely low Bit Error Rate (BER) requires the simulation of a huge number of samples. The simulation complexity furtherly increases if we want to take into account the joint effect of channel codes and complex modulation techniques, such as Orthogonal Frequency Division Multiplexing (OFDM), over multi-path fading channel. The use of software simulators to evaluate system performance in several scenarios may result in unacceptably long times and a reconfigurable hardware prototyping environment may be an effective solution. This paper describes the implementation of a complete real-time, fully digital, flexible high performance hardware/software prototype for beyond 3G wireless communications. The transmitter/receiver chain includes several innovative characteristics: Serial Concatenated Convolutional Codes (SCCC) Turbo Encoder/Decoder, adaptive OFDM modulation, versatile multiple user access scheme and a sophisticated, real-time power control.Optimal choices for partitioning and internal data representation have been described as well as internal architecture and measurement environment. Our programmable prototype ensures high flexibility and speedup of more than 4000 times compared with the software version.

During the last years wireless market has experienced an exponential growth. 2G systems are essentially voice-oriented: the main innovation expected from 3G ones is the ubiquitous Internet and multimedia fruition. The transition from 2G to 3G provides both opportunities and challenges: one way to make this migration as smoother as possible relies on the employment of reconfigurable architectures. In this paper a reconfigurable Rake Receiver for W-CDMA is proposed. Very promising results from the physical implementation on a XCV300E have been obtained.