This paper investigates the extent to which the geographical region (country) where a speaker acquired their English language affects the articulatory setting in their speech.To obtain accurate measurements for evaluating articulatory setting, we utilized a large real-time MRI corpus of vocal tract articulation.The corpus was obtained from speakers from a variety of linguistic backgrounds producing continuous English speech.We use an automated pipeline to process and extract articulatory positional information from the MRI video data.This data is used to draw comparisons between English language speakers from the United States and speakers who acquired their English in India, Korea, and China.Analysis of the speaker groups reveals statistically significant articulatory setting posture differences in multiple places of articulation.

A memory organization is considered for which a large number of faults can be tolerated at a low cost in redundancy. The primitive element in the memory is a large-scale integrated (LSI) chip that realizes a section of memory, b bits wide by y words long, together with an address decoder for the y words. The chips (including spares) are connected via a switching network so that the memory can be reconfigured effectively in the presence of chip failures. The main results of the paper relating to the switching network are as follows.

This paper is a survey of the open Soviet literature in the technical areas relevant to the design of complex digital systems that must exhibit a high degree of reliability. Particular emphasis is on the various techniques for the constructive application of redundancy in order to achieve the reliability necessary for the successful realization of machines of high computational power and high availability. Overall conclusions are drawn regarding the nature and significance of Soviet activities in these fields. The rather extensive bibliography upon which these observations are based is included as a stimulus and aid in further research and inquiry into the results already available in these technical areas.

This paper proposes a method, termed antiparallel control logic, for the control and efficient utilization of computer networks that exhibit substantial propagation delays on the lines interconnecting the logical elements, as well as in the elements themselves. The discussion encompasses the basic behavior of antiparallel stages that realize this method of control, including their logical realization and their extension to other useful network logic structures. In a strictly feedforward line, where the stored data are indexed forward by control pulses moving in a direction away from the data source, the existence of time variations in the delays of successive stages implies a nonzero probability that two successive control pulses will eventually appear at the inputs to a given stage so closely spaced that the basic reaction time of the stage is violated. The result is a failure of the transfer mechanism and a consequent loss of information. If feedback control is provided such that control pulses move in a direction opposite to the flow of information, that is, if the control and information flows are antiparallel, then the failure of the transfer mechanism does not cause an overlap in the information stored on the line, but rather leaves a void, or hole, which does not imply necessary information loss nor physically unrealizable storage requirements on the individual stages.