Demo Data from EDBT 2026 / reviewers in the wild / expert
Frédéric Reblewski
dblp:99/2590
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
fault emulation |
0.0 | 1 | 1996 | Serial Fault Emulation · DAC 1996 |
Electronic design automation
hardware emulation |
0.0 | 1 | 1996 | Serial Fault Emulation · DAC 1996 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1996 | Serial Fault Emulation · DAC 1996 |
Methods — techniques the papers use, named apart from their topics
serial fault emulation · 0.0hardware emulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Serial Fault EmulationabstractA hardware emulator based approach has been developed to perform test evaluation on large sequential circuits (at least tens of thousands of gates).This approach relies both on the flexibility and on the reconfigurability of hardware emulators based on dedicated reprogrammable circuits.A Serial Fault Emulation (SFE) method in which each faulty circuit is emulated separately has been applied to gate-level circuits for Single Stuck Faults (SSFs).This approach has been implemented on the Meta Systems's hardware emulator which is capable of emulating circuits of 1,000,000 gates at rates varying from 500KHz to several MHz.Experimental results are provided to demonstrate the efficiency of SFE.They indicate that SFE should be two orders of magnitude faster than software approaches for designs containing more than 100.000gates. Luc Burgun, Frédéric Reblewski, Gérard Fenelon, Jean Barbier, Olivier Lepape |
DAC | 2 |