In this paper, we present a framework called Web service based collaborative product commerce (WSCPC), which facilitates design and manufacturing process integration and coordination. In WSCPC, the design and manufacturing process is structured as a network of tasks. Companies can outsource a task, and join a process by providing their service. We propose an ontology based semantics using OWL-S to represent design and manufacturing activities as services. Manufacturing companies are able to publish their capabilities and identify potential manufacturing partners at the same time. We also present service models to support collaboration, which is based on Web ontology. Web ontology enables collaborative partners to understand each other's manufacturing decisions and behaviors, and hence help generate an optimal solution. We define interactions among companies during a process using a conversation model to support complex interactions necessary for flexible process management.

This paper presents a novel Web-based service-oriented framework to support collaborative product commerce. The framework coordinates processes to design and manufacture a product in a loosely coupled environment using Web services. We have developed a service model using OWL. It provides facilities for companies to discover services that other companies provide. Choreography of Web services is achieved using the process grammar. Usage of process grammar helps to configure processes dynamically, facilitating collaboration among companies. The framework, therefore, provides a truly distributed architecture for management of service composition and interoperation, lending a unique functionality to the framework.

We develop a model to predict the performance of synchronous discrete event simulation. Our model considers the two most important factors for the performance of synchronous simulation: load balancing and communication. The effect of load balancing in a synchronous simulation is computed using probability distribution models. We derive a formula that computes the cost of synchronous simulation by combining a communication model called LogGP and computation granularity. Even though the formula is simple, it is effective in capturing the most important factors for the synchronous simulation. The formula helps us to predict the maximum speed up achievable by synchronous simulation. In order to examine the prediction model, we have simulated several large ISCAS logic circuits and a simple PCS network simulation on an SGI Origin 2000 and Terascale Computing System (TCS) at the Pittsburgh Supercomputing Center. The results of the experiment show that our performance model accurately predicts the performance of synchronous simulation. The performance model developed is used to analyze the effect of several factors that may improve the performance of synchronous simulation. The factors include problem size, load balancing, granularity, communication overhead, and partitioning.

In this paper we propose a model to predict the performance of synchronous discrete event simulation. The model considers parameters including the number of active objects per cycle, event execution granularity and communication cost. We, derive a single formula that predicts the performance of synchronous simulation. We have benchmarked several VHDL circuits on SGI Origin 2000. The benchmark results show that the prediction model explains more than 90% of parallel simulation execution time. We also measure the effect of computation granularity over performance. The benchmark results show that although higher granularity can have better speedup because of dominance of computation over communication, the computational granularity cannot overshadow the inherent synchronization cost. This model can be used to predict the speed-up expected for synchronous simulation, and to decide whether it is worthwhile to use synchronous simulation before actually implementing it.

The problem of extracting RTL modules from a gate level netlist has many interesting applications in digital design (V.K. Madiseti, 1999; P. Schaumont et al., 1999; K. Singh and P. Subrahmunyam, 1995), because it provides a conceptual description of the circuit. We approach this transformation by solving two subproblems: the identification of potential modules (candidate subcircuits) and testing them for functional equivalence to known high-level modules (subcircuit identification). We present a technique for unique and comprehensive enumeration of subgraphs of an arbitrary graph, as well as a method of recognizing subgraph isomorphisms. Combined, these results provide a solution to the problem of candidate subcircuit enumeration. These techniques provide both theoretical and practical contributions within design automation and graph theory.

Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable information available about a piece of digital hardware is the hardware itself. Documentation, even if it is available, may be outdated or incorrect. Existing procedures are able to recover the transistor-level netlist, or a gate-level netlist from an existing implementation. The next step in this process is the gate-level to module-level transformation, the focus of this paper. We have designed a technique to enumerate all of the potential modules within a gate-level netlist so that their functional equivalence to known modules may be evaluated.

Motivated by the problem of reengineering legacy digital circuits for which design information is missing or incomplete, this paper presents a new technique for representing the relationships among the internal components of a combinational circuit. This technique proves to be a powerful tool for redesign, capable of representing internal Boolean relationships in a fully or partially specified multiple-output combinational circuit with a single data structure.

Article Analysis of a scheduler for a CAD framework Share on Authors: David S. Keyes Picker International, Inc. World Headquarters, 595 Miner Road, Cleveland, OH Picker International, Inc. World Headquarters, 595 Miner Road, Cleveland, OHView Profile , Laura K. Dillon Department of Computer Science & Engineering, 3115 Engineering Building, Michigan State University, East Lansing, MI Department of Computer Science & Engineering, 3115 Engineering Building, Michigan State University, East Lansing, MIView Profile , Moon Jung Chung Department of Computer Science & Engineering, 3115 Engineering Building, Michigan State University, East Lansing, MI Department of Computer Science & Engineering, 3115 Engineering Building, Michigan State University, East Lansing, MIView Profile Authors Info & Claims ICSE '99: Proceedings of the 21st international conference on Software engineeringMay 1999 Pages 152–161https://doi.org/10.1145/302405.302461Online:16 May 1999Publication History 2citation192DownloadsMetricsTotal Citations2Total Downloads192Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

We present a new class of interconnection topologies called the Linear Recursive Networks (LRNs) and examine their possible applications in distributed systems. Each LRN is characterized by a recursive pattern of interconnection which can be specified by simple parameters. Basic properties such as node degree, diameter, and the performance of routing algorithms for all LRNs are then collectively analyzed in terms of these parameters. By choosing appropriate values for the parameters, our results can assist a network designer in selecting a topology with required routing performance and cost of interconnection. A subclass of LRNs, called Congruent LRNs (CLRNs), is also identified here and shown to possess desirable properties for more tightly coupled systems. It is shown that the CLRNs include existing networks such as hypercube and generalized Fibonacci cubes. These results suggest that the linear recursive networks potentially have applications in interconnecting distributed systems.

The interconnection topology of a network plays a key role in determining the performance and cost of routing messages in the system. Presently, there are many known results about individual network topologies and their applications. However, relatively few results exist about the relations among these topologies; for instance, it is rather difficult to relate quantitatively the cost of interconnection with the routing efficiency. As such, the theory is incomplete for assisting a designer to choose a suitable topology for a required routing performance under a given cost of interconnection. Here, by extending the popular hypercube, a family of parameterized network topologies called Gaussian Cubes (GCs) is presented. By varying the parameter that controls the interconnection density, the routing performance of a GC can be scaled according to the traffic loads without changing the routing algorithm. It is demonstrated that these new networks can approximate the concurrent offered by hypercubes while lowering the cost of interconnection; common communication primitives such as Unicast, Multicast and Broadcast can all be supported efficiently on GCs. Therefore, the new network topologies can be applied to distributed systems with scalable messaging performance. Because GCs are also subgraphs of the conventional hypercubes, our results may also be useful to fault-tolerant computing based on hypercubes.

An algorithm for the cell selection problem is presented. Given a network G of logic gates, the problem is to select a library cell for each gate such that the longest delay through G is at most T/sub max/ and the total area of selected cells is minimum. We first prove the strong NP-completeness of the problem if the circuit is a general acyclic graph. The proof implies that there exists no pseudopolynomial time algorithm unless P=NP. We next propose a path-oriented, heuristic algorithm that iteratively chooses paths of gates with delay larger than T/sub max/, and then selects cells for the paths. The set of paths chosen induces a series-parallel subgraph. We also present a cloning method which further improves a solution obtained by the path-oriented algorithm. In the proposed cloning method, nodes are duplicated into clones such that the resulting graph becomes a series-parallel graph. Our cloning method is more efficient in terms of time and space than the tree cloning of Chan (1990). The results of our algorithm are compared to those Lin et al. (1990). The algorithm provides significantly better solutions to all the circuits than the previous work.>

In this paper, we present a design methodology management system, which assists designers in selecting a suitable design process and invoking the selected sequence of tools on the correct versions of design data.We i n troduce a formal graph representation of design methodologies in which nodes represent either tasks or design data.Using a graph grammar, nodes representing abstract tasks are replaced by graphs of less abstract tasks and intermediate speci cations.Graph grammars enable us to concisely and exibly describe a large class of methodologies.Often there are several alternative methodologies or tools available for some subtasks, leading to dierent results.Our system utilizes automated control agents, in combination with user interaction, to select among methodologies and invoke tools.Multiple alternatives can easily be explored simultaneously.

Multiple sequence alignment is a useful technique for studying molecular evolution and analyzing structure-sequence relationships. Dynamic programming of multiple sequence alignment has been widely used to find an optimal alignment. However, dynamic programming does not allow for certain types of gap costs, and it limits the number of sequences that can be aligned due to its high computational complexity. The focus of this paper is to use simulated annealing as the basis for developing an efficient multiple sequence alignment algorithm. An algorithm called Multiple Sequence Alignment using Simulated Annealing (MSASA) has been developed. The computational complexity of MSASA is significantly reduced by replacing the high-temperature phase of the annealing process by a fast heuristic algorithm. This heuristic algorithm facilitates in minimizing the solution set of the low-temperature phase of the annealing process. Compared to the dynamic programming approach, MSASA can (i) use natural gap costs which can generate better solution, (ii) align more sequences and (iii) take less computation time.

We present a new class of interconnection topolo gies called the generalized Fibonacci cubes (GFCs, for short) that encompass a range of networks such as the popular Boolean cube (hypercube) and the recent second-order Fibonacci cube in [5]. We show that each GFC has a recursive and self-similar structure and hence exhibits fault tolerant features. We also show that each GFC admits simple embedding of other useful net works such as cycles, trees, and meshes. The GFCs may find applications in fault-tolerant com puting.

We present a new class of interconnection topologies called the Linear Recursive Networks. It is shown that each member of this fairly large class of network topologies possesses a recursively-decomposable structure. The path and connectivity properties of the entire class of networks are analyzed and found to have useful features. It is also demonstrated that Point-To-Point or Broadcasting/Gathering operations can be performed efficiently on all Linear Recursive Networks. The preliminary results suggest that the Linear Recursive Networks potentially have many applications.

The authors present a constraint-driven, object-oriented approach to configuration management within a VHDL design environment called SDE. A configuration is generated from a generic design in such a way that technology-specific cells are bound to the generic components of the design. In the approach, user-defined constraints are exploited to efficiently organize versions and to generate workable configurations. They are also used for providing the formal definitions of various relationships between cells, making it possible to easily explore versions of a configuration by substituting other cells with a certain relationship, e.g., replaceability, for its already bound cells. To retrieve cells that satisfy constraints for a configuration to be generated, the authors suggest an object-oriented query model based on a graph model.>

Techniques are proposed for computing a global virtual time (GVT), which is the minimum local virtual time of processes in Time Warp. The algorithm computes a conservative estimate of GVT using an approach which is considerably simpler than previous algorithms for computing GVT. This algorithm does not require a global synchronization of processors. An inherent problem is GVT computation relates to handling messages in transit. Several alternatives are proposed for solving the transient message problem. The algorithm is suitable for distributed shared memory machines such as the BBN Butterfly and message passing machines with a variety of interconnection networks.>

A system-level design environment (SDE) for the VHSIC hardware description language (VHDL) is presented. The object-oriented approach is used for modeling the VHDL entities, design constraints, and even design patterns. The data model and its internal schema, which are suitable for the VHDL semantics, are proposed. SDE allows a designer to reconfigure the designed schematic by binding its generic components to technology-specific ones. It is effectively used for version control. SDE verifies the design by dynamically checking the constraints. The standard VHDL is extended in order to represent the constraints properly. >

Three efficient parallel logic simulation techniques for the Connection Machine are developed. The first technique which uses a global clock, is a synchronous version of a traditional simulation technique. The second technique is a hybrid of both the synchronous simulation technique with a global clock and the Chandy-Misra algorithm for asynchronous event processing. The third technique, called a simulation time lookahead technique, is proposed to make the second technique more optimistic than the Chandy-Misra algorithm by predicting in advance the timestamp of the next event. Experimental results show that the three techniques achieve better performance than the Time Warp protocol on the Connection Machine. The proposed techniques are several hundred times faster than the VHDL simulator on a SUN3, especially for circuits with very large number of gates.>

A new data parallel simulation technique of Time-Warp on the Connection Machine is presented. Our scheme handles the rollback problem of Time-Warp efficiently, and maximizes data parallelism, where the parallelism is extracted from simultaneous evaluation of different circuit elements. Each event is assigned to one of the processors of the Connection Machine to achieve high data parallelism. A new scheme to reduce space overhead in Time-Warp is proposed.

Systolic tree architectures are presented for data structures such as stacks, queues, dequeues, priority queues, and dictionary machines. The stack, queue, and dequeue have a unit response time and a unit pipeline interval. The priority queue also has a unit response time, but the pipeline interval is 2. The response time and pipeline interval for the dictionary machine are O(log n) and O(1), respectively, where n is the number of data elements currently residing in the tree. In each node of the tree, the mechanism for controlling the transmission and distribution of data is finite state. This feature makes the designs presented here suitable for VLSI. If there are n data elements in the data structure, the depth of the tree is O(log n).>

Polynomial algorithms are described that solve the MIN CUT LINEAR ARRANGEMENT problem on degree restricted trees. For example, the cutwidth or folding number of an arbitrary degree d tree can be found in $O(n(\log n)^{d - 2} )$ steps. This has applications to integrated circuit layout, in particular the layout of Weinberger arrays [41]. This also yields an algorithm for determining the black/white pebble demand of degree three trees. We also show that for degree three trees, cutwidth is identical to search number and give a forbidden subgraph characterization of degree three trees having cutwidth k.

This paper presents the study of an adaptive control which tracks a desired time-based trajectory as closely as possible for all times over a wide range of manipulator motion and payloads both in joint-variable coordinates and Cartesian coordinates. The proposed adaptive control is based on the linearized perturbation equations in the vicinity of a nominal trajectory. The controlled system is characterized by feedforward and feedback components which can be computed separately and simultaneously. The feedforward component computes the nominal torques from the Newton-Euler equations of motion either using the resolved joint information or the joint information from the trajectory planning program. This computation can be completed in O(n) time. The feedback component consisting of recursive least square identification and one-step optimal control algorithms for the linearized system computes the variational torques in O(n3) time. Because of the parallel structure, the computations of the adaptive control may be implemented in low-cost microprocessors. A computer simulation study was conducted to evaluate the performance of the adaptive control in joint-variable coordinates for a three-joint robot arm. The feasibility of implementing the adaptive control in Cartesian coordinates using present day low-cost microprocessors is discussed.

Polynomial algorithms are described that solve the MIN CUT LINEAR ARRANGEMENT problem on degree restricted trees. For example, the cutwidth or folding number of an arbitrary degree d tree can be found in O(n(logn)d-2) steps. This also yields an algorithm for determining the black/white pebble demand of degree three trees. A forbidden subgraph characterization is given for degree three trees having cutwidth k. This yields an interesting corollary: for degree three trees, cutwidth is identical to search number.