Since Lucent Technologies (formerly AT&T) launched the Built-In Self-Test/Boundary-Scan (BIST/B-S) program in mid 1980's, over 200 devices and 80 circuit packs have incorporated BIST/B-S. These are from over 25 different project areas in various business units including Switching, Transmission, Wireless, Micro-Electronics, Federal Systems, and Consumer Products. Furthermore, since the early 1990's we have begun to see the full life-cycle impact of BIST and Boundary-Scan as a large quantity of hardware with BIST/B-S has gone full-cycle from design through manufacturing. We expect the steady growth in designs with BIST/B-S to continue and feel that the time is right to share our experiences and lessons learned from all levels: device, board, and system.

The four (five) wires defined in IEEE Std 1149.1 can be extended to the backplane to form a test bus that provides a linkage between 1149.1 boards and the backplane environment. This test architecture has many advantages. However, one of the disadvantages is its inability to detect errors that may occur during backplane data transmission and to protect the boards-under-test from unsafe corrupted data. In this paper, we propose a novel scheme to address these issues. The concept is first described, then followed by implementation examples. As a result of its simplicity and flexibility, the proposed scheme can be implemented in different ways to suit specific application needs.

The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture Standard can be used at many different levels in the integration hierarchy of a product. However there is one level where using the standard poses some difficulty. This is multi-chip modules (MCM). This paper explores the problem and proposes a set of solutions for different classes of MCMs.

This paper proposes a framework for testing and diagnosing in-sys,tem, IEEE Std 1149.1 compliant boards. It defines the mechanisms used to describe, store, execute the tests, perform diagnosis, and the interface to the system diagnostician. Using, BIST and Boundary-Scan in-system makes it possible to achieve high test quality, comparable to that achieved during board test. Diagnostic accuracy and resolution can also be enhanced.

A board-level test strategy based on ANSIhEEE Std 1149.1-1990 is presented. A essential component of tlhis strategy is an intelligent parallel-serial protocol conviersion dievice-the Boundary-Scan Master (BSM). With the BSM, we can rapidly realize generic board level Built., In Self-Test (BIST) with a minimal amount of effort.

The need for a parallel-serial bus interface chip (BSM) which supports the boundary-scan architecture is demonstrated. Various external and embedded applications for the BSM are identified. The external applications include low-cost testers and other trouble-shooting instruments, such as in-circuit emulators. The embedded applications encompass board- and system-level test and diagnostic support functions. For the embedded applications, further distinction is made between centralized and distributed test and diagnostic control mechanisms. A comprehensive list of requirements which support the BSM's target applications is specified. A subset of the requirements is defined after a detailed design tradeoff analysis. It is demonstrated that, with the final feature set the BSM is able to meet the cost-performance, goals dictated by the anticipated applications.>

A novel framework for analyzing test generation and diagnosis algorithms for wiring interconnect are presented. A property of test vector sets, called diagonal independence, which guarantees the diagnostic resolution of the vector test set is identified. The failing responses or syndromes are classified into aliasing and confounding syndromes, and this classification permits precise analysis of the diagnostic capabilities of different test algorithms. Using this framework, all the algorithms that have been proposed for board interconnect testing are analyzed. Their capabilities and limitations are clearly defined. A new optimal adaptive algorithm that can reduce test and diagnosis complexity is also presented.>

It is noted that, to test wiring interconnects in a printed circuit board, especially one equipped with boundary-scan devices, it is important to minimize the test size while maintaining diagnostic capability. This has provided the motivation for research work that explores efficient test generation and diagnosis algorithms. The authors propose a unified theory for designing various types of interconnect test algorithms. They demonstrate that the algorithms proposed in the literature are special cases of the general algorithms given in the present work. The new algorithms are shown to be optimal or near optimal for a given set of design and process parameters. They increase the designer's flexibility by offering a full range of solutions (i.e., test vector sets) based on various tradeoff criteria, such as test compactness and diagnostic accuracy. Parameters for quantifying the quality of the tests are described. The significance and limitations of the proposed algorithms are also discussed.>

An architecture is proposed for multimegabit dynamic RAMs (random-access memories) that achieves higher testability and performance than the conventional four-quadrant RAMs. Applying the principle of divide and conquer, the RAM is partitioned into modules, each appearing as the leaf node of a binary interconnect network. Such a network carries the address/data/control bus, permitting the nodes to communicate among themselves as well as with the outside world. This architecture is shown to be easily testable. Parallelism in testing and partial self-test result in a large savings of testing time; the savings is independent of the test algorithm used. Unlike other testability schemes, this approach promises improved performance with only a small increase in chip area. It is also shown that the architecture is easily partionable and restructurable, with potential for yield and reliability improvement.>