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C. Laurent

dblp:99/2754 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 56% Hardware accelerators and domain-specific architectures · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › signal processing accelerator
DCT processor
0.011999
High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA · FPGA 1999
Reconfigurable computing and FPGAs
FPGA accelerator
0.011999
High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA · FPGA 1999
Reconfigurable computing and FPGAs
FPGA implementation
0.011999
High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA · FPGA 1999
YearPublicationVenuePosition
1999 High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA
abstract
No abstract available.
Lirida A. B. Naviner, Jean-Luc Danger, C. Laurent
FPGA3
1998 Parallel Image Reconstruction on MIMD Computers for Three-Dimensional Cone-Beam Tomography
C. Laurent, Françoise Peyrin, Jean-Marc Chassery, M. Amiel
Parallel Comput.1