This paper proposes split shared-bus architecture to reduce the energy dissipation for global data exchange among a set of interconnected modules. The bus splitting problem for minimum energy is formulated as a minimum-exchange bus split problem, which is shown to be NP-complete. The problem is solved heuristically by using a maximum-weight matching algorithm and combinatorial search. Experimental results show that the energy saving of split-bus architecture compared to monolithic-bus architecture varies from 16% to 50%, depending on the characteristics of the data transfer among the modules and the configuration of the split-bus. The proposed split-bus architecture can be extended to multiway split-bus architecture when large numbers of modules are to be connected.

In many applications, it is important to know how power is consumed while software is being executed on the target processor. Instruction-level power microanalysis, which is a cycle-accurate simulation technique based on instruction label generation and propagation, is aimed at answering this question for a superscalar and pipelined processor. This technique requires the micro-architectural details of the CPU and provides the power consumption of every module (or gate) for each active instruction in each cycle. To validate this approach, a Zilog digital signal processor core was designed by using a 0.25 /spl mu/ TSMC cell library, and the power consumption per instruction was collected using a Verilog simulator specially written for the DSP core.

A split-bus architecture is proposed to improve the power dissipation for global data exchange among a set of modules. The resulting bus splitting problem is formulated and solved combinatorially. Experimental results show that the power saving of the split-bus architecture compared to the monolithic-bus architecture varies from 16% to 50%, depending on the characteristics of the data transfer among the modules and the configuration of the split bus. The proposed split-bus architecture can be extended to multi-way split-bus when a large number of modules are to be connected.

This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that captures both sizing and buffering effects is presented. Next, the optimization problem is formulated as a non-convex mathematical program. To manage the problem size, only a small number of critical paths are considered simultaneously. The mathematical program is solved by a non-linear programming package. Finally, a design flow based on iterative selection and optimization of the k most critical paths in the circuit is proposed. Experimental results show that the proposed flow reduces the circuit delay by an average of 9.2% compared to conventional flows that separate gate sizing from fanout optimization.

This paper presents an iterative optimization technique for improving delay in integrated circuits. The basic idea is to perform timing analysis to identify the set of k most-critical paths in the circuit followed by cell resizing and replacement along the critical path set and their neighboring cells. The process is repeated until no further reduction in circuit delay is possible. At the core of this technique lies a mathematical formulation for simultaneous cell sizing and placement subject to timing and position constraints. We show that the resulting problem formulation is a generalized geometric program, which can be solved by solving a sequence of geometric programs. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement.

In this paper, we propose two efficient statistical sampling techniques for estimating the total power consumption of large hierarchical circuits. We first show that, due to the characteristic of the sampling efficiency in Monte Carlo simulation, granularity of samples is an important issue in achieving high overall efficiency. The proposed techniques perform sampling both temporally (across different clock cycles) and spatially (across different modules) so that a smaller sample granularity can be achieved while maintaining the normality of samples. The first proposed technique, which is referred to as the module-based approach, samples each module independently when forming a power sample. The second technique, which is referred to as the cluster-based approach, lumps the modules of a hierarchical circuit into a number of clusters on which sampling is then performed. Both techniques adapt stratification to further improve the efficiency. Experimental results show that these techniques provide a reduction of 23/spl times/ in simulation run time compared to existing Monte-Carlo simulation techniques.

In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing.We use a path-based delay model to capture the timing constraints in the circuit.To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the k-most critical paths in the circuit and their neighboring cells.All the operations are formulated and solved as mathematical programming problems by using eflcient solution techniques.Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches, which separate gate sizing from gate placement.

In this paper, we propose an efficient statistical sampling technique which is suitable for estimating the total power consumption of a large VLSI system. The basic idea is to generate simulation units for each module in the system independently and then form samples of the system power by randomly selecting simulation units for each module. Hence, sampling is performed both temporally (across different clock cycles) and spatially (across different modules). A module clustering step ensures that the module types are compatible with this sampling strategy. Experimental results show a 4x reduction in the simulation time compared to existing Monte-Carlo simulation techniques.

In this paper, we present new statistical sampling techniques for performing power estimation at the circuit level. These techniques first transform the power estimation problem to a survey sampling problem, and then apply stratified random sampling to improve the efficiency of sampling. The stratification is based on a low-cost predictor, such as the zero-delay power estimate. We also propose a two-stage stratified sampling technique to handle very long initial sequences. Experimental results show that the efficiency of stratified random sampling and two-stage stratified sampling techniques are 3-10 times higher than that of simple random sampling and the Markov-based Monte Carlo simulation techniques.

This paper presents a new approach for estimating power dissipation in a high performance microprocessor chip. A characteristic profile (including parameters such as the cache miss rate, branch-prediction miss rate, pipeline stalls, instruction mix, and so on) is first extracted from the application programs. Mixed-integer linear-programming and heuristic rules are then used to gradually transform a generic program template into a fully functional program. The synthesized program exhibits the same characteristics (and hence the same performance and power-dissipation behavior), yet it has an instruction trace that is orders of magnitude smaller than the initial trace. The synthesized program is subsequently simulated on a register-transfer-level description of the target microprocessor to provide the power-dissipation value. Results obtained for Intel's Pentium processor executing standard benchmark programs show a simulation-time reduction of three to five orders of magnitude.

This paper introduces the notion of cycle-accurate macro-models for RT-level power evaluation. These macro-models provide us with the capability to estimate the circuit power dissipation cycle by cycle at RT-level without the need to invoke low level simulations. The statistical framework allows us to compute the error interval for the predicted value from the user specified confidence level. The proposed macro-model generation strategy has been applied to a number of RT-level blocks and detailed results and comparisons are provided.

This paper proposes to use quantile points of the cumulative distributionfunction for power consumption to provide detailed informationabout the power distribution in a circuit. The paper also presentstwo techniques based on population pruning and stratification to improvethe efficiency of estimation. Both population pruning and stratificationare based on a lowcost predictor, such as zero-delay powerestimate. Experimental results show the effectiveness of the proposedtechniques in providing detailed power distribution information.

This paper presents a new approach for estimatingpower dissipation in a high performance microprocessor chip.First, characteristic profile (including parameters such as thecache miss rate, branch prediction miss rate, pipeline stalls,instruction mix, memory references, etc.) is extracted fromapplication programs. Then, mixed integer linear programmingand heuristic rules are used to gradually transform a genericprogram template to into a fully functional program. Thesynthesized program exhibits the same performance and powerdissipation behavior (as characterized by the extracted profile),yet it has an instruction trace orders of magnitude smaller thanthe initial trace. The synthesized program is subsequentlysimulated on a register-transfer level description of the targetmicroprocessor to provide the power dissipation value. Resultsobtained for the Intel's Pentium processor executing standardbenchmark programs show a simulation time reduction by 3-5orders of magnitude.

In this paper, we present new statistical sampling techniques for performing power estimation at the circuit level. These techniques first transform the power estimation problem to a survey sampling problem, then apply stratified random sampling to improve the efficiency of sampling. The stratification is based on a low-cost predictor, such as zero delay power estimates. We also propose a two-stage stratified sampling technique to handle very long initial sequences. Experimental results show that the efficiency of stratified random sampling and two-stage stratified sampling techniques are 3-10 X higher than that of simple random sampling and the Markov-based Monte Carlo simulation techniques.

In this paper, we propose a statistical power evaluation framework at the RT-level. We first discuss the power macro-modeling formulation, and then propose a simple random sampling technique to alleviate the the overhead of macro-modeling during RTL simulation. Next, we describe a regression estimator to reduce the error of the macro-modeling approach. Experimental results indicate that the execution time of the simple random sampling combined with power macro-modeling is 50 X lower than that of conventional macro-modeling while the percentage error of regression estimation combined with power macro-modeling is 16 X lower than that of conventional macro-modeling. Hence, we provide the designer with options to either improve the accuracy or the execution time when using power macro-modeling in the context of RTL simulation.

We describe a technique to estimate the energy consumed by speed-independent asynchronous (clock-less) control circuits. Because speed-independent circuits are hazard-free under all possible combinations of gate delays, we prove that an accurate estimate of their energy consumption is independent of relative component gate delays and can be determined by simulating only a small number of input patterns proportional to the size of the circuit's Signal Transition Graph specification. Specifically, we calculate the average energy per external signal transition consumed by a circuit. This can be used to compare the energy consumption between two different circuit implementations of the same specification, to calculate average energy for a given high-level operation, and to provide average circuit power when combined with delay information.