The identification of performance issues on specific computer architectures has a variety of important benefits such as tuning software to improve performance, comparing the performance of various platforms and assisting in the design of new platforms. In order to enable this analysis, most modern micro-processors provide access to hardware-based event counters. Unfortunately, features such as out-of-order execution, pre-fetching and speculation complicate the interpretation of the raw data. Thus, the traditional approach of assigning a uniform estimated penalty to each event does not accurately identify and quantify performance limiters. This paper presents a novel method employing a statistical regression-modeling approach to better achieve this goal. Specifically, a model-tree based approach based on the M5' algorithm is implemented and validated that accounts for event interactions and workload characteristics. Data from a subset of the SPEC CPU2006 suite is used by the algorithm to automatically build a performance-model tree, identifying the unique performance classes (phases) found in the suite and associating with each class a unique, explanatory linear model of performance events. These models can be used to identify performance problems for a given workload and estimate the potential gain from addressing each problem. This information can help orient the performance optimization efforts to focus available time and resources on techniques most likely to impact performance problems with highest potential gain. The model tree exhibits high correlation (more than 0.98) and low relative absolute error (less than 8 %) between predicted and measured performance, attesting it as a sound approach for performance analysis of modern superscalar machines

Network protocol stacks, in particular TCP/IP software implementations, are known for its inability to scale well in general-purpose monolithic operating systems (OS) for SMP. Previous researchers have experimented with affinitizing processes/thread, as well as interrupts from devices, to specific processors in a SMP system. However, general purpose operating systems have minimal consideration of user-defined affinity in their schedulers. Our goal is to expose the full potential of affinity by in-depth characterization of the reasons behind performance gains. We conducted an experimental study of TCP performance under various affinity modes on IA-based servers. Results showed that interrupt affinity alone provided a throughput gain of up to 25%, and combined thread/process and interrupt affinity can achieve gains of 30%. In particular, calling out the impact of affinity on machine clears (in addition to cache misses) is characterization that has not been done before

A stochastic analysis of multidimensional networks with unidirectional or bidirectional links between nodes is presented. The analysis allows the development of an accurate model for examining the performance and cost trade-offs of different network configurations. The model is validated through simulation and does not rely on the simplifying assumptions of previous models. In addition, the model is valid for the hypercube network. Two new performance-based design constraints are introduced: constant maximum throughput and constant unity queue. These new constraints are fundamentally different than previous constraints, which are based on some characterization of hardware implementation costs. Both of the new constraints allow performance and cost comparisons of different network configurations to be made on the basis of an equal ability to handle a range of traffic load. Results under the new constraints clearly show that a low dimensional network, while offering the lowest message latency, must be significantly more expensive than a comparable high dimensional network and, in some cases, may be impractical to implement. In addition, the constraints demonstrate that performance is highly dependent on offered load.

A stochastic analysis of multidimensional networks with unidirectional links between nodes is presented, which is more accurate than previous models and valid for the hypercube. The results are reconciled with those of previous researchers who have reported conflicting conclusions. In addition to the classic constraints of constant link width, pin-out, and bisection width, a new constraint, constant maximum throughput, is introduced. This constraint dramatizes the performance and cost trade-offs between different network topologies.

One type of interconnection network for a medium to large-scale parallel processing system (i.e., a system with 2/sup 6/ to 2/sup 16/ processors) is a buffered packet-switched multistage interconnection network (MIN). It has been shown that the performance of these networks is satisfactory for uniform network traffic. More recently, several studies have indicated that the performance of MIN's is degraded significantly when there is hot spot traffic, that is, a large fraction of the messages are routed to one particular destination. A multipath MIN is a MIN with two or more paths between all source and destination pairs. This research investigates how the Extra Stage Cube multipath MIN can reduce the detrimental effects of tree saturation caused by hot spots. Simulation is used to evaluate the performance of the proposed approaches. The objective of this evaluation is to show that, under certain conditions, the performance of the network with the usual routing scheme is severely degraded by the presence of hot spots. With the proposed approaches, although the delay time of hot spot traffic may be increased, the performance of the background traffic, which constitutes the majority of the network traffic, can be significantly improved.>

Methods for enhancing multistage interconnection network simulators running on massively parallel SIMD computers are presented. Aspects of parallel simulation of interconnection networks are discussed and different strategies of mapping the architecture of the network to be simulated onto the parallel machine are studied and compared. As case studies, two strategies of mapping synchronous multistage cube networks onto the MasPar MP-1 SIMD machine are explored and their implementations are compared. The methods result in an efficient simulator which can process 10^9 data packets in 40 minutes.

One type of interconnection network for a medium to large-scale parallel processing system (i.e., a system with 26 to 216 processors) is a buffered packet-switched multistage interconnection network (MIN). It has been shown that the per formance of these networks is satisfactory for uniform network traffic. More recently, several studies have indicated that the performance of MINs is degraded significantly when there is hot spot traffic, that is, a large fraction of the messages are routed to one particular destination. A multipath MIN is a MIN with two or more paths between all source and destination pairs. This research investigates how the Extra Stage Cube multipath MIN can reduce the detrimental effects of tree satura tion caused by hot spots. Simulation is used to evaluate the per formance of the proposed approach. The objective of this evaluation is to show that, under certain conditions, the perfor mance of the network with the usual routing scheme is severely degraded by the presence of hot spots. With the proposed approach, although the delay time of hot spot traffic may be increased, the performance of the background traffic, which constitutes the majority of the network traffic, can be significantly improved.

Any architectural or operational inefficiencies in multiprocessors with thousands of processors are likely to have a significant negative impact on the performance of the system. The authors examine two such issues in large-scale shared memory multiprocessors-the delays involved in accessing global shared memory, and the low processor utilization resulting from inefficient partitioning of the system among several tasks. These studies are undertaken using a simulation model that directly integrates the nondeterministic interconnection network delays encountered during shared memory accesses into the execution of tasks on processors. The results show the quantitative impact of interconnection network delay on system performance and point to ways of reducing this impact. Furthermore, when incoming tasks have large processor requirements, the system's inability to partition the processors among several tasks efficiently has a significant detrimental effect on performance. The effectiveness of some techniques to solve this partitionability problem is discussed.>

A mathematical model for predicting the performance of the direct binary n-cube interconnection scheme is presented. These predictions are checked against simulations of a comparable system. The results for the network are compared to known results for indirect interconnection schemes like the crossbar and indirect n-cube networks. Special operation conditions such as broadcasts and hot spots are considered. The following main inferences can be drawn from the study. Indirect networks need to use switches of size significantly larger than 2*2 to equal or better the performance of the hypercube system, under equiprobable distribution of message destinations. Sources attached to nodes in the direct network must be capable of generating multiple messages in a cycle to exploit the available bandwidth fully which is a key difference from the indirect networks. A variant of the standard broadcast algorithm introduced achieves a balanced distribution of network traffic, permitting the hypercube to support significant amounts of broadcast messages. These studies indicate that the transient effects of potential hot spot nodes on the background messages are small in the case of the hypercube.>

The implementation of an instruction reorganizer for a floating-point microprocessor with a variable-length pipeline is described. The reorganizer is designed to work with compiler-generated or hand-written assembly language code. A greedy heuristic algorithm is used to reorder instructions inside basic blocks. Memory aliasing is handled by accepting dependency-resolving directives from either the compiler or the assembly language programmer. Benchmark of the reorganizer using the Basic Linear Algebra Subprograms and the Livermore Loops are presented.>