EDBT 2026 Demo / reviewers in the wild / expert

Andrés David García García

dblp:99/289 · also Andrés D. García · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 46% Energy-efficient computing · 46% Processor architecture and microarchitecture · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA architecture		 0.012000
Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption · FPGA 2000
Reconfigurable computing and FPGAs
FPGA power reduction		 0.012000
Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption · FPGA 2000
Energy-efficient computing
power management		 0.012000
Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption · FPGA 2000
Energy-efficient computing
voltage reduction		 0.012000
Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption · FPGA 2000
Processor architecture and microarchitecture › pipelining
pipeline design		 0.012000
Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption · FPGA 2000
YearPublicationVenuePosition
2000 Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption
abstract
No abstract available.
Andrés David García García, Jean-Luc Danger, Wayne P. Burleson
 FPGA1
2000 Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption
abstract
Some techniques for low power operation in VLSI using the lowest possible supply voltage coupled with an architectural optimization have shown that we can save power even if we increase silicon area. In this paper we present a strategy to reduce power consumption in FPGAs based on pipeline architectures working with a low supply voltage.
Andrés David García García, Wayne P. Burleson, Jean-Luc Danger
 ISCAS1