Federated learning (FL) is a popular approach to facilitate privacy-aware machine learning since it allows multiple clients to collaboratively train a global model without granting others access to their private data. It is, however, known that FL can be vulnerable tomembership inference attacks(MIAs), where the training records of the global model can be distinguished from the testing records. Surprisingly, research focusing on the investigation of the source inference problem appears to be lacking. We also observe that identifying a training record's source client can result in privacy breaches extending beyond MIAs. For example, consider an FL application where multiple hospitals jointly train a COVID-19 diagnosis model, membership inference attackers can identify the medical records that have been used for training, and any additional identification of the source hospital can result the patient from the particular hospital more prone to discrimination. Seeking to contribute to the literature gap, we take the first step to investigate source privacy in FL. Specifically, we propose a new inference attack (hereafter referred to assource inference attack– SIA), designed to facilitate an honest-but-curious server to identify the training record's source client. The proposed SIAs leverage the Bayesian theorem to allow the server to implement the attack in a non-intrusive manner without deviating from the defined FL protocol. We then evaluate SIAs in three different FL frameworks to show that in existing FL frameworks, the clients sharing gradients, model parameters, or predictions on a public dataset will leak such source information to the server. We also conduct extensive experiments on various datasets to investigate the key factors in an SIA. The experimental results validate the efficacy of the proposed SIAs, e.g., an attack success rate of 67.1% (baseline 10%) can be achieved when the clients share model parameters with the server. Comprehensive ablation studies demonstrate that the success of an SIA is directly related to the overfitting of the local models.

Summary Recommender systems are important applications in big data analytics because accurate recommendation items or high‐valued suggestions can bring high profit to both commercial companies and customers. To make precise recommendations, a recommender system often needs large and fine‐grained data for training. In the current big data era, data often exists in the form of isolated islands, and it is difficult to integrate the data scattered due to privacy security concerns. Moreover, privacy laws and regulations make it harder to share data. Therefore, designing a privacy‐preserving recommender system is of paramount importance. Existing privacy‐preserving recommender system models mainly adapt cryptography approaches to achieve privacy preservation. However, cryptography approaches have heavy overhead when performing encryption and decryption operations and they lack a good level of flexibility. In this paper, we conduct privacy analysis on the existing locality sensitive hashing (LSH) approach based privacy‐preserving recommender system and show how an attacker can retrieve user's information under such a recommender system. Given such privacy risks, we propose differentially private LSH approach to build recommender system that can offer differential privacy guarantees for users. Our proposed efficient and scalable federated recommender system can make full use of multiple source data from different data owners while guaranteeing privacy preservation of users' data in contributing parties. Extensive experiments on real‐world benchmark datasets show that our approach can achieve both high time efficiency and accuracy under small privacy budgets.

Lots of non-additive cost assignment methods designed for image steganography have improved the security of stego images, but surprisingly there are only a few such non-additive cost assignment methods for video steganography. In this paper, we first analyze the distortion propagation by decomposing it into inner-block, inter-block, and inter-frame distortion drifts. Then, we determine the inner-block distortion drift (caused by the embedding modifications) that induces the inter-block and the inter-frame distortion drifts, using prediction. Based on the findings, we compose a joint distortion for all transform coefficients in each transform block. Finally, we propose a joint distortion-based non-additive cost assignment (NACA) method to reduce the inner-block distortion drift by distortion compensation. This allows us to further reduce both intra-frame (inter-block) and inter-frame distortion drifts, and achieve enhanced security. We conduct extensive experiments to evaluate the performance of NACA, in terms of security and coding performance. The evaluation results demonstrate that NACA achieves improved security and visual stego video quality, and maintains a very marginal increase in bit-rate, in comparison to four other competing additive cost assignment approaches.

Designing software systems underpinned by a formal model of computation (MoC) is crucial for safety-critical, real-time and all industrial applications as it allows formal analysis of those designs and support for correct by design systems. In this paper, we focus on Globally Asynchronous Locally Synchronous (GALS) software systems and Coloured Petri Nets (CPNs) based approach to formally model and analyse GALS software systems specified in SystemJ GALS programming language. The approach translates SystemJ constructs into CPN modules and composes them into CPN GALS model based on control flow and concurrency specified in the SystemJ program. It preserves GALS MoC by automatically integrating synchronizer modules, asynchronous channel interface modules, and scheduling modules to result in the execution model of SystemJ program equivalent CPN. The created CPN GALS model allows system developers to verify the properties of the design formally with the use of Computation Tree Logic (CTL). An industrial automation example is provided as a use case.

Recently issued data privacy regulations like GDPR (General Data Protection Regulation) grant individuals the right to be forgotten. In the context of machine learning, this requires a model to forget about a training data sample if requested by the data owner (i.e., machine unlearning). As an essential step prior to machine unlearning, it is still a challenge for a data owner to tell whether or not her data have been used by an unauthorized party to train a machine learning model. Membership inference is a recently emerging technique to identify whether a data sample was used to train a target model, and seems to be a promising solution to this challenge. However, straightforward adoption of existing membership inference approaches fails to address the challenge effectively due to being originally designed for attacking membership privacy and suffering from several severe limitations such as low inference accuracy on well-generalized models. In this paper, we propose a novel membership inference approach inspired by the backdoor technology to address the said challenge. Specifically, our approach of Membership Inference via Backdooring (MIB) leverages the key observation that a backdoored model behaves very differently from a clean model when predicting on deliberately marked samples created by a data owner. Appealingly, MIB requires data owners' marking a small number of samples for membership inference and only black-box access to the target model, with theoretical guarantees for inference results. We perform extensive experiments on various datasets and deep neural network architectures, and the results validate the efficacy of our approach, e.g., marking only 0.1% of the training dataset is practically sufficient for effective membership inference.

This paper presents DSF-IoT, a novel distributed approach enabling a future decentralised Internet of Things (IoT). DSF-IoT is designed to address key challenges in the IoT, providing a novel secure and efficient specification for the description of IoT services and their data, as well as novel mechanisms for consistent dynamic and contextually relevant service discovery and interaction. Distributed technologies provide an alternative to existing centralised and firmly capitalised models for service provision, removing the requirements for trusted vendor infrastructure and simplifying the deployment of IoT devices, while end-to-end trust, authenticity, and confidentiality ensure user interactions and data are secure-by-default. DSF-IoT is demonstrated through the development of a network of demonstration devices, and evaluated against existing frameworks for IoT service specification and discovery.

Scalable data processing platforms built on cloud computing becomes increasingly attractive as infrastructure for supporting big data applications. But privacy concerns are one of the major obstacles to making use of public cloud platforms. Multidimensional anonymisation, a global-recoding generalisation scheme for privacy-preserving data publishing, has been a recent focus due to its capability of balancing data obfuscation and usability. Existing multidimensional anonymisation methods suffer from scalability problems when handling big data due to the impractical serial I/O cost. Given the recursive feature of multidimensional anonymisation, parallelisation is an ideal solution to scalability issues. However, it is still a challenge to use existing distributed and parallel paradigms directly for recursive computation. In this paper, we propose a scalable approach for big data multidimensional anonymisation based on MapReduce, a state-of-the-art data processing paradigm. Our basic idea is to partition a data set recursively into smaller partitions using MapReduce until all partitions can fit in the memory of a computing node. A tree indexing structure is proposed to achieve recursive computation. Moreover, we show the applicability of our approach to differential privacy. Experimental results on real-life data demonstrate that our approach can significantly improve the scalability of multidimensional anonymisation over existing methods.

Cost assignment plays a key role in coding performance and security of video steganography. Existing cost assignment methods (for adaptive video steganography) are designed for specific transform coefficients rather than all transform coefficients. In addition, existing video steganographic frameworks do not allow Syndrome-Trellis Codes (STCs) to modify all transform coefficients in both intra-coded and inter-coded frames at the same time. To address these limitations, in this article, we first propose a novel video steganographic framework. Then, we give a theoretical analysis of distortion drift in both intra- and inter-coding procedures. Based on the analysis, we design a Distortion Drift-Based Cost Assignment method, hereafter referred to as DDCA. DDCA considers the inner-block, inter-block and inter-frame distortion costs in order to improve the coding performance and the security of stego videos when the embedding payload is fixed. We conducted extensive experiments using two video datasets to evaluate the proposed video steganographic framework and DDCA, in terms of the coding performance and the security. Our experiments show that the proposed framework outperforms three recent state-of-the-art methods, for example the coding performance and the security of stego videos can benefit from DDCA by making full use of all nonzero transform coefficients.

Federated learning (FL) has emerged as a promising privacy-aware paradigm that allows multiple clients to jointly train a model without sharing their private data. Recently, many studies have shown that FL is vulnerable to membership inference attacks (MIAs) that can distinguish the training members of the given model from the non-members. However, existing MIAs ignore the source of a training member, i.e., the information of the client owning the training member, while it is essential to explore source privacy in FL beyond membership privacy of examples from all clients. The leakage of source information can lead to severe privacy issues. For example, identification of the hospital contributing to the training of an FL model for the COVID-19 pandemic can render the owner of a data record from this hospital more prone to discrimination if the hospital is in a high risk region. In this paper, we propose a new inference attack called source inference attack (SIA), which can derive an optimal estimation of the source of a training member. Specifically, we innovatively adopt the Bayesian perspective to demonstrate that an honest-but-curious server can launch an SIA to steal non-trivial source information of the training members without violating the FL protocol. The server leverages the prediction loss of local models on the training members to achieve the attack effectively and non-intrusively. We conduct extensive experiments on one synthetic and five real datasets to evaluate the key factors in an SIA, and the results show the efficacy of the proposed source inference attack.

Membership inference attacks on a machine learning model aim to determine whether a given data record is a member of the training set. They pose severe privacy risks to individuals, e.g., identifying an individual's participation in a hospital's health analytic training set reveals that this individual was once a patient in that hospital. Adversarial regularization (AR) is one of the state-of-the-art defense methods that mitigate such attacks while preserving a model's prediction accuracy. AR adds membership inference attacks as a new regularization term to the target model during the training process. It is an adversarial training algorithm that is trained on a defended model which is essentially the same as training the generator of generative adversarial networks (GANs). We observe that many GAN variants are able to generate higher quality samples and offer more stability during the training phase than GANs. However, whether these GAN variants are available to improve the effectiveness of AR has not been investigated. In this paper, we propose an enhanced adversarial regularization (EAR) method based on Least Square GANs (LSGANs). The new EAR surpasses the existing AR in offering more powerful defensive ability while preserving the same prediction accuracy of the protected classifiers. We systematically evaluate EAR on five datasets with different target classifiers under four different attack methods and compare it with four other defense methods. We experimentally show that our new method performs the best among other defense methods.

In this paper, a real-time, real-life, novel license plate localisation (LPL) based on deep learning (DL) and accelerated by field-programmable gate array (FPGA), and Open Visual Inference and Neural network Optimization (OpenVINO) toolkit, is proposed and prototyped. The solution was tested against two popular international research databases and achieves state-of- the-art results, proving the viability of FPGA in real-life latency- oriented application. Using novel asynchronized DL inference that prepares next result while current inference is ongoing, the system increases computational efficiency without buffering frames, allowing for reduced latency. Comparisons show that the proposed LPL system has lower latency and better performance per watt than other related solutions.

Model inference is the final stage in machine/deep learning application deployments in practical applications. Hardware-implemented or accelerated model inferences find significant attractions as they offer faster inference than those implemented as programs. This is especially attractive for real-time applications. In this paper, we address models that serve for parking occupancy prediction based on historical time-series parking records. We use the Keras library to build and train software DNN and LSTM models, then compare their prediction performances in terms of accuracy. While the software-implemented inference models indicate advantages of LSTM, we still opted to select only DNN-based models for additional hardware acceleration as the current advanced tool-chains leveraged for automatic software-to-hardware model converting do not allow the creation of LSTM hardware- implemented models. We create, explore and compare the inference performances of hardware (FPGA)-implemented models on relatively low-cost FPGAs. For this, we create an FPGA-accelerated Fog-layer cluster by adding two additional Xilinx FPGA boards of different performances into our existing cluster of four Raspberry Pi (RPi) computers.

In this article, we propose a comprehensive multilayer (IoT-device, edge, fog, and cloud) streaming analytics platform with two-tier fog layer, which comprises streaming and analytics tiers. The approach, functionally validated on a testbed of clusters of low-cost off-the-shelf components, demonstrates that both real-time streaming processing and large-scale data analytics are feasible, with even completely avoiding the use of cloud layer. The fog layer uses advanced streaming and analytics paradigms, such as Apache Kafka, Apache Spark, and Hadoop, to support the effective development of applications that use streaming, long-term data storage and analytics. As such, the platform is suitable for and is affordable for “private” users. Furthermore, we add to the platform intelligent edge layer that abstracts and can simulate the operation of the IoT-device layer in real time or can be directly connected to the IoT-device layer. The experiments on a real-life IoT-based smart parking application show that our two-tier approach is cost effective and scalable, and can handle simultaneously streaming processing and analytics tasks successfully.

The recommender system is an important application in big data analytics because accurate recommendation items or high-valued suggestions can bring high profit to both commercial companies and customers. To make precise recommendations, a recommender system often needs large and fine-grained data for training. In the current big data era, data often exist in the form of isolated islands, and it is difficult to integrate the data scattered due to privacy security concerns. Moreover, privacy laws and regulations make it harder to share data. Therefore, designing a privacy-preserving recommender system is of paramount importance. Existing privacy-preserving recommender system models mainly adapt cryptography approaches to achieve privacy preservation. However, cryptography approaches have heavy overhead when performing encryption and decryption operations and they lack a good level of flexibility. In this paper, we propose a Locality Sensitive Hashing (LSH) based approach for federated recommender system. Our proposed efficient and scalable federated recommender system can make full use of multiple source data from different data owners while guaranteeing preservation of privacy of contributing parties. Extensive experiments on real-world benchmark datasets show that our approach can achieve both high time efficiency and accuracy under small privacy budgets.

Anomaly detection is one of the most important data mining tasks in many real-life applications such as network intrusion detection for cybersecurity and medical diagnosis for healthcare. In the big data era, these applications demand fast and versatile anomaly detection capability to handle various types of increasingly huge-volume data. However, existing detection methods are either slow due to high computational complexity, or unable to deal with complicated anomalies like local anomalies. In this paper, we propose a novel anomaly detection method named OPHiForest with the use of the order preserving hashing based isolation forest. The core idea is to learn the information from data to construct better isolation forest structure than the state-of-the-art methods like iForest and LSHiForest, which can achieve robust detection of various anomaly types. We design a fast two-step learning process for the order preserving hashing scheme. This leads to stronger order preservation for better hashing, and therefore enhances anomaly detection robustness and accuracy. Extensive experiments on both synthetic and real-world data sets demonstrate that our method is highly robust and scalable.

Dynamic reconfigurability and adaptability are crucial features of the future manufacturing systems that must be supported by adequate software technologies. Currently, they are typically achieved as add-ons to existing software tools and run-time systems, which are not based on any formal foundation such as formal model of computation (MoC). This paper presents the new programming paradigm of service oriented SystemJ (SOSJ), which targets dynamic distributed software systems suited for future manufacturing applications. SOSJ is built on a merger and the synergies of two programming concepts of service oriented architecture, to support dynamic software system composition, and SystemJ programming language based on a formal MoC, which targets correct by construction design of static distributed software systems. The resulting programming paradigm allows the design and implementation of dynamic distributed software systems.

This article introduces distributed service framework (DSF), a distributed service framework supporting development, and deployment of trustworthy and privacy-preserving distributed Internet of Things (IoT) and Industrial IoT (IIoT) applications. DSF provides a common protocol and infrastructure for secure service specification, registration, discovery, publishing, and subscription, over insecure public networks, and introduces mechanisms for service replication, supporting dynamic scalability of services, and delegation, allowing use on embedded and resource-constrained devices. DSF is an open protocol, with an open-source implementation including supporting library for application development, a command-line client for user interaction, and a daemon that manages services and data. DSF is qualitatively evaluated against existing approaches to developing distributed applications and common technologies used in the IIoT context and demonstrated through the development of an IIoT scenario.

In this paper, a new solution based on wireless sensor network is introduced to provide low cost and low energy monitoring for underground pipelines. We propose an adaptive duty-cycle MAC protocol based on Wake-on-Radio called WoR-MAC. Simulation experiments have been conducted to validate the outstanding performance compared with other duty-cycle based energy-efficient MAC protocols in terms of energy consumption and average end-to-end latency.

SystemJ is a programming language developed for implementing safety critical cyber-physical systems, including industrial automation systems. However, the current tools do not support an efficient mechanism to verify SystemJ programs formally. This paper presents a semantics-preserving translation of the synchronous subset of SystemJ to Coloured Petri Net (CPN), which in turn enables leveraging the plethora of analysis and verification tools for CPN to verify SystemJ programs. The translation and verification approach is illustrated on a pedagogical industrial automation example of a SystemJ program.

The heterogeneity of execution platforms and operating software in manufacturing machines and robots, as well as various sensors and actuators, creates challenges for integration into larger systems. Existing approaches make use of different types of middleware to mitigate the challenges of designing interoperable systems. However, middleware can significantly impede modular design and composition of software systems that are dynamic in nature. This paper elaborates upon those challenges and proposes using an approach called service-oriented SystemJ (SOSJ), based on the system-level programming language SystemJ enhanced with service oriented features. This approach allows developers to design dynamic software systems while adopting and incorporating legacy solutions. The approach is demonstrated on the integration of an industrial automation system, incorporating the use of multiple modular mechatronics stations and service robotics systems, represented by robot operating system-enabled Baxter robots. The proposed approach offers a simple service interface based on abstract objects for integrating robots and automation machines in the SOSJ world, without the need to modify the underlying mechatronics or robotics systems.

This paper proposes a novel extension for communication in the lEC 61499 standard. Inspired by the features found in the formal programming language SystemJ, the extension supports reliable and guaranteed communication in distributed execution of function block application(s)/program(s). The extension utilizes mechanisms agnostic on underlying network protocols and are based on formal semantics that guarantee data delivery. The use of proposed extension, called channel, is demonstrated in an industrial automation-type example.

Ahstract- This paper introduces Yet Another Wireless Network Simulator (YAWNS), a simulator supporting the development and automated validation of complex heterogeneous systems based on wireless sensor and actuator networks (WSANs). YAWNS allows simulation of heterogeneous systems through the use of a novel Virtual Radio Interface (VRI) abstraction that mimics the operation of physical radio hardware over a language independent simulation protocol. This simplifies system integration and decouples application languages and hardware from the simulation process, allowing evaluation and interoperability testing when using different languages, operating systems, applications and protocol implementations. The simulator is based on an extensible discrete-time engine coupled with a low-fidelity emulated medium allowing intuitive description of scenarios as well as simulation of complex dynamic and multiband environments with approximate real-world parity. A simple configuration language allows the definition of scenarios as well as events to update or validate the state of the simulation, allowing automated alteration of scenarios and evaluation of applications.

One of the key challenges in modern manufacturing systems is how to dynamically reconfigure software behaviors that govern machines to reflect changes in physical manufacturing process without completely resetting the entire manufacturing operation. The existing software solutions used to describe software behaviors in manufacturing systems are typically not based on formal semantics and model of computation and have limited capabilities in handling dynamic adaptation/reconfiguration. This paper presents the Service-Oriented SystemJ (SOSJ) framework that supports a new programming paradigm for designing dynamic distributed manufacturing systems. SOSJ combines the system-level language SystemJ and service-oriented architecture (SOA) paradigm to take advantages of both SystemJ's correct-by-construction formal semantics and SOA's dynamic features, respectively. The paper describes the concepts and functionalities of SOSJ, which enable dynamic reconfiguration of a typical manufacturing system. Performance benchmarks are run to compare the capabilities of SOSJ to a multiagent system framework JADE.

Anomaly or outlier detection is a major challenge in big data analytics because anomaly patterns provide valuable insights for decision-making in a wide range of applications. Recently proposed anomaly detection methods based on the tree isolation mechanism are very fast due to their logarithmic time complexity, making them capable of handling big data sets efficiently. However, the underlying similarity or distance measures in these methods have not been well understood. Contrary to the claims that these methods never rely on any distance measure, we find that they have close relationships with certain distance measures. This implies that the current use of this fast isolation mechanism is only limited to these distance measures and fails to generalise to other commonlyused measures. In this paper, we propose a generic framework named LSHiForest for fast tree isolation based ensemble anomaly analysis with the use of a Locality-Sensitive Hashing (LSH) forest. Being generic, the proposed framework can be instantiated with a diverse range of LSH families, and the fast isolation mechanism can be extended to any distance measures, data types and data spaces where an LSH family is defined. In particular, the instances of our framework with kernelised LSH families or learning based hashing schemes can detect complicated anomalies like local or surrounded anomalies. We also formally show that the existing tree isolation based detection methods are special cases of our framework with the corresponding distance measures. Extensive experiments on both synthetic and real-world benchmark data sets show that the framework can achieve both high time efficiency and anomaly detection quality.

One of the most efficient ways of reducing household energy consumption is through an online feedback system, which helps users in reducing their household energy. There are several research and commercial products available, yet over-consumption issues are still prevalent. An important factor fueling these issues is rendering too many features or information in the online feedback system, which results in a decrease in use of those applications over time. This study aims to develop a user-friendly system with a minimal set of features that would help the residential users achieve maximum savings. The energy control system (ECoS) consists of three major features, i.e., (a) visualization of energy, (b) recommendation of energy saving decision to users, (c) remote appliance control through recommendations, with thirteen sub-features. Based on an analysis of energy savings and user preferences, we identified the top seven sub-features suitable to be in ECoS to help users save energy. In addition, this article also provides recommendations to energy providers on the list of features that they should include in their online application to help their users save a significant amount of energy.

In this paper, we propose using an approach based on the system-level programming language SystemJ extended with service oriented features, called SOSJ, to design dynamic interoperable software systems. The approach abstracts and integrates the worlds of automation and robotics systems by using a simple service interface based on abstract objects within SOSJ. We demonstrate our approach in a real-life automated bottling system scenario that uses multiple FESTO modular stations operating in SOSJ and integrating them with two Baxter robots operating in ROS without the need for any modification of the underlying mechatronics or robotics systems.

Time predictability is a first class requirement in safety critical system design. Techniques exist for the timing analysis of programs designed in memory managed languages, but these require detailed knowledge of memory allocation. Moreover, enforcing hard real-time guarantees for systems designed in such garbage collected languages is difficult, because of the so called collection pause - however incremental. This paper proposes a novel solution whereby a separate reference counting unit replaces the garbage collector. We present the underlying concepts of the Reference Counting Memory Management Unit (RCMMU) and its use for garbage collection. In addition, we present an implementation that includes a specialized memory arrangement that allows for object management transactions to occur concurrently with program execution, with no resultant impact upon program performance. The RCMMU has been targeted for use with Java but can be adopted to be used with other memory managed languages. The hardware-implemented RCMMU removes all overhead associated with garbage collection operations when compared against a software-only collector. Additionally, it simplifies the static worst-case execution time analysis of programs.

MPSoC-based embedded systems design is becoming increasingly complex. Not only do we need to satisfy multiple design objectives, we increasingly need to address potential security risks. In this work, we propose a security-aware systematic design approach which explores the design space, given a system-level application description, by generating potential architecture configurations of execution platform nodes that are interconnected using a NoC. We then perform automated security analysis to check the generated configurations against designer-specified security constraints. Following the analysis, we use an automated architecture configuration refinement process to generate a list of security additions that are inserted into the initial configuration so that the security constraints are satisfied. By performing this refinement on several candidate configuration options, we can explore the trade-off between resource cost and security. In this paper, we illustrate the proposed approach using a Smart Home Control System application.

Scalability and performance in multicore processors for embedded and real-time systems usually don't go well each with the other. Networks on Chip (NoCs) provide scalable execution platforms suitable for such kind of embedded systems. This article presents a NoC-based Heterogeneous Multi-Processor system, called NoC-HMP, which is a scalable platform for embedded systems developed in the GALS language SystemJ. NoC-HMP uses a time-predictable TDMA-MIN NoC to guarantee latencies and communication time between the two types of time-predictable cores and can be customized for a specific performance goal through the execution strategy and scheduling of SystemJ program deployed across multiple cores. Examples of different execution strategies are introduced, explored and analyzed via measurements. The number of used cores can be minimized to achieve the target performance of the application. TDMA-MIN allows easy extensions of NoC-HMP with other cores or IP blocks. Experiments show a significant improvement of performance over a single core system and demonstrate how the addition of cores affects the performance of the designed system.

While cloud computing has become an attractive platform for supporting data intensive applications, a major obstacle to the adoption of cloud computing in sectors such as health and defense is the privacy risk associated with releasing datasets to third-parties in the cloud for analysis. A widely-adopted technique for data privacy preservation is to anonymize data via local recoding. However, most existing local-recoding techniques are either serial or distributed without directly optimizing scalability, thus rendering them unsuitable for big data applications. In this paper, we propose a highly scalable approach to local-recoding anonymization in cloud computing, based on Locality Sensitive Hashing (LSH). Specifically, a novel semantic distance metric is presented for use with LSH to measure the similarity between two data records. Then, LSH with the MinHash function family can be employed to divide datasets into multiple partitions for use with MapReduce to parallelize computation while preserving similarity. By using our efficient LSH-based scheme, we can anonymize each partition through the use of a recursive agglomerative $k$-member clustering algorithm. Extensive experiments on real-life datasets show that our approach significantly improves the scalability and time-efficiency of local-recoding anonymization by orders of magnitude over existing approaches.

This paper presents new changes and improvements in the architecture of a programming paradigm Service Oriented SystemJ (SOSJ) to tackle large distributed systems. The programming paradigm makes use of the synergy of two programming concepts of Service Oriented Architecture (SOA) suitable for dynamic system composition and formal GALS (Globally Asynchronous Locally Synchronous) language SystemJ amenable for designing safe static concurrent distributed systems. The use of SOSJ framework based on the new architecture is demonstrated in an industrial manufacturing example and initial benchmarks that evaluate the framework's performance in large distributed systems are shown.

The paper introduces a new multi-core SoC platform designed for industrial automation applications with mixed criticality. The applications are written in SystemJ language. The multi-core platform consisting of three different types of cores is implemented in a SoC that contains a standard dual-core ARM and a FPGA, which is used to run the critical part of the system. The platform is fully customizable in terms of number and types of cores to the needs of the application. An industrial automation case study is used to demonstrate the use and performance of the multi-core SoC.

This paper presents the Service Oriented SystemJ (SOSJ) framework, which combines correct-by-construction language features of GALS (Globally Asynchronous Locally Synchronous) system-level language SystemJ with dynamic reconfiguration features of Service Oriented Architecture (SOA), creating a new programming paradigm suitable for designing dynamic distributed manufacturing systems. The paper demonstrates new concepts introduced by SOSJ which enable dynamic online reconfiguration of typical distributed manufacturing systems. Some performance benchmarks are used to showcase the capability of the SOSJ framework.

Chip temperature becomes a critical design issue with technology scaling to nanometer-scale, especially for NoC systems with large number of cores and shrunken core size. To reduce peak temperature and balance spatial temperature distribution on NoC-based multi-cores chips, this paper proposes a temperature-aware task scheduling approach. The thermal profiles of tasks are first extracted by accurate temperature model. Then run-time task mapping heuristic is proposed considering transient core temperatures, thermal dissipation from adjacent cores, communication overheads and the thermal influence of physical position on chip. Voltage-frequency is also scaled down when timing constraint is met to reduce power consumption and core temperature. Experimental results show that the significant reduction of peak temperature and the temperature variance compared with the current approaches is achieved.

IEC 61499 enables component-oriented descriptions of complex industrial processes facilitating model-driven engineering. One aspect that is lacking, however, is the ability to directly express Statecharts-like hierarchy and concurrency within basic function blocks (BFBs). Such features can significantly enhance function blocks and help create more succinct and readable specifications. We propose a new syntactic extension to the standard called hierarchical and concurrent execution control chart (HCECC). A major roadblock for any suggested changes to the standard is the need for compliance. Our approach extends the synchronous execution semantics of IEC 61499, where HCECCs are purely syntactic sugar. Using a revised synchronous semantics, our compiler generates standard compliant C code from HCECCs. Benchmarking and usability studies reveal the relative superiority of the proposed approach over existing approaches.

Embedded sensors are increasingly seen in modern mobile and wearable devices to support better user activities and vital signs monitoring. While more wireless sensing devices are becoming available, network connectivity and scalability remain the key obstacles in achieving seamless information flow and service provision as envisaged by the vision of the Internet of Things. In this paper, a mobile 6LoWPAN network architecture is proposed by engaging Android-based mobile devices as edge routers to address the connectivity and scalability issues with the wider IP network for pervasive healthcare applications. The 6LoWPAN-based wireless sensor network, together with the Android edge router, form a mobile sub-network that allows seamless information exchange with the Internet and improves service availability for each end user. The proposed architecture includes a customised bare-metal 6LoWPAN protocol designed for ultra low power wireless sensor nodes for long term vital signs monitoring and integrated with Android devices for mobile internet access. The proposed network architecture is demonstrated and validated on a pervasive healthcare monitoring application.

This paper presents an extensible and adaptable platform for distributed applications with mixed criticality based on using state of the art FPGA technology. Although capable of executing programs written in different languages, the platform specifically targets the execution of programs written in Globally Asynchronous Locally Synchronous language SystemJ used in the context of Internet of Industrial Things. The key properties of the prototype platform are accommodation of mixed-criticality processing as well as provision of Internet addressable services. Mixed-criticality execution platform (MCEP) uses multiple processor cores and network interfaces: (1) a dual-core ARM processor with Ethernet for Internet access and processing of non-real -- time application parts and (2) TP-JOP reactive hard real-time processor with customized Controller Area Network (CAN) for real-time and time-critical response processing. This platform has been successfully developed and used in an industrial automation system within the Internet of Industrial Things context.

This paper proposes a new software composition method for automated machines that exploits their mechatronic modularity. It is demonstrated that desired behavior of a certain class of machines can be composed of behaviors of its mechatronic components, including fully decentralized scheduling and operation control. This aims at increased performance of software design and maintenance, as well as systems' flexibility and reconfigurability. The IEC 61499 Function Blocks' (FBs) architecture is used as an implementation platform that enables system-level simulation and transparency of deployment. A configurable pick-and-place (PnP) manipulator with decentralized control synthesized using the proposed approach is chosen as an illustrative example.

Safety-critical software systems need to guarantee functional correctness and bounded response times to external input events. Programs designed using reactive programming languages, based on formal mathematical semantics, can be automatically verified for functional correctness guarantees. Real-time guarantees on the other hand are much harder to achieve. In this article we provide a static analysis framework for guaranteeing response times for reactive programs developed using the Globally Asynchronous Locally Synchronous (GALS) model of computation. The proposed approach is applicable to scheduling of GALS programs for different target architectures with single or multiple processors or cores. A Satisfiability Modulo Theory (SMT) formulation in the quantifier free linear real arithmetic (QF_LRA) logic is used for scheduling. A novel technique to encode rendezvous used in synchronization of globally asynchronous processes in the presence of locally synchronous parallelism and arbitrary preemption into QF_LRA logic is presented. Finally, our SMT formulation is shown to produce schedules in reasonable time.

We present a novel approach for design of manufacturing automation systems with formal verification of selected properties based on the use of Globally Asynchronous Locally Synchronous programming language SystemJ and industrial-proof verification tools. By being able to prove properties of the automation control logic that consists of multiple concurrent controllers, represented by FSMs that correspond to asynchronous processes of SystemJ program, using Spin model checker, we demonstrate that the program features can be formally verified. Moreover, by also guaranteeing preservation of features and GALS model of the SystemJ program after compilation (correct by construction specification), we actually close the design process within What You Prove Is What You Execute (WYPIWYE) Paradigm.

We face a glut of languages for programming distributed software today. However, only a few languages have proven their potential with wider practical use in different domains of computing. We picked two such languages, meant for different domains, to see if they could cross-pollinate and enrich one another. Specifically, we chose SystemJ, a language to program distributed embedded systems, and IEC61499, the next generation standard for distributed industrial automation control software. Unsurprisingly, we found similar structures and artifacts between the two. We also found significant differences mainly due to differing domain-specific requirements. This comparison leads to observations and guidelines for improving both languages, and we discuss directions towards an “ideal” distributed software programming language.

This research proposes an innovative agent-based design method known as “MIRA” (Modular, Intelligent and Real-time Agent) to represent products as well as mechatronic components in manufacturing systems. The new agent exploits semantic knowledge representation of its capabilities, tasks and surroundings, and upon which performs rule-based reasoning leading to generation of the IEC 61499 Function Blocks for real time and distributed control of production systems. This approach facilitates product's mass customization through development of intelligent mechatronic systems. Furthermore, the MIRA approach is exemplified in a food production case study.

Connection of wireless sensor and actuator networks (WSANs) to the Internet will enable information flow to these once isolated networks. Distributed Ambient Intelligence (AmI) applications, such as remote monitoring and control services, would become possible if Internet connectivity of WSANs is achieved. However, realization of such applications remains challenging with three major obstacles. First, the homogeneity of embedded sensor and actuator nodes and hence homogeneous networks prevents seamless information flow and service provision. Second, current WSAN technology has limited support for Internet connectivity. Protocol conversion with heavy overhead is required on a more powerful gateway device. Third, there are no common interoperable interfaces between different WSAN standards which has become a barrier to heterogeneous WSAN applications. This paper introduces a design for an integrated IP compatible, heterogeneous WSAN composed of the University of Auckland's AWSAM and Oracle's Sun SPOT nodes. This was achieved through the creation of a Hybrid Router, which physically bridges AWSAM and Sun SPOT communication with customized network abstraction, and an Edge Router, which provides Internet connectivity.

Static estimation of the Worst Case Reaction Time (WCRT) of synchronous programs is pivotal for designing hard-real time systems in these languages. The current approaches to WCRT estimation suffer from either large overestimation of the WCRT value or the state space explosion problem. In this paper, we present TACO: a framework that integrates model checking based WCRT estimation with code optimization techniques, which results in close to optimal WCRT estimates with orders of magnitude reduced worst case runtime complexity. Finally, the TACO framework also allows us to generate executables with a smaller overall memory footprint.

In this paper we introduce exact and non-exact real-time waits in reactive Globally Asynchronous Locally Synchronous (GALS) programming languages and synchronous languages as their subset. The language constructs that allow use of real-time waits are illustrated on the SystemJ GALS language. They allow system designers to explicitly use, at the specification level, not only logical time but also the real-time in order to control program execution. The introduced concepts utilize execution platforms that allow finding best and worst reaction time of a GALS or synchronous program.

Collaborative communication produces high power gain and significantly reduces bit error rate (BER) if both frequency and phase synchronization are achieved. In this paper, a novel collaborative communication system with imperfect phase and frequency synchronization that includes the influence of noise and fading is proposed, modeled, theoretically analyzed, and simulated. Mathematical expressions are derived for the received power as a function of number of collaborative nodes and BER as a function of signal to noise ratio (Eb ∕ N0). To analyze the energy efficiency of our proposed collaborative communication system, energy consumption of the system is modeled, simulated, and analyzed by considering the parameters of the off-the-shelf products. Analytical and simulation results showed that the proposed system produces significant power gain and reduction in BER in the presence of phase errors, frequency errors, additive white Gaussian noise, and Rayleigh fading. A detailed theoretical analysis and Monte Carlo simulation revealed that the proposed collaborative communication system is an energy efficient communication system that can be implemented in sensor networks, as approximately N (number of collaborative nodes) times less total transmitted power is required than for the single input single output communication for a specifies transmission range.

This paper presents a model-based design approach for description of mechatronic systems using System Modeling Language (SysML) in order to facilitate modification and customization of existing intelligent mechatronic components and their use in new applications. This approach enables re-use and integration of the existing mechatronic software components to meet system design requirements and minimize the design and commissioning complexity of the control systems. A case study with a delta robot used in a colour sorting application demonstrates how its control system is tailored to meet the desired system behaviour.

The ever increasing demand for energy has led towards distributed renewable energy generation systems. Such systems depend on a well integrated information and communication infrastructure for interconnection and integration of various energy sources, loads, and environmental sensors to achieve intelligent distributed control and management. This paper describes the design and implementation of an intelligent hybrid communication system for a micro distributed energy generation application. The industrial standard controller area network (CAN) bus was selected to connect various energy sources and loads, due to its resistance to noisy conditions. An application specific communication protocol was designed, based on the CAN protocol, to allow data exchange and control. The proposed communication system was verified using a prototype micro wind generation system with multiple power converters and a central energy management unit. Combined with intelligent control algorithms, which could in future be incorporated in the energy management unit, the system has the ability to perform optimised load balancing and energy usage planning.

The availability of low-power wireless sensor nodes has brought forward the scenarios of the Internet of Things, in which ubiquitous things need to be aware of their context, and at the same time be power efficient and IP-addressable. 6LoWPAN is one of the first protocols to standardise Internet connectivity for wireless sensor networks. The various 6LoWPAN implementations that are currently available are either dependent on the operating systems used on the sensor nodes or only commercially available. The dependency on using operating systems is suitable for larger nodes with more processing power and memory capacity, but is not practical, if not impossible, for power efficient nodes with systems on chip (SoC) solutions such as TI CC430. In this work, a successful implementation of 6LoWPAN/CD (6LoWPAN protocol for constrained devices) on bare metal CC430-based sensor nodes has been designed and implemented. It is based on open source software including the Contiki operating system and TI SimpliciTI protocol stack. The IP connectivity is demonstrated on a CC430-based power efficient wireless sensor node, AWSAM.

This paper proposes a rule-based approach for automatic configuration of mechatronic components in a novel agent-based manufacturing automation architecture known as MIRA, implemented using Prolog. Through this method, MIRAs are enriched with semantic knowledge representation and, based on that, perform some reasoning and decision making (both at the design stage and even during the operation) to achieve the desired goals. This approach is illustrated in a simple case study in which composition of a reconfigurable pick-and-place robot with various linear cylinders is achieved through rule-based reasoning.

We present a new heterogeneous multiprocessor (GALS-HMP) for the execution of Globally Asynchronous Locally Synchronous (GALS) programming languages. It specifically targets SystemJ GALS language, which extends Java with asynchronous and synchronous concurrency. A SystemJ program is partitioned by a compiler onto data-driven and control-driven parts, which are then allocated for the execution on traditional and reactive processors, which constitute GALS-HMP. The reactive processor is customized to meet the requirements of the control parts of the SystemJ programs. The prototypes developed on an FPGA show significant improvements in code size and execution speed compared to the case of using just traditional processors.

In this paper we present an approach to efficiently mix Java with asynchronous and synchronous concurrency and execute it on a specialized Java processor extended with capabilities for concurrency and reactivity. A new processor, which uses JOP (Java Optimized Processor) as its base, executes concurrent programs that comply with Globally Asynchronous Locally Synchronous (GALS) formal model of computation by clearly distinguishing between concurrency and reactivity control flow and Java control flow. The new processor, called JOP-Plus, can be used for embedded and even real-time applications in which majority of code is written in Java and the overall programs specified and structured in SystemJ system-level concurrent programming language.

Systems-on-chip (SoCs) contain multiple interconnected and interacting components. In this paper, we present a compositional approach for the integration of multiple components with a wide range of protocol mismatches into a single SoC. We show how SoC construction can be done in single-step when all components are integrated at once or it can also be performed incrementally by adding components to an already integrated design. Using a number of AMBA IPs, we show that the proposed framework is able to perform protocol conversion in many cases where existing approaches fail.

Distributed surveillance systems represent a class of sensor networks used for object location and tracking, road traffic monitoring, security, and other purposes. They are very complex to describe, design, and run. Because of their sensitivity, they need to be carefully designed and validated. We present a system-level approach to modeling and designing such systems using a new system-level programming language, SystemJ, which enables designers to describe computational and communication parts of such applications in a highly abstract manner. The designed system can be modeled and validated even before deployment and in that way contribute to the overall reliability and trustworthiness of such systems. As an additional tool, the design environment for specification of the surveillance system topology, physical and communication properties, selected sensors and their interconnectivity with the computing resources was developed. This tool enables easy composition of multiple sensors and their respective controllers, capturing changes of configuration of the system and underlying communication, and automatic generation of the formal description of the surveillance system. This description is then used for the generation of executable code and/or the templates for detailed SystemJ application-specific code, as well as for generation of the operator GUI in a surveillance system.

Cyber-physical systems (CPS) are integrations of computation and control with sensing and actuation of the physical environment. Typically, such systems consist of embedded computers that monitor and control physical processes in a feedback loop. While modern electronic systems are increasingly characterized as CPS, their design and synthesis still rely on traditional methods, which lack systematic and automated techniques for accomplishment. Recently, IEC 61499 has been proposed as a standard for designing industrial process-control and measurement systems. It prescribes a component-based approach for developing industrial automation software using function blocks. Executable code can then be automatically generated and simulated from these function blocks. This bodes well for designers of CPS, who are more likely to be experts in specific industrial domains, rather than in computer science. The intuitive graphical nature and automatic code synthesis of IEC 61499 programs will alleviate the programming burden of industrial engineers, while ensuring more reliable software. While software synthesis from IEC 61499 programs is not new, the generation of efficient code from them has been wanting. This has made it difficult for function blocks to be used in software development for resource-constrained embedded controllers commonly employed in CPS. To address this, we present an approach that can generate very efficient code from function block descriptions. Experimental results from a benchmark suite shows that our approach produces substantially faster and smaller code compared to existing techniques.

The paper presents a programming language, DSystemJ, for dynamic distributed Globally Asynchronous Locally Synchronous (GALS) systems, its formal model of computation, formal syntax and semantics, its compilation and implementation. The language is aimed at dynamic distributed systems, which use socket based communication protocols for communicating between components. DSystemJ allows the creation and control at runtime of asynchronous processes called clock-domains, their mobility on a distributed execution platform, as well as the runtime reconfiguration of the system's functionality and topology. As DSystemJ is based on a GALS model of computation and has a formal semantics, it offers very safe mechanisms for implementation of distributed systems, as well as potential for their formal verification. The details and principles of its compilation, as well as its required runtime support are described. The runtime support is implemented in the SystemJ GALS language that can be considered as a static subset of DSystemJ.

The IEC 61499 standard defines a generic architecture for designing distributed industrial control systems based on function blocks. The standard, however, lacks a formal model of computation to describe the behavior of function block compositions. While various models have been prescribed in the literature to define the composite behavior on a single computational node, few have been proposed to directly address compositions in a distributed setting. This paper proposes a globally asynchronous locally synchronous (GALS) model for distributed function block systems. The model provides an abstract way to view communication between function blocks without implying yet any particular implementation. This abstraction can then be subsequently refined to obtain various implementations with different tradeoffs. We do so using an approach that is fully compatible with the standard's notion of communication function blocks, which abstract underlying communication mechanisms from the application. As a contribution, we have developed a compiler that automatically synthesizes separate programs for a given distributed function block system without needing any additional middleware or run-time environment to execute the resulting distributed code. The efficacy of the proposed approach is demonstrated through an industrial case study.

This paper presents a novel, high performance and low cost execution architecture for the system level GALS programming language SystemJ, which extends Java with synchronous reactive features present in Esterel and asynchronous constructs of CSP (Communicating Sequential Processes). The new architecture is based on JOP (Java Optimized Processor), which is a hardware implementation of the Java Virtual Machine (JVM). The JOP, inherently suited to data-driven transformational operations, is extended to efficiently execute the control constructs and control flow of SystemJ. The new core, which is called RJOP (Reactive JOP) supports efficient execution of both data dominated and control dominated embedded applications. It also maintains the time-predictable execution of the applications intended for real-time embedded systems and calculation of Worst Case Reaction Time (WCRT) as provided by the original core. The initial results indicate significant performance improvement and lower resource requirements over the existing architectures used for the SystemJ execution.

This paper presents GALS-JOP processor for efficient execution of programs written in SystemJ GALS programming language, which extends Java with both synchronous and asynchronous concurrency and directly supports the design of concurrent and reactive programs that comply with globally asynchronous locally synchronous (GALS) formal model of computation (MoC). In the first step, a Java optimized processor (JOP) is enhanced with a control processor (CP), which deals with concurrency and reactivity, to design an intermediate solution, called tandem processor, or TP-JOP, in which control processor and JOP work together to implement control flow and data operations of GALS programs, respectively. Then, JOP and the CP functionalities are merged into a single processor, GALS-JOP, which enriches JOP with some key constructs and abstractions for efficient implementation of SystemJ GALS programs. Experimental results demonstrate superiority of the new processor over all other approaches for implementation of SystemJ programs so far making it suitable for embedded systems.

CAN bus systems are used in many industrial control applications, particularly automotive. Due to growing system and functional requirements, the low capacity of the CAN bus and usually strict conditions under which it is used in realtime applications, applicability of CAN bus is severely limited. The paper presents an approach for achieving high utilization and breathes new life to CAN bus based systems by proposing a dynamic offset adaptation algorithm for scheduling messages and improving message response times without any changes to a standard CAN bus. This simple algorithm, which runs on all nodes of the system, results in excellent average response times at all loads and makes the approach particularly attractive for soft real-time systems. We demonstrate the performance improvement of the proposed approach by comparisons to other approaches and introduce a new performance measure in the form of a rating function.

Modern embedded systems incorporate multiple applications that run on the same execution platform. However, due to limited resources and other constraints, not all the combinations of applications may run concurrently. This paper tackles the problem of determining which combinations of applications can run on a given hardware architecture without violating given constraints, thus creating feasible operational modes of the system. The architecture itself may include standard processors for software implementation of applications and dynamically (partially) reconfigurable hardware resources, which enable dynamic sharing of the resource in different operational modes. The paper describes the models, theoretical results, and the mode exploration algorithm to perform this task. Here, the specification is symbolically encoded so that the feasibility of modes can be tested by applying a SAT solver. In the experiment, we demonstrate how to apply our approach to build a self-organizing smart camera framework.

GALS-Designer is a framework for the design of software systems which comply with the formal Globally Asynchronous Locally Synchronous model of computation (GALS). Those systems consist of single or multiple GALS programs and their immediate environment, which can be other programs and any other modules described in SystemC. The framework integrates our libGALS library for writing GALS programs and SystemC. It enables modeling and simulation of single and multiple GALS programs within the single SystemC executable model on the host (simulation) operating system. The same GALS programs can then be run without SystemC on a target operating system for which the libGALS runtime library is available. The use of the GALS-Designer is demonstrated on an example of a complex embedded system. As libGALS can execute on multiprocessor platforms both the simulation and target models of the GALS system can take advantage of multiprocessor and multicore systems, which is not possible when using standard SystemC. Results of running simulation models of GALS programs demonstrate simulation performance improvement when executing on multicore platforms.

The use of formal models of computation in dealing with increasing complexity of embedded systems design is gaining attention. A successful model of computation must be able to handle both control-dominated and data-dominated behaviors, which are most often simultaneously present in complex embedded systems. Besides behavioral heterogeneity, direct support for modeling distributed systems is also desirable, since an increasing number of embedded systems belong to this category. In this paper, we present distributed DFCharts (DDFCharts), a language based on a formal model that targets distributed heterogeneous embedded systems. Its top hierarchical level is made suitable to capture distributed systems. Behavioral heterogeneity is addressed by composing finite-state machines (FSMs) and synchronous dataflow graphs (SDFGs). We illustrate modeling in DDFCharts with practical examples and describe its implementation on heterogeneous target architecture.

LibGALS is a library and run-time environment that extends a multi-process host operating system (OS) to support the design of Globally Asynchronous Locally Synchronous (GALS) software systems and models. LibGALS provides an application programming interface (API) that enables the designer to describe GALS concurrent programs and reactivity in sequential programming languages. Moreover, it facilitates the interface between the GALS concurrent program and other processes through the services provided by the host OS. LibGALS is also suitable as a target for code generation from GALS and synchronous concurrent languages. The experiments demonstrate code size and run-time gains when compared with other approaches to GALS system implementation.

Collaborative communication produces high power gain and significantly reduces bit error rate (BER) if both frequency and phase synchronization are achieved. In this paper a MISO collaborative communication system with imperfect phase and frequency synchronization that includes the influence of noise and fading is proposed, modeled, theoretically analyzed and simulated. Mathematical expressions are derived for the received power as a function of number of collaborative nodes and BER as a function of SNR (Eb/N0). Analytical and simulation results showed that the proposed system produces significant power gain and reduction in BER in the presence of phase errors, frequency errors, AWGN and Rayleigh fading. A detailed theoretical analysis and Monte Carlo simulation revealed that the proposed collaborative communication system is an energy efficient communication system with almost linear reduction of the required transmitted power per node as the function of the number of collaborative nodes.

The automated design of SoCs from pre-selected IPs that may require different clocks is challenging because of the following issues. Firstly, protocol mismatches between IPs need to be resolved automatically before IPs are integrated. Secondly, the presence of multiple clocks makes the protocol conversion even more difficult. Thirdly, it is desirable that the resulting integration is correct-by-construction, i.e., the resulting SoC satisfies given system-level specifications. All of these issues have been studied extensively, although not in a unifying manner. In this paper we propose a framework based on protocol conversion that addresses all these issues. We have extensively studied many SoC design problems and show that the proposed methodology is capable of handling them better than other known approaches. A significant contribution of the proposed approach is that it nicely generalizes many existing techniques for formal SoC design and integrates them into a single approach.

The IEC 61499 function block standard proposes a new specification language for describing distributed industrial control systems. The standard specifies the use of an execution control chart (ECC) for state control, with algorithm calls for data handling. The design of complex industrial systems such as baggage handling systems can be difficult because of large state-spaces or complicated component interactions. Additionally, the flat state machines used in the standard do not provide a simple method for specifying error handling within the process's execution. State machines from synchronous languages, however, have hierarchy and concurrent constructs to aid the developer. This paper presents a hierarchical and concurrent extension to ECCs, which we call HCECCs, which presents new design constructs adapted from synchronous languages in order to improve system specification with function blocks. The semantics of HCECCs, which are backward compatible with the standard, are described and design using HCECCs is compared with other specification approaches.

Collaborative communications in sensor networks is analyzed for the case when a phase error, which is result of a displacement error, exists in the system. In this paper we analyze a more realistic collaborative communication system that includes the influence of AWGN and phase error on the signal transmission. A mathematical analysis is performed to calculate the received power and bit error rate (BER). A phase error is assumed to be uniformly distributed over --πΔ to πΔ, where Δ is between 0.1 to 0.4. It is shown that received power increase as the number of sensor nodes (transmitters) increases, and that the received power decrease about 40% as the phase error increases from 0.1π to 0.4π. A detailed theoretical analysis and simulation reviled that the BER increase from 10-5 to 10-2 when the phase error increases from 0.1π to 0.4π.

IEC 61499 has been endorsed as the standard for modeling and implementing distributed industrial process measurement and control systems. The standard prescribes the use of function blocks for designing systems in a component-oriented approach. The execution model of a basic function block and the manner for event/data connections between blocks are described therein. Unfortunately, the standard does not provide exhaustive specifications for function block execution. Consequently, multiple standard-compliant implementations exhibiting different behaviors are possible. This not only defeats the purpose of having a standard but also makes verification of function block systems difficult. To overcome this, we propose synchronous semantics for function blocks and show its feasibility by translating function blocks into a subset of Esterel, a well-known synchronous language. The proposed semantics avoids causal cycles common in Esterel and is proved to be reactive and deterministic under any composition. Moreover, verification techniques developed for synchronous systems can now be applied to function blocks.

SystemJ is a language based on the Globally Asynchronous Locally Synchronous (GALS) paradigm. A SystemJ program is a collection of GALS nodes, also called clock domains, and each clock domain is a synchronous program that extends the Java language. Initial compilation of SystemJ has been to standard Java executing on a Java Virtual Machine (JVM), which is both inefficient and bulky for small embedded systems. This article proposes a new approach for compiling and executing SystemJ using a new type of virtual machine, called a Tandem Virtual Machine (TVM). The TVM approach provides an efficient implementation of SystemJ on both standard processors and resource-constrained embedded processors. The new approach is based on separating the control-driven and data-driven operations for execution on two virtual machines. While the JVM executes the data-driven operations, a Control Virtual Machine (CVM) is introduced to execute the control-driven parts of a SystemJ program. The TVM approach is capable of handling all data-driven and control-driven operations required by the GALS model. The benchmark results show that the TVM has code size improvements of over 60% on average and also a substantial improvement in execution speed over standard Java-based compilation.

Single-clock specifications with purely synchronous communication have been successfully used in capturing the behavior of small and medium scale embedded systems. In large scale embedded systems, where processes often operate at vastly different speeds, using a single clock in an entire specification can be difficult. In this paper, we present Multiclock Charts (McCharts), a language where finite state machines driven by different clocks are composed. The communication between FSMs is specified by both synchronous and asynchronous mechanisms. The essential feature in the semantics of McCharts is that a complete specification can be mapped onto a single multiclock FSM (MCFSM).

In this paper, we propose a new system-level design language, called SystemJ. It extends Java with synchronous reactive features present in Esterel and asynchronous constructs suitable for modelling globally asynchronous locally synchronous systems. The strength of SystemJ comes from its ability to offer the data processing and encapsulation elegance of Java, Esterel-like reactivity and synchrony, and the asynchronous de-coupling of CSP all within the Java framework. Using standard Java environments, for specification and modelling, or specialised reactive embedded processors, for high performance implementation, the SystemJ design flow is extremely versatile. With the increasing attention that Java gets in embedded systems, SystemJ comes to address data and control, software and hardware, modelling and implementation in a unified manner

Securing communication sessions between networked embedded systems is a major challenge that needs to be addressed as an increasing number of such systems become Internet-enabled. Securely and quickly establishing a session key between communicating nodes in a network requires authentication of node identities. In this paper, we propose a simple elliptic-curve based key negotiation protocol suitable for fully hardware implementation as a protocol on chip (PoC). The protocol uses the elliptic curve variants of both the Diffie Hellmann exchange and the Digital Signature Algorithm. Timing results demonstrate that an endto- end protocol run can be performed in as little as 28ms on a 25MHz clock, which is several times faster than previous microprocessor-based implementations of similar protocols. The results indicate that session keys can thereby have shorter lifetimes, since there is little computational overhead in re-generating them, thus enhancing overall security of the networked embedded systems.

Efficient scheduling mechanisms are essential for implementing real-time operating systems on embedded microprocessors. Reactive processors provide mechanisms and an instruction set architecture more suitable for dealing with external signals than it is the case with traditional interrupts. By extending the reactive framework further we demonstrate simple and efficient hardwareimplemented scheduling of tasks with static priorities. The scheduler support unit is added to the reactive microprocessor core. The real-time scheduler shows substantial improvement of performance over the conventional approach of using prioritized interrupts.

Reactivity on external events is an important feature of almost all embedded systems. In this paper we present the design of a new, reactive embedded microprocessor called REMIC, that supports reactivity in a new way following the paradigm of synchronous system level language Esterel. The rationale for REMIC design, its novel features with the design details and some performance figures are presented to demonstrate its suitability for embedded systems. Besides single processor systems, REMIC can be easily combined into multiple processor architectures that support real concurrency.

Specification of embedded systems based on formal models of computation is gaining importance. The behavior of an increasing number of embedded systems is heterogeneous, consisting of a mixture of control-dominated and data-dominated parts. While models of computations suitable to control-dominated systems and data-dominated systems are well developed, there are only a limited number of models catering to both systems. In this paper, we present informally a new model for heterogeneous embedded systems, called HEMOC, which combines three common models of computation, synchronous reactive, hierarchical finite state machines and synchronous data flow. Then, the languages Esterel and SyncCharts are used for system specification following the new model in order to determine what they need to become suitable specification platform.

Esterel is a system-level language for the modelling, verification and synthesis of control dominated (reactive) embedded systems. Existing Esterel compilers generate intermediate C code that is subsequently mapped to a suitable target processor. The generated code emulates the reactive features of the language due to lack of support for these features on traditional processors. The resultant code is thus inefficient and bulky. Therefore, Esterel is not so effective for resource constrained embedded systems. This paper describes a reactive microcontroller called RePIC that has native support for reactive features of the language. Limited support for concurrent Esterel programs is demonstrated through a dual-processor RePIC architecture. A new benchmark suite for comparing the reactive performance of processors called the Auckland Reactive Benchmark (ARE-Bench) is used to demonstrate significant performance improvement and code compaction due to the proposed approach. This paper, thus, paves the way for resource constrained embedded system development using a subset of Esterel supported by RePIC like architectures.

The multiobjective genetic algorithm is an effective solution to the complex problem of hardware-software codesign. An extended genetic algorithm (EGA) has been developed that implements a novel selection method with function scaling, adaptive crossover and mutation. This EGA is applied in a codesign optimization stage for dataflow oriented applications and synthesis on field-programmable gate arrays (FPGAs). Its effectiveness is illustrated on the problem of codesign of a self-tuning regulator considering area and performance.

A generic field-programmable logic device (FPLD)-based fuzzy logic system aimed at high-speed applications that can be easily customized for practically any application is presented. It implements fuzzy logic systems that vary in terms of the numbers of inputs and outputs and their accuracy, the membership functions (MFs), fuzzy rules, and the speed at which new outputs have to be generated. This is achieved by using the sysstem's unique architecture and its parameterized description, which is based on VHDL generics. The system can be used as either a stand-alone system or as an application-specific co-processor added to standard or customized microprocessors.