We propose a hybrid power model for estimating the power dissipation of a design at the RT-level. This new model combines the advantages of both RT-level and gate-level approaches. We investigate the relationship between steady-state transition power and overall power dissipation. We observe that, statistically, two input sequences causing similar amount of steady-state transitions will exhibit similar overall power dissipation for an RTL module. Based on this observation, we propose a method to construct a hybrid power model for RTL modules. We further propose a hierarchical power estimation method for estimating the power dissipation of data-path consisting of RTL modules. Experimental results show that, for full-chip power estimation, the estimation time of the technique based on our power models is on average 275 times faster than directly running a commercial transistor-level power simulator, and the errors are less than 6% as compared to the transistor-level power simulation results.

In this paper, we propose a hybrid approach for estimating the switching activities of the internal nodes in logic circuits. The new approach combines the advantages of the simulation-based techniques and the probability-based techniques. We use the user-specified control sequence for simulation, and treat the weakly correlated data inputs using the probabilistic model. The new approach, on one hand, is more accurate than the probabilistic approaches because the strong temporal and spatial correlations among control inputs are well taken into consideration. On the other hand, the new approach is much more efficient than the simulation-based approaches because the weakly correlated data inputs are not explicitly simulated. We also discuss the situation where BDD's are built in terms of internal nodes so that large circuits can he handled. Extensive experimental results are presented to show the effectiveness and efficiency of our algorithms.

In this paper, we propose a hybrid approach for estimating the switching activities of the internal nodes in logic circuits.The new approach combines the advantages of the simulation-based t e chniques and the probability-based t e chniques.We use the user-speci ed control sequence for simulation and treat the weakly correlated data inputs using the probabilistic model.The new approach, on one hand, is more a c curate than the probabilistic approaches because the strong temporal and spatial correlations among control inputs are well taken into consideration.On the other hand, the new approach is much more ecient than the simulation-based approaches because the weakly correlated data inputs are not explicitly simulated.In addition, we also propose a heuristic that builds BDDs in terms of internal nodes such that large circuits can be handled.Extensive experimental results are p r esented to show the eectiveness and eciency of our algorithms.

Article Free Access Share on Novel routing schemes for IC layout part I: Two-layer channel routing Author: Deborah C. Wang Department of Electrical Engineering and Computer Science, Electronics Research Laboratory, University of California, Berkeley, CA Department of Electrical Engineering and Computer Science, Electronics Research Laboratory, University of California, Berkeley, CAView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 49–53https://doi.org/10.1145/127601.127626Published:01 June 1991Publication History 20citation1,019DownloadsMetricsTotal Citations20Total Downloads1,019Last 12 Months24Last 6 weeks8 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper presents an optimum scheme for interconnecting the chip core and the I/O pads in the final stage of physical design. The pad placement routine, based on linear assignment, determines the dimension of the pad ring and selects the optimum position for each pad with the objective of minimizing the chip area and the total wire length. The router is based on a channel routing algorithm which incorporates additional features to address the special needs of the ring configuration. It attempts to achieve 100% routing completion in a rectangular ring-shaped area with two interconnect layers. The complete package has been implemented as part of the BEAR Layout System for custom chip design.