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Carlos García Quiñones

dblp:99/4167 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 100%
Software engineering, system software, and programming languages
2 papers
Compilers and program optimization · 100%

Topics — the 3 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › multithreading
speculative multithreading
0.112008
Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices · IEEE Trans. Parallel Distributed Syst. 2008
Compilers and program optimization › parallelization
thread-level speculation
0.112005
Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices · PLDI 2005
Processor architecture and microarchitecture
speculative execution
0.112005
Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices · PLDI 2005

Methods — techniques the papers use, named apart from their topics

speculation · 0.2hardware-software co-design · 0.2pre-computation slices · 0.1
YearPublicationVenuePosition
2008 Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices
abstract
This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads. Speculative multithreading increases single-threaded application performance by exploiting thread-level parallelism speculatively - that is, executing code in parallel even when the compiler or runtime system cannot guarantee the parallelism exists. The proposed approach is based on predicting/computing thread input values via software, through a piece of code that is added at the beginning of each thread (the pre-computation slice). A pre-computation slice is expected to compute the correct thread input values most of the time, but not necessarily always. This allows aggressive optimization techniques to be applied to the slice to make it very short. This paper focuses on the microarchitecture that supports this execution model. The primary novelty of the microarchitecture is the hardware support for the execution and validation of pre-computation slices. Additionally, this paper presents new architectures for the register file and the cache memory in order to support multiple versions of each variable and allow for efficient roll-back in case of misspeculation. We show that the proposed microarchitecture, together with the compiler support, achieves an average speedup of 2.2 for applications that conventional non-speculative approaches are not able to parallelize at all.
Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González 0001, Dean M. Tullsen, Hong Wang 0003, John Paul Shen
IEEE Trans. Parallel Distributed Syst.2
2005 Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices
Carlos García Quiñones, Carlos Madriles, F. Jesús Sánchez, Pedro Marcuello, Antonio González 0001, Dean M. Tullsen
PLDI1