Air pollution monitoring systems are essential for evaluating rural and industrial environmental quality for safeguarding public health. This study presents a comprehensive IoT-based framework that uses low-cost sensors and machine learning algorithms for real-time monitoring of various pollutants, including LPG, methane, CO, alcohol, PM2.5, PM10, temperature, and humidity. The system gathers sensor data from a gateway node, which is then processed using Support Vector Machines (SVM) and Random Forest Regression (RFR) models to predict pollutant concentrations. Our approach features innovative methodologies for data validation, anomaly detection, and predictive modeling, employing Root Mean Squared Error (RMSE) as the performance metric. The model achieved a remarkably low RMSE value of 0.022, significantly improving the accuracy and reliability of air quality assessments. Experimental results highlight the system's capability to capture complex environmental patterns and predict pollutant levels with high precision. This research intends air pollution monitoring from cost-effective Internet of Things (IoT) solutions and machine learning techniques. Additionally, the user interface is designed for mobile applications, offering real-time data access, alerts, and notifications, thereby enabling personalized environmental health management and targeted pollution control strategies in industrial areas.

The Smart Grid concept evolved from the idea of intelligent and secure management of electrical grid infrastructure components and their communication through sustainable integration with the state-of-the-art technologies. This research focuses on emerging quantum computing-assisted security and its application in the Smart Grid. The robustness of electrical grid is increasing every day through advancements in grid infrastructure management which include outage control, relay protection, reliable distribution, renewable energy resource integration, and energy trading. Quantum Computing emerges as a formidable solution for application in the smart grid due to its processing capability and scale. Its application and scope are evolving every day with the recent developments in Quantum Chips which could pave the way for emerging Quantum-Chain-of-Things (QCoT). This research focuses on providing robust security in smart grids through Quantum Physical Unclonable Functions (QPUF) primitive, a quantum-hardware assisted security approach driven by micro manufacturing quantum process variations for generating a quantum digital fingerprint driven by quantum mechanics principles. The QPUF experimental evaluation in this research was performed to uniquely fingerprint various electrical grid entities providing a sustainable and secure flow of communication. Experimental evaluation shows a robust and reliable extraction of quantum digital fingerprints from noisy IBM quantum systems. The evaluation shows an impressive 86% keys achieving 100% reliability.

Sustainable advancement is being made to improve the efficiency of the generation, transmission, and distribution of renewable energy resources, as well as managing them to ensure the reliable operation of the smart grid. Supervisory control and data acquisition (SCADA) enables sustainable management of grid communication flow through its real-time data sensing, processing, and actuation capabilities at various levels in the energy distribution framework. The security vulnerabilities associated with the SCADA-enabled grid infrastructure and management could jeopardize the smart grid operations. This work explores the potential of Quantum Physical Unclonable Functions (QPUF) for the security and reliability of the smart grid’s energy transmission and distribution framework. Quantum computing has emerged as a formidable security solution for high-performance computing applications through its probabilistic nature of information processing. This work has a quantum hardware-assisted security mechanism based on intrinsic properties of quantum hardware driven by quantum mechanics to provide tamper-proof security for quantum computing-driven smart grid infrastructure. This work introduces a novel QPUF architecture using quantum logic gates based on quantum decoherence, entanglement, and superposition. This generates a unique bitstream for each quantum device as a fingerprint. The proposed QPUF design is evaluated on IBM and Google quantum systems and simulators. The deployment on IBM quantum (ibmq_qasm_simulator) and Google Cirq simulators has achieved 100% reliability with an average Hamming distance of 50.07%, 51% randomness.

Hardware Trojans are deliberate malicious hardware modifications inserted in semiconductor Integrated Circuits (ICs) for the purpose of stealing or leaking sensitive information, as well as disrupting critical systems upon activation. Emerging hardware security research highlights the criticality of employing AI for effective detection within the semiconductor IC supply chain. The efficient detection of these malicious Trojan circuits is of utmost significance, as it holds paramount importance in cultivating trust within the semiconductor IC supply chain. However, prevailing detection methodologies, predominantly reliant on Side-Channel Analysis (SCA), often necessitate the utilization of golden chips for validation. This article heralds a new era in hardware Trojan detection, harnessing the prowess of unsupervised machine learning in conjunction with SCA to eliminate the need for golden data. Employing unsupervised clustering, the methodology not only showcased a superior false-positive rate but also demonstrated a comparable accuracy level when compared to supervised counterparts. Notably, the proposed model exhibited an impressive accuracy rate of 93%, particularly excelling in pinpointing diminutive Trojans triggered by concise events, surpassing the capabilities of preceding techniques. In conclusion, this research advances a paradigm in hardware Trojan detection, emphasizing its potential in enhancing the integrity of semiconductor IC supply chains.

Street lighting is one of the prominent applications that demand a massive amount of power and substantially contributes to the energy budget of a country. Light Emitting Diode (LED) and the advancement of Internet of Things (IoT) have significantly improved conventional street light technology. Nevertheless, the rapid growth of IoT devices has presented a formidable challenge in powering the vast array of IoT devices. In this manuscript, a sustainable, battery-free, low-power street light management system has been proposed which is powered from hybrid solar and solar thermal energy harvesting scheme integrated with an efficient power management unit. As a specific case study, the prototype has been implemented with an existing LED street light in India. The characteristics and performance of the prototype have been evaluated to ensure its seamless operation under real-world scenarios. The average power consumption of the system is measured as 2.088 mW when operating in real-time with 50% duty cycle, exhibiting high Quality of Service (QoS). It features long-range communication up to 761 m through implementing LoRaWAN technology. Dimension of the prototype has been restricted to 10.5 cm x 6.5 cm x 2.3 cm to make it suitable for retrofitting with existing LED based street lights

The proliferation of interconnected devices in the era of the Internet of Things (IoT) has given rise to the need for robust device identity management and authentication mechanisms in cyber-physical systems (CPSs). Traditional centralized approaches to identity management face challenges of security, scalability, and privacy. Therefore, the paper provides an innovative approach by fusing Self-Sovereign Identity (SSI) with blockchain technology to revolutionize device identity management within CPS environments. In this paper, devices autonomously initiate their identity-creation processes. Each device generates a cryptographic key pair comprising a public key for openly identifying the device and a closely guarded private key used for authentication and decryption purposes. The research also introduces an innovative authentication algorithm within CPS environments that employs secure tokens to validate the authenticity of devices. The proposed framework reduces the risk of unauthorized access and data breaches while empowering devices with control over their identities. Overall, the proposed approach not only enhances security, privacy, and resilience within CPSs but also provides a transformative solution for identity management in dynamic and autonomous device environments.

Physical Unclonable Functions (PUFs) are widely researched in the field of security because of their unique, robust, and reliable nature, PUFs are considered device-specific root keys that are hard to duplicate. There are many variants of PUFs that are being studied and implemented including hardware and software PUFs. Though PUFs are believed to be secure and reliable, they are not without challenges of their own. The efficient performance of PUF depends on various environmental factors, which leads to inefficiency. Bit flipping is one such problem that can bring down the reliability of the PUF. Memory-based PUFs are prone to unavoidable bit flips occurring in the hardware, similarly, sensor-based PUFs are prone to bit flips occurring due to temperature variation. The number of errors in the PUF response must be minimized to improve the reliability of the PUF in security applications. In this research we explore the Machine Learning (ML) model based on K-mer sequencing to detect and correct the bit flips in the PUFs, hence fortifying the PUF-based secure authentication system for authentication and authorization of Edge Data Centers (EDC) in a Collaborative Edge Computing (CEC) Environment.

Deepfake has emerged as a threat to individual’s privacy and identity. It uses advanced deep learning algorithms to synthesize visual, text, and audio from multimedia content in a realistic way. The advancement of Deepfake techniques is posing a question on the integrity of the digital content on social media. This work presents a novel hardware assisted Deepfake mitigation approach through the device and content integrity verification. In this work, the potential of hardware security primitive Physical Unclonable Functions (PUF) for mitigation of visual Deepfakes has been explored. The proposed framework presents a novel PUF-based image attestation technique that uses human facial features to create a unique pseudo-identity. The proposed architecture maps facial key point coordinates of each person in an image to PUF and creates a unique PUF generated key thereby having a unique pseudo identity for each image. Experimental evaluation uses Dlib facial detection model for facial attribute extraction and uses Arbiter PUF for image attestation.

Heterogeneous chiplets have been proposed for accelerating high-performance computing tasks. Integrated inside one package, CPU and GPU chiplets can share a common interconnection network that can be implemented through the interposer. However, CPU and GPU applications have very different traffic patterns in general. Without effective management of the network resource, some chiplets can suffer significant performance degradation because the network bandwidth is taken away by communication-intensive applications. Therefore, techniques need to be developed to effectively manage the shared network resources. In a chiplet-based system, resource management needs to not only react in real-time but also be cost-efficient. In this work, we propose a reconfigurable network architecture, leveraging Kalman Filter to make accurate predictions on network resources needed by the applications and then adaptively change the resource allocation. Using our design, the network bandwidth can be fairly allocated to avoid starvation or performance degradation. Our evaluation results show that the proposed reconfigurable interconnection network can dynamically react to the changes in traffic demand of the chiplets and improve the system performance with low cost and design complexity.

Billions of devices on the Internet of Things (IoT) capture massive amounts of data from everyday events, raising privacy and security concerns. The current technology standard transfers the majority of this data over the internet stores it, processes it, and uses it to train machine learning (ML) and deep learning (DL) models on the cloud server. Then, edge devices make decisions. However, this threatens data privacy and security. Federated learning (FL) can be helpful in this scenario because it transfers the model to the data. However, issues like poor network connectivity, low bandwidth, and network latency demand more research on edge-based models, on-device training, and lightweight and low-overhead communication protocols. In this article, we present ToEFL, an incremental training (T) on (o) edge (E) method for an FL network in a smart agriculture application, addressing data bottlenecks and low computational capability constraints. We selected plant disease detection as the application. The whole idea is to train the model on the edge device to reduce the frequency of server updates and make ToEFL suitable for a remote village where internet service may be poor. The ToEFL system can choose between server and local models based on model performance, with the latter more tailored to a local dataset.

This article asserts that Artificial Intelligence (AI) has been the focus of research in recent years, and the Internet of Things devices powered by AI are proven to perform better than general purpose, but has given rise to a new set of challenges in privacy and security. The authors agree that a potential solution to improve security is through Hardware Assisted Security (HAS).

Physical Unclonable Functions (PUFs) are widely studied for the security of devices in the largely heterogenous Internet-of-Things ecosystem. The need for low-power and low-cost yet robust and reliable security systems is of prime importance in resource-constrained environments like smart villages. Using PUFs as a security primitive has the limitation of environmental effects that lead to bit flipping in the PUF response, the challenge in using PUFs is to overcome the bit errors without adding to the area overhead or computational overhead. This research proposes a novel bit error detection and correction algorithm implemented using Federated Learning (FL). The error detection and correction model uses the N-gram concept of Natural Language Processing (NLP). The FL model is implemented on Flower AI, the global model gets the locally trained model's parameters, updates itself, and shares the updated models with all the local models. At the edge, the use of FL for model training and updating enhances the efficiency of the authentication system that uses PUF Challenge-Response Pairs (CRPs), reduces the area overhead and power consumption, and improves the security of the PUF-based authentication system.

The increasing threat to individual privacy and personalized digital content on social media posed by Deepfakes has highlighted the importance for a secure and reliable multimedia content integrity mechanism. In this paper a novel Blockchain driven hardware secure video attestation scheme, BlockShield is proposed for Deepfake mitigation. The proposed system includes a novel approach that ensures digital content traceability and privacy using Blockchain smart contracts and TPM's digital signature mechanism. The proposed work explores the scope of hardware-assisted security for Deepfake mitigation through a hardware TPM working together with Blockchain for enhanced digital media protection and sharing. The proposed work is experimentally validated and presented which validates the scope of hardware-assisted and blockchain integrated Deepfake mitigation framework.

Food is crucial in our life. Despite food manufacturers' efforts to meet consumers' needs with manufactured food, it cannot attain the identical level of quality and flavor as natural food. Some fruits and vegetables are classified as food that cannot be manufactured. Also, they play an essential role worldwide. This paper focuses on how farmers can protect their farms from an object that might threaten the crops and cause damage to them. It proposes a framework that farmers may utilize to safeguard the crops against any species of birds. Considering the adverse impact of bird attacks on crop production, this system effectively addresses this problem and consistently enhances the quality and quantity of them. It utilizes computer vision technology to establish a secure environment for the crop. This system is called Quality of Crop Device (qCrop), and it works with a You Only Look Once (Yolov8m) model to detect birds with high accuracy to protect farms.

Public lighting is a ubiquitous utility in cities to ensure the safety of people. In addition to playing a significant role in amending the comfort and safety of cities, street lighting causes substantial financial burden on governments to maintain its operation. Smart Light Emitting Diode (LED) street light system has become a prominent alternative to conventional street lighting systems with the involvement of Internet of Things (IoT). In this manuscript, a supercapacitor based smart street management system with energy autonomous capability has been proposed. It works in real-time and as an energy-saving alternative to prevent unnecessary electricity consumption of the street light. The average current consumption and power consumption of the system are 619.14$\mu$A and 2.022 mW, respectively. Three charging schemes have been investigated to find the optimized topology to harvest energy. The proposed device harvests energy from ambient sunlight and artificial light using a solar cell of 64 mm x 37 mm x 0.22 mm with maximum output power of 66 mW. LoRaWAN has been incorporated for communication, with a communication range of 761 m in real-world testbed. The operation characteristics and performance evaluation has been done based on implementing the system in field to ensure seamless operation.

Logic locking has become a robust method for reducing the risk of intellectual property (IP) piracy, overbuilding, and hardware Trojan threats throughout the lifespan of integrated circuits (ICs). Nevertheless, the majority of reported logic locking approaches are susceptible to satisfiability (SAT)-based attacks. The existing SAT-resistant logic locking methods provide a tradeoff between security and effectiveness and require a significant design overhead. In this article, a novel gate replacement-based input-dependent key-based logic locking (IDKLL) technique is proposed. We first introduce the concept of IDKLL, and how the IDKLL can mitigate the SAT attacks completely. Unlike conventional logic locking, the IDKLL approach uses multiple key sequences (KSs) (instead of a single KS) as the correct key to lock/unlock the design functionality for all inputs. Based on this IDKLL concept, we developed several locked gates. Further, we propose a lightweight gate replacement-based IDKLL called GateLock that locks the design by replacing exciting gates with their respective IDKLL-based locked gates. The security analysis of the proposed method shows that it prevents the SAT attack completely and forces the attacker to apply a significantly large number of brute-force attempts to decipher the key. The experimental evaluation on International Symposium on Circuits and Systems (ISCAS) and International Test Conference (ITC) benchmarks shows that the proposed GateLock method completely prevents the SAT-based attacks and requires an average of 56.7%, 72.7%, and 87.8% reduced area, power, and delay compared to cascaded locking (CAS-Lock) and strong Anti-SAT (SAS) approaches.

Collaborative Edge Computing (CEC) works on the distributed model, and is established at the Fog layer that consists of multiple edge devices like Edge Data Centers (EDCs), Edge Routers etc. In the CEC environment, the Edge layer has the capability of storing and processing data. Since the processing capacity is limited, many edge devices collaborate with each other to offload the processing in a scheme called Load Balancing. CEC enables applications in smart villages through task offloading/sharing, which calls for a trusted security system to make the resource sharing and information safe. Since the Edge is a resource-constrained environment where not all data centers are resourceful enough to implement computation intensive security systems. Physically Unclonable Functions (PUF) are a robust, secure, and light-weight solution for providing hard- ware security. PUFs are used to authenticate the EDCs during load balancing in a collaborative edge computingenvironment. Though PUFs are secure and difficult to remodel, the drawback lies in the storage of Challenge-Response Pairs (CRP) in a CRP database. The storage space for the CRP database becomes a concern when many EDCs participate in dynamic load balancing and each EDC needs to store a copy of the database. This research proposes a PUF based certificate Authority protocol for authentication of EDCs which will eliminate the need for CRP database storage while harnessing the security feature of the PUF. Further, in this research the effised authentication system is evaluated through oretical analysis and experimental results.

In smart healthcare, blockchain technology addresses existing concerns with security, privacy, and electronic healthcare records. In addition, utilizing edge devices with IoMT devices is very advantageous for addressing security, computing, and storage challenges. Symmetric and asymmetric keys are used to conceal sensitive information from unauthorized parties. Moreover, the hash function SHA256 helps for data alteration detection. The proposed system uses a blockchain-based smart healthcare system using IoMT devices for continuous patient monitoring. The edge device is used to hash and encrypt data and provide additional computational capability. A symmetric key maintains data privacy in the blockchain, allowing patients to safely share data through smart contracts while preventing unauthorized physicians from seeing it. A verification node and blockchain sign and validate patient data in the healthcare provider system using an asymmetric key. Location-based authentication is addressed to ensure the authenticity and data source.

This work presents a sustainable cybersecurity solution using Physical Unclonable Functions (PUF), Trusted Platform Module (TPM), and Tangle Distributed Ledger Technology (DLT) for sustainable device and data security. Security-by-Design (SbD) or Hardware- Assisted Security (HAS) solutions have gained much prominence due to the requirement of tamper-proof storage for hardwareassisted cryptography solutions. Designing complex security mechanisms can impact their efficiency as IoT applications are more decentralized. In the proposed architecture, we presented a novel TPM-enabled PUF-based security mechanism with effective integration of PUF with TPM. The proposed mechanism is based on the process of sealing the PUF key in the TPM, which cannot be accessed outside the TPM and can only be unsealed by the TPM itself. A specified NV-index is assigned to each IoT node for sealing the PUF key to TPM using the Media Access Control (MAC) address. Access to the TPM's Non-Volatile Random Access Memory (NVRAM) is defined by the TPM's Enhanced Authorization policies as specified by the Trust Computing Group (TCG). The proposed architecture uses Tangle for sustainable data security and storage in decentralized IoT systems through a Masked Authentication Messaging (MAM) scheme for efficient and secure access control to Tangle. We validated the proposed approach through experimental analysis and implementation, which substantiates the potential of the presented PUFchain 4.0 for decentralized IoT-driven security solutions.

The Internet of Medical Things (IoMT) technology’s fast advancements aided smart healthcare systems to a larger extent. IoMT devices, on the other hand, rely on centralized processing and storage systems because of their limited computational and storage capacity. The reliance is susceptible to a single point of failure (SPoF) and erodes the user control over their medical data. In addition, Cloud models result in communication delays, which slow down the system’s overall reaction time. To overcome these issues a decentralized distributed smart healthcare system is proposed that eliminates the SPoF and third-party control over healthcare data. Additionally, the proposed Fortified-Chain 2.0 uses a blockchain-based selective sharing mechanism with a mutual authentication technique to solve the issues, such as data privacy, security, and trust management in decentralized peer-to-peer healthcare systems. Also, we suggested a hybrid computing paradigm to deal with latency, computational, and storage constraints. A novel distributed machine learning (ML) module named random forest support vector machine (RFSVM) also embedded into the Fortified-Chain 2.0 system to automate patient health monitoring. In the RFSVM module, a random forest (RF) is used to select an optimal set of features from patients data in real-time environment and also support vector machine (SVM) is used to perform the decision making tasks. The proposed Fortified-Chain 2.0 works on a private blockchain-based distributed decentralised storage system (DDSS) that improves the system-level transparency, integrity, and traceability. Fortified-Chain 2.0 outperformed the existing Fortified-Chain in terms of low latency, high throughput, and availability with the help of a mutual authentication method.

Recently, harvesting natural energy is gaining more attention than other conventional approaches for sustainable IoT. System on chip power requirement for the internet of things (IoT) and generating higher voltages on chip is a massive challenge for on-chip peripherals and systems. In this article, an on-chip reliable energy-harvesting system (EHS) is designed for IoT with an inductor-free methodology. The control section monitors the computational load and the recharging of the battery/super-capacitor. An efficient maximum power point tracking algorithm is also used to avoid quiescent power consumption. The reliability of the proposed EHS is improved by using an aging tolerant ring oscillator. The effect of Trojan on the performance of energy-harvesting system is analyzed, and proper detection and mitigation mechanism is proposed. Finally, the proposed ripple mitigation techniques further improves the performance of the aging sensor. The proposed EHS is designed and simulated in CMOS 90-nm technology. The output voltage is in the range of 3–3.55 V with an input 1–1.5 V with a power throughput of 0–22 μW. The EHS consumes power under the ultra-low-power requirements of IoT smart nodes.

No abstract available.

Cyber–physical systems (CPSs) have developed rapidly in recent years, contributing to an efficient integration between the cyber and physical worlds in intelligent and connected city environments. However, efficient mobility in a CPS is not well solved. Here, we present a prototype for a privacy-aware secure human-centric mobility-aware (SHM) model proposed and tested to analyze physical and human domains in IoT-based wireless sensor networks (WSNs). The proposed SHM model involves five modules: 1) sensor advertisements; 2) mobile sensor recruitment; 3) load balancing; 4) transmission guarantee; and 5) privacy with data-sharing phases. The proposed model is also validated using an accurate testing method that involves software and hardware tools and mathematical modeling to confirm secure communication. The model provides a tradeoff between energy efficiency and Quality-of-Service (QoS) requirements and compares the performance with other known models/protocols. Our testing process continued for four days, demonstrating that the SHM model provides compelling features of a secure CPS based on actual testing results. In practice, our model can be used in hospitals, as evident from validation in a real-life environment following the protocols.

Smart vehicles-enabled intelligent transportation system (ITS) supports a wide range of applications, such as, but not limited to, traffic planning and management, collision avoidance alert system, automated road speed enforcement, electronic toll collection, and real-time parking management, to name a few. However, it suffers from various types of security and privacy issues due to insecure communication among the entities over public channels. Therefore, an efficient and lightweight security mechanism is essential to protect the data that is both at rest as well as in transit. To this direction, we propose a public blockchain-envisioned secure communication framework for ITS (PBSCF-ITS). The proposed PBSCF-ITS guarantees access control and key management among the vehicle to vehicle, vehicle to roadside unit, and roadside unit to cloud server. We analyze the security of PBSCF-ITS to prove its resilience against various types of possible attacks. Furthermore, the performance of PBSCF-ITS with other related competing schemes has been compared. The obtained results illustrate that PBSCF-ITS outperforms the existing ones. Additionally, the pragmatic study of PBSCF-ITS is conducted to check its influence on various network-related performance parameters, like the number of mined blocks and transactions per block.

Within vehicles, the Controller Area Network (CAN) allows efficient communication between the electronic control units (ECUs) responsible for controlling the various subsystems. The CAN protocol was not designed to include much support for secure communication. The fact that so many critical systems can be accessed through an insecure communication network presents a major security concern. Adding security features to CAN is difficult due to the limited resources available to the individual ECUs and the costs that would be associated with adding the necessary hardware to support any additional security operations without overly degrading the performance of standard communication. Replacing the protocol is another option, but it is subject to many of the same problems. The lack of security becomes even more concerning as vehicles continue to adopt smart features. Smart vehicles have a multitude of communication interfaces an attacker could exploit to gain access to the networks. In this work, we propose a security framework that is based on physically unclonable functions (PUFs) and lightweight cryptography (LWC). The framework does not require any modification to the standard CAN protocol while also minimizing the amount of additional message overhead required for its operation. The improvements in our proposed framework result in major reduction in the number of CAN frames that must be sent during operation. For a system with 20 ECUs, for example, our proposed framework only requires 6.5% of the number of CAN frames that is required by the existing approach to successfully authenticate every ECU.

introduction Share on Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things Editors: Saraju P. Mohanty University of North Texas University of North TexasView Profile , Jim Plusquellic University of New Mexico University of New MexicoView Profile , Garrett S. Rose University of Tennessee, Knoxville University of Tennessee, KnoxvilleView Profile , Wei Zhang Hong Kong University of Science and Technology Hong Kong University of Science and TechnologyView Profile , Maria K. Michael University of Cyprus University of CyprusView Profile Authors Info & Claims ACM Journal on Emerging Technologies in Computing SystemsVolume 18Issue 1January 2022 Article No.: 1pp 1–3https://doi.org/10.1145/3475952Online:29 September 2021Publication History 0citation90DownloadsMetricsTotal Citations0Total Downloads90Last 12 Months90Last 6 weeks12 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The use of the Internet of Things and modern technologies has boosted the expansion of e-health solutions significantly and allowed access to better health services and remote monitoring of patients. Every service provider usually implements its information system to manage and access patient data for its unique purpose. Hence, the interoperability among independent e-health service providers is still a major challenge. From the structure of stored data to its large volume, the design of each such big data system varies, hence the cooperation among different e-health systems is almost impossible. In addition to this, the security and privacy of patient information is a challenging task. Building a unified solution for all creates significant business and economic issues. In this article, we present a solution to migrate existing e-health systems to a unified Blockchain-based model, where access to large scale medical data of patients can be achieved seamlessly by any service provider. A core blockchain network connects individual & independent e-health systems without requiring them to modify their internal processes. Access to patient data in the form of digital assets stored in off-chain storage is controlled through patient-centric channels and policy transactions. Through emulation, we show that the proposed solution can interconnect different e-health systems efficiently.

The rapid developments in the Internet of Medical Things (IoMT) help the smart healthcare systems to deliver more sophisticated real-time services. At the same time, IoMT also raises many privacy and security issues. Also, the heterogeneous nature of these devices makes it challenging to develop a common security standard solution. Furthermore, the existing cloud-centric IoMT healthcare systems depend on cloud computing for electrical health records (EHR) and medical services, which is not suggestible for a decentralized IoMT healthcare systems. In this article, we have proposed a blockchain-based novel architecture that provides a decentralized EHR and smart-contract-based service automation without compromising with the system security and privacy. In this architecture, we have introduced the hybrid computing paradigm with the blockchain-based distributed data storage system to overcome blockchain-based cloud-centric IoMT healthcare system drawbacks, such as high latency, high storage cost, and single point of failure. A decentralized selective ring-based access control mechanism is introduced along with device authentication and patient records anonymity algorithms to improve the proposed system's security capabilities. We have evaluated the latency and cost effectiveness of data sharing on the proposed system using Blockchain. Also, we conducted a logical system analysis, which reveals that our architecture-based security and privacy mechanisms are capable of fulfilling the requirements of decentralized IoMT smart healthcare systems. Experimental analysis proves that our fortified-chain-based H-CPS needs insignificant storage and has a response time in the order of milliseconds as compared to traditional centralized H-CPS while providing decentralized automated access control, security, and privacy.

Software-Defined Networking has become an integral technology for large scale networks that require dynamic flow management. It separates the control function from data plane devices and centralizes it in a domain controller. However, only a limited number of switches can be managed by a single and centralized controller which introduces challenges such as scalability, reliability, and availability. Distributed controller architecture resolves these issues but also introduces new challenges of uneven load and traffic management across domains. As real-world networks have redundant links, hence a significant challenge is to distribute traffic flows on multiple paths, within a domain, and across multiple independent domains. The selection of ingress and egress switches becomes even more problematic if the intermediate domain is non-cooperative. In this work, we propose a Dynamically Optimized and Load-balanced Path for Inter-domain (DOLPHIN) communication system, a customized solution for different SDN controllers. It provides control beyond the virtual switch elements in intra and inter-domain communication and extends the range of programmability to wireless devices, such as the Internet of Things or vehicular networks. Extensive simulation results show that the traffic load is distributed evenly on multiple links connecting different domains. We model data center communication and 5G vehicular network communication to show that, by load balancing the flow completion times of the different types of network traffic can be significantly improved.

Security and energy-consumptiont are two conflicting challenges in the design and operation of the smart cities that use Internet-of-Things (IoT). Providing power to IoT things (i.e., sensors and their communications) is a challenge as battery have a limited lifetime, and their maintenance and disposal are costly and hazardous. System on chip (SoC) power requirements for IoT ultra-low-power realm is different and is a challenge for the design engineers to provide uninterrupted power. In this paper, a paradigm shift research that addresses a secure self-sustainable solar-energy harvesting system (EHS) with a security mechanism is proposed. This design incorporates Physically Unclonable Functions (PUFs) for the security of EHS along with an aging sensor for recycled IC detection. The control unit monitors the computational load, recharging of the battery, and security mechanism. Capacitor value modulation (CVM) is used for impedance matching between solar cell and converter during maximum power point tracking (MPPT) to avoid quiescent power consumption. The existing resources of EHS used for designing the PUFs and aging sensor. The secure EHS is designed and fabricated in CMOS 90nm technology. The resulting output is in the range of 3-3.55 V with an input 1-1.5 V. The proposed EHS is consuming 22 μW of power, that satisfies the ultra-low-power requirements of IoT smart nodes.

Efficient and smart business processes are heavily dependent on the Internet of Things (IoT) networks, where end-to-end optimization is critical to the success of the whole ecosystem. These systems, including industrial, healthcare, and others, are large scale complex networks of heterogeneous devices. This introduces many security and access control challenges. Blockchain has emerged as an effective solution for addressing several such challenges. However, the basic algorithms used in the business blockchain are not feasible for large scale IoT systems. To make them scalable for IoT, the complex consensus-based security has to be downgraded. In this article, we propose a novel lightweight proof of block and trade (PoBT) consensus algorithm for IoT blockchain and its integration framework. This solution allows the validation of trades as well as blocks with reduced computation time. Also, we present a ledger distribution mechanism to decrease the memory requirements of IoT nodes. The analysis and evaluation of security aspects, computation time, memory, and bandwidth requirements show significant improvement in the performance of the overall system.

With the rapid development and increasing complexity of computer systems and communication networks, user requirements for trust, security, and privacy are becoming more and more demanding. Therefore, there is a grand challenge that traditional security technologies and measures may not meet user requirements in open, dynamic, heterogeneous, mobile, wireless, and distributed computing environments. Thus, there is a strong need to build systems and networks in which various applications allow users to enjoy more comprehensive services while preserving trust, security, and privacy at the same time. As useful and innovative technologies, trusted computing and communications are attracting researchers with more and more attention. The scope of this special issue is broad and is representative of many important topics involving emerging technologies in the field of Trust, Security, Privacy, Forensics, and Data analytics. In addition, the articles selected through this special issue also present strong aspects on theoretical analysis, algorithms, and practical experience in their proposed schemes. The submissions to the Special Issue were significantly extended research papers from the 16th IEEE International Conference on Trust, Security and Privacy in Computing and Communications (Trustcom 2017). This conference brings together researchers and practitioners around the world working on trusted computing and communications, with regard to trust, security, privacy, reliability, dependability, survivability, availability, and fault tolerance aspects of computer systems and networks. All the submissions for this special issue have been reviewed rigorously following the guidelines of Wiley Journal on Concurrency and Computation: Practice and Experience (CCPE). A majority of the reviewers represent expertise in their fields who provided high quality reviews for the manuscripts. The articles selected through a rigorous reviews process for this Special Issue are briefly presented in the rest of this guest editorial. The guest editors sincerely believe that this special issue on Trust, Security, and Privacy will be a great reading for the contemporary researchers worldwide. The guest editors would like to thank the editor-in-chief (EiC) Dr Geoffrey Fox of the Wiley Journal on Concurrency and Computation: Practice and Experience (CCPE) for the opportunity of this special issue. The guest editors are sincerely thankful to the many reviewers around the globe for their timely reviews without which this successful special issue would not have been possible. The guest editors thank the authors for their patience and dedication at all stages of the review process. The guest editors are also thankful to the Wiley production staffs for their help during the production of this special issue. Fault injection has been increasingly used both to attack software applications and to test system robustness. Detecting fault injection vulnerabilities has been approached with a variety of different but limited methods. Given-Wilson et al1 propose extension of a recently published general model checking–based process to detect fault injection vulnerabilities in binaries. This new extension makes the general process scalable to real-world implementations. The authors demonstrate their scheme by detecting vulnerabilities in different cryptographic implementations. Fault analysis of AEZ is based on AES using three 128-bit keys. Al Mahri et al2 analyzed AEZ 4.2 and investigated the fault issue showing all three 128-bit keys used in AEZ 4.2 can be uniquely retrieved using only three random valued single byte fault injections. Data publishing may suffer from privacy disclosures, especially, the case in transactional data such as web search and point of sales logs. Current potent privacy preserving mechanisms mainly focus on relational data. Bewong et al3 propose a new privacy metric for transactional data to prevent inference attacks. Their proposed scheme, Anony, ensures that the adversary learns no more about an intended victim than what is publicly available. In order to demonstrate the effectiveness of their scheme, the authors present empirical evaluation on three benchmark datasets. Jahan et al4 present selective read/write access to the outsourced data for clients using mobile devices supporting users from multiple domains. The authors use Ciphertext-Policy Attribute-based Encryption (CP-ABE) scheme that provides access control on encrypted outsourced data. The proposed scheme provides fine-grained read/write access to the users, accompanied with a lightweight signature scheme and computationally inexpensive user revocation mechanism suitable for resource-constrained mobile devices. Both theoretical analyses of the security protocol and experimental results measured from a real-world testbed strongly validate the proposed scheme. Yoking-proof scheme is a very useful mechanism in many IoT (Internet of Things) application areas such as health care and supply chain. However, existing yoking-proof scheme requires two or more rounds of communication to generate the yoking-proof. Sun et al5 investigate how to design the one-round yoking-proof scheme with computational efficiency. The scheme is designed with a new timestamp-based scheme for the RFID tag pair. The authors prove the security and privacy of the proposed scheme extending to more than two RFID tags along with one-round of communication to generate the yoking-proof. While Malware-based activities on recent years are slowing down, more and more sophisticated targeting malwares have been emerging. These new categories of Malwares share little or no common feature with traditional malware. Han et al6 present classifications of malicious tasks using decidable theory and prove that tasks performed by any software can be recursive and determinable. By establishing a mapping from software to task, they prove their proposition and demonstrate that presence of malwares in software is recursive. This issue would be incomplete without the article on IoT security. Secured authentication using 6LoWPAN networks is one of the important considerations among various IoT-based applications. Existing asymmetric key distribution scheme may not be a perfect choice as recent research shows that Lucky Thirteen attack has compromised Datagram Transport Layer Security (DTLS) with Cipher Block Chaining (CBC) mode for key establishment. Even though EAKES6Lo and S3 K techniques for key establishment follow the symmetric key establishment method, they strongly rely on a remote server and trust anchor. Baskaran et al7 present a Lightweight AUthentication Protocol (LAUP) using symmetric key method with no pre-shared keys between sensors and Edge Router in a 6LoWPAN environment. Their proposed scheme is formally verified using the Scyther security protocol verification tool and the protocol is implemented using COOJA simulator. Finally, the authors develop a Testbed to measure computation time and efficiency of LAUP scheme. The proposed scheme achieves less computational time and low power consumption compared to existing authentication protocols such as the EAKES6Lo and SAKES.

Internet-of-Things (IoT) is the technical backbone of smart cities which are envisioned to cope up with rapid urbanization of human population with limited resources. IoT provides three key features of smart cities such as intelligence, interconnection, and instrumentation. IoT is essentially a system-of-systems which can be considered as a configurable dynamic global network of networks. The main components of IoT include the following: 1) The Things; 2) Internet; 3) LAN; and 4) The Cloud. IoT is built by various diverse components including electronics, sensors, actuators, controllers, networks, firmware, and software. However, the existing electronics, controllers, and processors do not meet IoT requirements, such as multiple sensors, communication protocols, and security requirements. The existing computer-aided design (CAD) or electronic design automation tools are not enough to meet diverse challenges such as time-to-market, complexity, and cost of IoT. The required electronic circuits and systems need to be developed by handling and solving specific requirements. Real-time and ultralow power plays a major role since mobile devices in the IoT have to provide a long availability with a relative small energy budget. At the same time, reliability, availability, real-time constraints, and performance requirements pose significant challenges, and therefore, lead to a high interest in research. In this special issue, different approaches to design novel devices, circuits, and systems for solving the challenges with IoT are targeted. Various novel design automation components including modeling, design flows, simulation methods, and optimizations for designing of modern IoT are targeted, from system level down to device level. The current special issue was envisioned with the above technical considerations. After a rigorous review process, a set of articles were selected for this special issue. These papers are briefly discussed in the rest of the editorial.

Reusable intellectual property (IP) cores used in the consumer electronic devices, representing years of valuable investment, need protection against threats such as piracy and illegal claim of ownership. This paper introduces a novel 7-variable signature encoding driven triple-phase watermarking methodology during high level synthesis (HLS)/architectural synthesis for IP core protection of vendor rights. The proposed approach is extremely robust against external threats as it involves vendor signature comprising of 7-variable combination embedded through three independent phases of HLS. This paper is the first work in the HLS literature that presents a triple-phase watermarking process during HLS compared to single phase watermarking techniques so far. The proposed approach incurs zero delay overhead and minimal hardware overhead while embedding as well as yields average cost reductions of 7.38% and 6.25% compared to two similar approaches. Further, the proposed triple-phase watermark approach achieves a lower Pc value by ~3.2× 1027times in magnitude compared to similar approaches. Additionally, the proposed approach is 3.4 ×1043and 2.8 ×1019times more tamper tolerant than similar approaches.

Security against hardware Trojan that is capable to change the computational output value is accomplished by employing dual modular redundant (DMR) schedule during high level synthesis (HLS). However, building a DMR for Trojan security is nontrivial and incurs extra delay and hardware. This paper proposes a novel HLS methodology for constraint driven low cost hardware Trojan secured DMR schedule design for loop-based control data flow graphs (CDFGs). Proposed approach simultaneously explores an optimal schedule and optimal loop unrolling factor (U) combination for a low cost Trojan security aware DMR schedule. As a specific example, proposed low cost Trojan secured HLS approach relies on particle swarm optimization algorithm to explore optimized Trojan secured schedule with optimal unrolling that provides security against specific Trojan (causing change in computational output) within user provided area and delay constraints. The novel contributions of this paper are, first an exploration of a low cost Trojan security aware HLS solution for loop-based CDFGs; second, proposed encoding scheme for representing design solution comprising candidate schedule resources, candidate loop unrolling factor and candidate vendor allocation information; third, a process for exploring the a low cost vendor assignment that provides Trojan security; finally, experimental results over the standard benchmark that indicates an average reduction in final cost of ~12% compared to recent approach.

Intellectual property (IP) cores have emerged as a promising solution to the challenges of future design as well as mounting time to market pressure. However, due to increasing globalization of design supply chain, possibility of intervention and typical attacks is on the rise, which therefore mandates protection of IP cores from piracy/counterfeiting even at behavioral level. This paper presents a technique for generating low cost watermarking solution during high level synthesis (HLS) based on multi-variable signature encoding for security of reusable IP cores. The watermark generated by the proposed approach satisfies the following properties: (a) low embedding cost (b) robustness (c) low watermark creation time (d) strong proof of authorship (e) lower hardware overhead. Comparison with similar technique revealed that proposed approach obtains watermarked solution with lower embedding cost with less storage overhead and creation time.

No abstract available.

The high density of interconnects, closer proximity of modules, and routing phase are pivotal during the layout of a performance-centricthree-dimensional integrated circuit(3D IC). Heuristic-based approaches are typically used to handle such NP-complete problems of global routing in 3D ICs. To overcome the inherent limitations of deterministic approaches, a novel methodology for multi-objective global routing based on fuzzy logic has been proposed in this article. The guiding information generated after the placement phase is used during routing with the help of a fuzzy expert system to achieve thermally efficient and congestion-free routing. A complete global routing solution is designed based on the proposed algorithms and the results are compared with selected fully established global routers, namely Labyrinth, FastRoute3.0, NTHU-R, BoxRouter 2.0, FGR, NTHU-Route2.0, FastRoute4.0, NCTU-GR, MGR, and NCTU-GR2.0. Experiments are performed over ISPD 1998 and 2008 benchmarks. The proposed router, calledFuzzRoute, achieves balanced superiority in terms of routability, runtime, and wirelength over others. The improvements on routing time for Labyrinth, BoxRouter 2.0, and FGR are 91.81%, 86.87%, and 32.16%, respectively, for ISPD 1998 benchmarks. It may be noted that, though FastRoute3.0 achieves fastest runtime, it fails to generate congestion-free solutions for all benchmarks, which is overcome by the proposed FuzzRoute of the current article. It also shows wirelength improvements of 17.35%, 2.88%, 2.44%, 2.83%, and 2.10%, respectively, over others for ISPD 1998 benchmarks. For ISPD 2008 benchmark circuits it also provides 2.5%, 2.6%, 1 %, 1.1%, and 0.3% lesser wirelength and averagely runs 1.68×, 6.42×, 2.21×, 0.76×, and 1.54× faster than NTHU-Route2.0, FastRoute4.0, NCTU-GR, MGR, and NCTU-GR2.0, respectively.

In this paper a design optimization flow is proposed for memristor-based oscillators using the Gravitational Search Algorithm. This paper presents for the first time a memristor behavioral model in the Simscape physical modeling language. Using this model, a memristor based Wien oscillator is characterized within the Simscape framework. The oscillation frequency and power consumption of the oscillator for different configurations are explored.

With the rapid increase in the chip density, Network-on-Chip (NoC) is becoming the prevalent architecture for today's complex chip multi processor (CMP) based systems. One of the major challenges of the NoC is to design an enhanced parallel communication centric scalable architecture for the on chip communication. In this paper, a hybrid Mesh based Star topology has been proposed to provide low latency, high throughput and more evenly distributed traffic throughout the network. Simulation results show that a maximum of 62% latency benefit (for size 8x8), 55% (for size 8x8), and 42% (for size 12x12) throughput benefits can be achieved for proposed topology over mesh with a small area overhead.

With the technology trend moving towards smaller geometries and improved circuit performances, multigate transistors are expected to replace the traditional bulk devices. The double-gate FinFET lends itself to a rich design space using various configurations of the two gates. Accurate current mirroring is a critical analog design requirement in many applications. Current mirror is an essential component in analog design for biasing and constant current generation. This paper presents the exploration of different configurations of a double gate fully depleted SOI based FinFETs for efficient design of current mirror designs. In particular, comparison among the important Figures-of-Merit (FoMs) current mirror designs including mismatch, variability, output resistance ($r_0$), compliance voltage ($V_{CV}$) is presented for: (1) shorted-gate (SG), (2) independent-gate (IG), and (3) low-power (LP) configurations. Based on the results obtained, guidelines are presented for the designer for current mirror design using FinFET.

Due to the increasing complexity of nanoscale CMOS circuits and systems integration, full SPICE simulations for silicon accurate results can have run times in the order of days or weeks. This paper presents a methodology that uses a simple Kriging metamodeling technique capable of modeling the correlation effects between parameters, and a simulated annealing algorithm for ultrafast design optimization. The proposed methodology is applied to a clamped bitline amplifier circuit, which shows promising results for increased accuracy in process-aware metamodeling techniques. The error of the metamodels is very small, which is generated in 10.5 min compared to the 72 h taken for an exhaustive simulation. The design optimization performed on the metamodels improves the precharge time of the circuit by 61.15%.

The gap between abstraction levels in analog design is a major obstacle for advancing analog and mixed-signal design automation. Intelligent surrogate models for low-level analog building blocks are needed to bridge behavioral and transistor-level simulations. With this objective, artificial neural network (ANN) metamodels are incorporated in Verilog-AMS to capture the highly nonlinear response of the analog block. Parameterized ANN Verilog-AMS behavioral metamodels are constructed for efficient system-level design exploration. The application of these intelligent metamodels to multi-objective analog block optimization is demonstrated. To the best of the authors' knowledge this is the first paper to integrate artificial neural network models in Verilog-AMS. To demonstrate the application of iVAMS, a biologically-inspired “firefly optimization algorithm” is applied to an OP-AMP design. The optimization process is sped up by 5580× due to the use of iVAMS with negligible loss in accuracy.

An automated top-down design flow to achieve physical design of Analog/Mixed-Signal Systems-on-Chip (AMS-SoCs) is difficult, especially for nano-CMOS. Process variation effects have profound impact on the performance of silicon versus layout design. In this paper metamodels, (surrogate models) and Particle Swarm Optimization (PSO) have been combined in an automated physical design flow for fast design exploration of AMS-SoCs. Neural network based non-polynomial metamodels that handle large numbers of design parameters, are used to predict the statistical process variation effects instead of exhaustive Monte Carlo simulations. The PSO algorithm is used for optimization of the AMS-SoC components using their metamodels instead of the actual circuit. The PSO algorithm followed a two step approach: local and global. The physical design of a Phase Locked Loop (PLL) is considered as a case study circuit. The proposed design flow is approximately 5 times faster while the error is under 2% compared to the Monte Carlo analysis.

Intellectual property (IP) core based embedded systems design is a pervasive practice in the semiconductor industry due to shorter time-to-market and tougher cost competitions. Protecting the design information in these IP cores and securing test from various attacks are two emerging challenges in today's embedded systems design. Recently reported techniques address these challenges considering secure test and IP core protection separately. However, for ensuring high security during IP core functionality and also during test, joint consideration of secure test and IP core protection is much needed. In this paper, we propose a novel and unified design methodology, called STEP (Secure TEst and IP core Protection), which addresses the joint objective of secure test and IP core protection. The aim of STEP design methodology is to achieve high security at low system cost using the same key integrated hardware during test and IP core functionality. We evaluate the effectiveness of STEP design methodology considering advanced encryption standard (AES) system as a case study. We show that proposed design methodology benefits from high security and test accuracy, requiring up to 9% higher area and 20% power overheads.

Current Verilog-AMS system level modeling does not capture the physical design (layout) information of the target design as it is meant to be fast behavioral simulation only. Thus, the results of behavioral simulation can be very inaccurate. In this paper a paradigm shift of the current trend is presented that integrates layout level information (with full parasitics) in Verilog-AMS through polynomial metamodels such that system-level simulation of a mixed-signal circuit/system is realistic and as accurate as the true parasitic netlist simulation. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design exploration. Based on a quadratic polynomial metamodel, the PLL simulation achieves approximately a 10X speedup compared to the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power consumption are 0.7% and 3%, respectively. This behavioral metamodel approach bridges the gap between layout accurate but fast simulation and design space exploration.

No abstract available.

This paper presents research leading to robust nano-CMOS sense amplifier design by incorporating process variation early in the design process. The effects of process variation are analyzed on the performance of a conventional voltage sense amplifier which is used in most DRAMs. A parametric study is performed through circuit simulations to investigate which parameters have the most impact on the performance of the sense amplifier. The Figures of Merit (FoMs) used to characterize the circuit are precharge time, power dissipation, sense delay and sense margin. Statistical analysis is performed to examine the impact of process variations on each FoM. By analyzing the results from the statistical study, a method is presented to select parameter values that minimize the effects of process variation. In this context, the well-established process-level techniques dual-threshold voltage and dual-oxide thickness are, for the first time, investigated for efficient sense amplifier design. Experimental results prove that the proposed approach improves precharge time by 63.3%, sense delay by 53.6%, sense margin by 39.3%, and power dissipation by 23.3% for 45 nm CMOS.

The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume for high density chips. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flip-flops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be placed in parallel is determined by the minimum incompatibility relations among the corresponding bits of a test set, to enhance fault coverage in broadcast mode. As a result, the number of serial test patterns also reduces.

Network-on-Chip (NoC) is an on-chip communication solution in the future system-on-a-chip (SoC) necessitating high performance operation with low power dissipation. We present a novel dynamic power management technique for low power NoC router buffers using nano CMOS SRAMS. A feedback controller was designed for block level power management and a power aware adaptive controller was designed for low power flit storage encoding to reduce energy consumptions in the router buffers. Experiments with the proposed scheme showed up to 20% reduction in energy consumption while improving throughput by up to 21%.

In this paper, a novel design flow is presented for power minimization of nano-CMOS SRAM (static random access memory) circuits, while maintaining their performance. A 32nm high-K/metalgate SRAM is used as an example circuit. The baseline SRAM circuit is subjected to power minimization using a dual-VTh assignment based on a novel Design of Experiments-Integer Linear Programming (DOE-ILP) approach. However, this leads to a 15% reduction in the Static Noise Margin (SNM) of the SRAM, which is an indicator of the stability degradation of the SRAM. This reduction in the SNM is then overcome using a conjugate gradient optimization, while maintaining the minimum power consumption. The final SRAM design shows 86% reduction in power (including leakage) consumption and 8% increase in the SNM compared to the baseline design. The variability analysis of the optimized cell is carried out considering the variability effect in 12 parameters to study the robustness of the optimal SRAM circuit. An 8 x 8 array is constructed to show the feasibility of the proposed SRAM.

Concurrent error detection and correction is an effective way to mitigate fault attacks in cryptographic hardware. Recent work on differential power analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energy consumed by a working digital circuit, it is possible to gain valuable information about the encryption algorithms used and even the specific encryption keys. Thwarting such attacks requires a new approach to logic and physical designs. This paper presents a systematic approach to fault tolerant cryptographic hardware designs. Firstly, the effectiveness of the Hamming code based error correction schemes as a fault tolerance method in stream ciphers is investigated. Coding is applied to Linear Feedback Shift Registers (LFSR) based stream cipher implementations. The method was implemented on industrial standard stream ciphers, e.g. A5/1(GSM), E0 (Bluetooth), RC4 (WEP), and W7. The performance variation of stream cipher algorithms with error detection and correction was studied by synthesising the designs on Field Programmable Logic Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Further, we analyse hardware building blocks to minimise switching activity of a circuit over all possible inputs and input transitions by adding redundant gates and increasing the overall number of signal transitions. We also discuss the overhead and compositional properties of uniformly-switching circuits.

Power dissipation is a major bottleneck for emerging applications, such as implantable systems, digital cameras, and multimedia processors. Each of these applications is essentially designed as an Analog/Mixed-Signal System-on-a-Chip (AMS-SoC). These AMS-SoCs are typically operated from a single power-supply source which is a battery providing a constant supply voltage. In order to reduce power dissipation of the AMS-SoCs, multiple-supply voltage and/or variable-supply voltage is used as an attractive low-power design approach. In the multiple-/variable-supply voltage AMS-SoCs the use of a DC-to-DC voltage-level shifter is critical. The voltage-level shifter is an overhead when its own power dissipation is high. In this article a new DC-to-DC voltage-level shifter is introduced that performs level-up shifting, level-down shifting, and blocking of voltages and is called Universal Level Shifter (ULS). The ULS is a unique component that reduces dynamic power and leakage of the AMS-SoCs while facilitating their reconfigurability. The system-level architectures for three AMS-SoCs, such as Drug Delivery Nano-Electro-Mechanical-System (DDNEMS), Secure Digital Camera (SDC), and Net-centric Multimedia Processor (NMP) are introduced to demonstrate the use the ULS for system-level power management. The article presents a design flow and an algorithm for optimal design of the ULS using a dual-Vthhigh-κ technique for efficient realization of ULS. A prototype ULS is presented for 32nm nano-CMOS technology node. The robustness of the ULS design is examined by performing three types of analysis, such as parametric, load, and power. It is observed that the ULS produces a stable output for voltages as low as 0.35 V and loads varying from 50fFto 120fF. The average power dissipation of the ULS with a 82fFcapacitive load is 5 μW.

This paper presents a six-transistor (6T) single-ended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-VDDand low-power embedded applications. The proposed bitcell has a better static noise margin (SNM) and write-ability compared to a standard 6T bitcell and equivalent to an 8T bitcell [1]. An 8Kbit SRAM module with the proposed and standard 6T bitcells is simulated, including full blown parasitics using BPTM, 65 nm CMOS technology node to evaluate and compare different performance parameters. The active power dissipation in the proposed 6T design is 28% and 25% less, compared to standard 6T and 8T SRAM modules respectively.

In this paper, we present the design of a P4 (Power-Performance-Process-Parasitic) aware voltage controlled oscillator (VCO) at nano-CMOS technologies. Through simulations, we have shown that parasitics and process have a drastic effect on the performance (center frequency) of the VCO. For process variation analysis, we propose a methodology called Design of Experiments-Monte Carlo (DOE-MC), which offers up to 6.25x time savings over a traditional Monte Carlo (TMC) method. A performance optimization of the VCO along with dual-oxide power minimization technique has been carried out in the presence of worst case process. The end product of the proposed methodology is a process aware, performance optimized, dual oxide VCO physical design. We have achieved 25% power (including leakage) minimization with only 1% degradation in center frequency compared to target frequency, in the presence of worst-case process and parasitics. The dual-oxide physical design of the VCO is carried out at 90nm. To the best of the authors' knowledge, this is the first research reporting a dual-oxide nano-CMOS VCO design simultaneously optimized for power (including leakage), performance, parasitics and process.

This paper proposes a novel flow for parasitic and process-variation aware design of radio-frequency integrated circuits (RFICs). A nano-CMOS current-starved voltage controlled oscillator (VCO) circuit has been designed using this flow as a case study. The oscillation frequency is considered as the objective optimization function with the area overhead as constraint. Extensive Monte Carlo simulations have been carried out on the parasitic extracted netlist of the VCO to study the effect of process variation on the oscillation frequency. In the design cycle, a performance degradation of 43.5% is observed when the parasitic extracted netlist is subjected to worst-case process variation. The proposed design flow could bring the oscillation frequency within 4.5% of the target, leading to convergence of the complete design in only one design iteration. To the best of the authors' knowledge, this paper presents the first work focussed on a current starved VCO in which the combined effect of parasitics and process variations has been considered.

Battery lifetime and safety are primary concerns in the design of battery operated systems. Lifetime management is typically supervised by the system via battery-aware task scheduling, while safety is managed on the battery side via features deployed into smart batteries. This research proposes IntellBatt; an intelligent battery cell array based novel design of a multi-cell battery that offloads battery lifetime management onto the battery. By deploying a battery cell array management unit, IntellBatt exploits various battery related characteristics such as charge recovery effect, to enhance battery lifetime and ensure safe operation. This is achieved by using real-time cell status information to selects cells to deliver the required load current, without the involvement of a complex task scheduler on the host system. The proposed design was evaluated via simulation using accurate cell models and real experimental traces from a portable DVD player. The use of a multi-cell design enhanced battery lifetime by 22% in terms of battery discharge time. Besides a standalone deployment, IntellBatt can also be combined with existing battery-aware task scheduling approaches to further enhance battery lifetime.

This paper presents a process variation tolerant, SoC ready, 1 GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologies. The physical design is carried out with a generic 90 nm Salicide 1.2 V/2.5 V 1 Poly 9 Metal process design kit using Design for Manufacturability (DFM) methodologies. Post-layout simulation results at nominal supply and threshold voltages are presented. The parasitic-extracted physical design of the ADC has been simulated for a supply voltage variation of 10%, and threshold voltage mismatch of 5%. The results show maximum variations of 10.5% and 5.7% in the INL and DNL respectively, with nominal INL = 0.344 LSB and nominal DNL = 0.459 LSB, at a supply voltage of 1.2 V. The ADC consumes a peak power of 5.794 mW and an average power of 3.875 mW. The comparators used in the ADC have been designed using the threshold inverting technique.

In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is proposed which is highly stable against nanoscale process variations as well as power efficient. The effectiveness of the proposed cell is exhaustively evaluated through detailed Monte Carlo simulations. It is observed that the 16% variation in threshold voltage results in negligible effects on static noise margin (SNM) during read operation. Experiments under different loading conditions indicate that there is reduction 2X (approximately) in power dissipation and 2X (approximately) in leakage.

This article presents a novel invisible robust watermarking scheme for embedding and extracting a digital watermark in an image. The novelty lies in determining a perceptually important subimage in the host image. Invisible insertion of the watermark is performed in the most significant region of the host image such that tampering of that portion with an intention to remove or destroy will degrade the esthetic quality and value of the image. One feature of the algorithm is that this subimage is used as a region of interest for the watermarking process and eliminates the chance of watermark removal. Another feature of the algorithm is the creation of a compound watermark using the input user watermark (logo) and attributes of the host image. This facilitates the homogeneous fusion of a watermark with the cover image, preserves the quality of the host image, and allows robust insertion-extraction. Watermark creation consists of two distinct phases. During the first phase, a statistical image is synthesized from a perceptually important subimage of the image. A compound watermark is created by embedding a watermark (logo) into the statistical synthetic image by using a visible watermarking technique. This compound watermark is invisibly embedded into the important block of the host image. The authentication process involves extraction of the perceptive logo as well statistical testing for two-layer evidence. Results of the experimentation using standard benchmarks demonstrates the robustness and efficacy of the proposed watermarking approach. Ownership proof could be established under various hostile attacks.

For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorithm for the gate leakage current reduction by simultaneous scheduling, allocation and binding during behavioral synthesis. Gate leakage current reduction is based on the use of functional units of different oxide thickness while simultaneously accounting for process variations. We present a cost function that minimizes leakage and area overhead. The algorithm minimizes the cost function for a given delay trade-off factor. It uses a pre-characterized cell library for tunneling current, delay and area, expressed as analytical functions of the gate oxide thickness T/sub ox/. We tested our approach using a number of behavioral level benchmark circuits characterized for a 45nm library by integrating our algorithm into a high-level synthesis system. We obtained an average gate leakage reduction of 76.88% with an average area overhead of 17.38% for different delay trade-off factors ranging from 1.0 to 1.4.

We introduce a new congestion driven placement algorithm for FPGAs in which the overlapping effect of bounding boxes is taken into consideration. Experimental results show that compared with the linear congestion method (Betz et al., 1999) used in the state-of-the-art FPGA place and route package VPR (Betz and Rose, 1997), our algorithm achieves channel width reduction on 70% of the 20 largest MCNC benchmark circuits (10.1% on average) while keeping the channel width of the remaining 30% benchmarks unchanged. A distinct feature of our algorithm is that the critical path delay is not elongated on average, and in most cases reduced

Gate leakage (direct tunneling current for sub-65 nm CMOS) can severely affect both the transient and steady state behaviors of CMOS circuits. In this paper we quantify the transient and steady-state gate leakage effects as capacitances and state independent (equiprobable) average values, respectively. These metrics are characterized for two universal logic gates, 2-input NAND and NOR, and their sensitivity to variations in process and design parameters is studied. The effective tunneling capacitance of a logic gate is defined as the maximum change in tunneling current with respect to the rate of change of input voltage. It is an unique and novel metric and to our knowledge proposed here for the first time with respect to a logic gate. This metric concisely encapsulates both qualitative as well as quantitative information about the swing in tunneling current during state transitions while simultaneously accounting for the transition rate and represents the capacitive load of the logic gate due to transience in tunneling.

In this paper, we propose a new metric called "effective tunneling capacitance" (Cefft) to quantify the transient swing in the gate leakage (gate oxide tunneling) current due to state transitions. Cefftwhich is defined as the change in tunneling current with respect to the rate of change of input voltage is a unique metric and to our knowledge proposed here for the first time. This metric concisely encapsulates information about the swing in tunneling current during state transitions while simultaneously accounting for the transition rate and represents the capacitive load of the transistor due to tunneling. This capacitance can have impact on transistor characteristics being additive to its gate oxide and diffusion capacitances. We express Cefftas functions of gate oxide thickness Toxand on-chip power supply VDDto make it useful for modeling in higher levels of design abstraction. We also statistically analyze the effects of process variations of Toxand VDDon its distribution

With aggressive technology scaling, gate oxide tunneling current is emerging as a prominent component of power dissipation in nanoCMOS circuits. This paper presents a novel approach for reduction of tunneling current (gate leakage) during behavioral synthesis using simultaneous scheduling and binding of resources made of transistors of different gate oxide thicknesses. We provide a heuristic algorithm for optimizing allocation and utilization of resources while scheduling operations with the objective of reducing gate leakage. We selectively bind the off-critical operations to instances of functional units that have transistors of higher oxide thickness, and critical operations to the functional units of lower oxide thickness. We performed extensive experiments for several behavioral synthesis benchmarks using a 45nm technology library. For a time constrained approach we achieved a maximum reduction of 84.8%, while for a resource-time constrained approach the reduction is 75.8%

In this paper we present a robust and novel strategic invisible approach for insertion-extraction of a digital watermark, a color image, into color images. The novelty of our scheme lies in determining a perceptually important sub-image in the host image so that slight tampering of the sub-image will affect the aesthetic of the host image significantly. This eliminates the possibility of watermark removal, which in turn makes the watermark secure and robust. The other novel feature of our algorithm is the creation of a compound watermark image, called effective watermark, using the input user watermark (logo) and attributes of host image, which facilitates robust insertion-extraction processes. The effective watermark creation consists of two distinct phases: in the first phase, a statistical image is synthesized from a perceptually important sub-image of the host image and in the second phase, a compound image is created by fusing the input logo and synthetic statistical image. Results of exhaustive experimentation using standard benchmarks demonstrates the robustness and efficacy of our approach

In low-power design for battery-driven portable applications, the reduction of peak power, peak power differential, cycle difference power, average power and energy are equally important. These are different forms of dynamic power dissipation of a CMOS circuit, which is predominant compared to static power dissipation for higher switching activity. The peak power, the cycle difference power, and the peak power differential drive the transient characteristic of a CMOS circuit. In this article, we propose an ILP-based framework for the reduction of energy and transient power through datapath scheduling during behavioral synthesis. A new metric called “modified cycle power function” (CPF*) is defined that captures the above power characteristics and facilitates integer linear programming formulations. The ILP-based datapath scheduling schemes with CPF* as objective function are developed assuming three modes of datapath operation, such as, single supply voltage and single frequency (SVSF), multiple supply voltages and dynamic frequency clocking (MVDFC), and multiple supply voltages and multicycling (MVMC). We conducted experiments on selected high-level synthesis benchmark circuits for various resource constraints and estimated power, energy and energy delay product for each of them. Experimental results show that significant reductions in power, energy and energy delay product can be obtained.

With continued and aggressive scaling, using ultra-low thickness SiO/sub 2/ for the transistor gates, tunneling current has emerged as the major component of leakage in CMOS circuits. In this paper, we propose a new approach called dual dielectrics of dual thicknesses (DKDT) for the reduction of both ON and OFF state gate tunneling currents. We claim that the simultaneous utilization of SiON and SiO/sub 2/ each with multiple thicknesses is a better approach for gate leakage reduction than the conventional one that uses a single gate dielectric, SiO/sub 2/, of multiple thicknesses. We develop an algorithm for the corresponding assignment of dual dielectric and dual thickness cells that minimizes the overall tunneling current for a circuit without compromising its performance. We performed extensive experiments on ISCAS'85 benchmarks using 45 nm technology which demonstrate that our approach can reduce the tunneling current by as much as 98.7% (on average 94.8%), without performance degradation.

Recently, dynamic frequency scaling has been explored at the CPU and system levels for power optimization. Low-power datapath scheduling using multiple supply voltages has been well researched. In this work, we develop new datapath scheduling algorithms that use multiple supply voltages and dynamic frequency clocking in a coordinated manner in order to reduce the energy consumption of datapath circuits. In dynamic frequency clocking, the functional units can be operated at different frequencies depending on the computations occurring within the datapath during a given clock cycle. The strategy is to schedule high-energy units, such as multipliers at lower frequencies, so that they can be operated at lower voltages to reduce energy consumption and the low-energy units, such as adders at higher frequencies, to compensate for speed. The proposed time- and resource-constrained algorithms have been applied to various high-level synthesis benchmark circuits under different time and resource constraints. The experimental results show significant reduction in energy for both the algorithms.

Watermarking is the process that embeds data called a watermark, a tag, or a label into a multimedia object, such as images, video, or text, for their copyright protection. According to human perception, the digital watermarks can be divided into four categories.. A watermark is a secondary translucent image overlaid into the primary image and appears to a viewer on a careful inspection. The in watermark is embedded in such a way that the modifications made to the pixel value is perceptually not noticed, and it can be recovered only with an appropriate decoding mechanism. This paper presents a new very large scale integration (VLSI) architecture for implementing two digital image watermarking schemes. The proposed architecture is designed to aim at easy integration into any existing digital camera framework. To the authors' knowledge, this is the first VLSI architecture for implementing watermarking schemes. A prototype chip consisting of 28 469 gates is implemented using 0.35-/spl mu/ technology, which consumes 6.9-mW power while operating at 292 MHz.

Watermarking is the process that embeds data called a watermark, a tag, or a label into a multimedia object, such as images, video, or text, for their copyright protection. According to human perception, the digital watermarks can either be visible or invisible. A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a viewer on a careful inspection. The invisible watermark is embedded in such a way that the modifications made to the pixel value is perceptually not noticed, and it can be recovered only with an appropriate decoding mechanism. This paper presents a new very large scale integration (VLSI) architecture for implementing two visible digital image watermarking schemes. The proposed architecture is designed to aim at easy integration into any existing digital camera framework. To the authors' knowledge, this is the first VLSI architecture for implementing visible watermarking schemes. A prototype chip consisting of 28 469 gates is implemented using 0.35-/spl mu/m technology, which consumes 6.9-mW power while operating at 292 MHz.

In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability and efficiency. The peak power and the peak power differential drive the transient characteristics of a CMOS circuit. In this paper, we propose a framework for the simultaneous reduction of energy and transient power during behavioral synthesis. A new metric called "cycle power function" (CPF) is defined which captures the transient power characteristics as an equally weighted sum of the normalized mean cycle power and the normalized mean cycle differential power. Minimizing CPF using multiple supply voltages and dynamic frequency clocking under resource constraints results in the reduction of both energy and transient power. Based on the above, we develop a new datapath scheduling algorithm called CPF-scheduler which attempts at power and energy minimization by minimizing the CPF parameter during the scheduling process. The type and number of functional units available become the set of resource constraints for the scheduler. Experimental results indicate that the proposed scheduler achieves significant reductions in terms of power and energy.

The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using deep submicron and nanometer technology, the peak power, peak power differential, average power and total energy are equally critical design constraints. In this work, we propose datapath scheduling algorithms for simultaneous minimization of peak and average power while maintaining performance by use of dynamic frequency clocking and multiple supply voltages. The algorithms use integer linear programming based models. The dynamic frequency clocking methodology is more useful for data intensive signal processing applications. The effectiveness of our scheduling technique is measured by estimating the peak power consumption, the average power consumption and the power delay product of the datapath circuit. Furthermore, the proposed scheduling scheme is compared with combined multiple supply voltages and multicycling scheme. Experimental results show that combined multiple supply voltages (3.3V,2.4V) and dynamic frequency clocking scheme achieves significant reductions in peak power (72% on the average), average power (71% on the average) and power delay product (54% on the average).

We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapath design: single supply voltage and single frequency (SVSF), multiple supply voltages and dynamic frequency clocking (MVDFC), and multiple supply voltages and multicycling (MVMC). Various experiments are conducted on selected high-level synthesis benchmarks. Experimental results in terms of several parameters, such as mean power gradient, mean cycle power, peak power, and power delay product, are presented.

Digital watermarking is the technique in which a visible/invisible signal (watermark) is embedded in a multimedia document for copyright protection. In this paper, we propose a watermarking scheme called "dual watermarking". Dual watermark is a combination of a visible watermark and an invisible watermark.