Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Robert R. Roediger

dblp:99/4639 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 83% Performance modeling and evaluation · 17%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache
0.011995
SPAID: software prefetching in pointer- and call-intensive environments · MICRO 1995
Memory systems › memory access optimization
pointer-chasing prefetching
0.011995
SPAID: software prefetching in pointer- and call-intensive environments · MICRO 1995
Memory systems
software prefetching
0.011995
SPAID: software prefetching in pointer- and call-intensive environments · MICRO 1995
Performance modeling and evaluation
simulation
0.011995
SPAID: software prefetching in pointer- and call-intensive environments · MICRO 1995
Performance modeling and evaluation › simulation › cache simulation
trace-driven cache simulation
0.011995
SPAID: software prefetching in pointer- and call-intensive environments · MICRO 1995

Methods — techniques the papers use, named apart from their topics

trace-driven cache simulation · 0.0
YearPublicationVenuePosition
1995 SPAID: software prefetching in pointer- and call-intensive environments
abstract
Software prefetching, typically in the context of numeric- or loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems by the cost of servicing cache misses. This paper proposes a new heuristic-SPAID-for utilizing prefetch instructions in pointer- and call-intensive environments. We use trace-driven cache simulation of a number of pointer- and call-intensive benchmarks to evaluate the benefits and implementation trade-offs of SPAID. Our results indicate that a significant proportion of the cost of data cache misses can be eliminated or reduced with SPAID without unduly increasing memory traffic.
Mikko H. Lipasti, William J. Schmidt, Steven R. Kunkel, Robert R. Roediger
MICRO4