Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from EDBT 2026 / reviewers in the wild / expert

Hongming Chen 0002

dblp:99/4827-2 · DBLP profile ↗
← Back
3ranked-venue papers
3as first author
0since 2021 · last 2014
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2 · 2 first-authorSystems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 94% Memory systems · 6%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
delay-locked loop		 0.212014
A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller · Sci. China Inf. Sci. 2014
Integrated circuit design
digital circuit design		 0.212014
A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology · Sci. China Inf. Sci. 2014
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design		 0.212014
A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller · Sci. China Inf. Sci. 2014
Integrated circuit design › memory circuit design
SRAM design		 0.212014
A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology · Sci. China Inf. Sci. 2014
Memory systems
DRAM		 0.112014
A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller · Sci. China Inf. Sci. 2014
Integrated circuit design
low-power circuit design		 0.112014
A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology · Sci. China Inf. Sci. 2014

Methods — techniques the papers use, named apart from their topics

low-power design · 0.2all-digital DLL · 0.2
YearPublicationVenuePosition
2014 A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology
Hongming Chen 0002
 Sci. China Inf. Sci.1
2014 A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller
Hongming Chen 0002, Kenyi Pan
 Sci. China Inf. Sci.1
2012 VLSI implementation of color interpolation in color difference spaces
abstract
This paper presents a color interpolation processor for color-filter-array (CFA) based image sensor. We propose a modified color difference spaces interpolation method by using direction determination. Simulations show that the proposed method can achieve better quality-complexity tradeoff than other algorithms. For real-time VLSI implementation, a cost-effective architecture consisting of pipeline is designed based on our algorithm. The prototype of the color interpolation processor has been successfully verified on FPGA device. This design only uses about 25K gates and six line buffers on 0.18um process.
Hongming Chen 0002
 ISCAS1