We evaluate HARVEST (Hardware Accelerated Runtime Verification for Embedded SofTware), a runtime error detection mechanism for embedded software running on standard SoPC architectures,i.e., one (or more) processor(s) and an FPGA on a single chip. The program under monitoring runs on the processor(s), while a trace analysis module running on the FPGA detects errors in its execution. The hardware implementation of trace analysis minimizes the performanceimpact and achieves a very low error reporting latency (a few processor cycles). In this article, we evaluate the suitability of using HARVEST to detect errors resulting from transient physical faults. We explain how HARVEST is used to monitor a complex software component (Trampoline RTOS) on a commercially available hardware platform (Microchip SmartFusion2). We measure the overhead of the resulting instrumentation on system resources. We then evaluate its performance in detecting silent data corruptions, based on a systematic simulation of bit flips at the instruction set architecture level. We report a detection rate of up to 90.2% for a fairly low system resource overhead, suggesting an interesting trade-off for designers of highly constrained critical systems.

Numerous attacks compromising processor security have been developed over decades, including some targeting the microarchitecture, such as side-channel or transient attacks, or control-flow hijacking attacks. As these attacks target processor microarchitectural features and bypass software-level mitigation techniques, they are considered a serious threat. In order to mitigate these attacks while limiting the impact on performance, various detection methods have been proposed. Indeed, detection techniques offer solutions to limit the execution of costly countermeasures, only after attacks detection, limiting the induced performance overhead. However, detection techniques in the literature suffer from several drawbacks, including non-real-time detection, significant increase in execution time, or make the hypothesis of a trusted Operating System (OS). In this work, we introduce DynHaMo that addresses these issues by detecting attacks targeting the microarchitecture, such as Cache-based Side-Channel Attacks (CSCAs) and Return-Oriented Programming (ROP) attacks, at run-time by taking advantage of dynamic instruction insertion at the hardware level. DynHaMo, is a light-weight hardware micro-decoding unit capable of monitoring microarchitectural events on the fly. For evaluation purposes, DynHaMo has been integrated into a RISC-V core, assessed through multiple benchmarks and attack codes, and implemented on an FPGA platform. We evaluated our solution under high workloads to demonstrate the efficiency of the approach and its robustness to noise. The evaluation results show a detection accuracy of 99.3% on average, with 0.7% false negative and 1.2% false positive on average.

Dynamically reconfigurable architectures allow sharing of hardware resources, which is particularly beneficial for small low-end FPGAs. Based on the online modification of parts of the circuit, these architectures require partial reconfiguration of the chip. Reducing resource availability or usage comes at the cost of a performance penalty affecting execution time. The challenge lies in bitstream management, especially for complex applications that often exceed the internal memory capacity of the FPGA (BRAM). Consequently, the time penalty arises from the need to retrieve partial bitstreams from external memory (e.g., often a DDR) each time it is necessary. Current state-of-the-art reconfiguration controllers are limited to a throughput of 400 MB/s, significantly penalizing reconfiguration times and making dynamic reconfiguration unattractive for real-life applications (e.g., video processing, machine learning applications, and continual and federated learning for embedded systems). This article introduces a novel partial reconfiguration controller architecture that achieves a throughput of up to 1.396 GB/s, a 3.49× acceleration over existing controllers. The reduced reconfiguration time allows the practical use of dynamic reconfiguration with fewer performance penalties. Additionally, the article compares various reconfiguration controllers in terms of time penalties and offers a tradeoff between algorithm complexity, FPGA resources, and performance.

The SecureV (also known as SecV) project offers an innovative, open-source hardware, secure, and high-performance processor core based on the RISC-V ISA. The originality of the approach lies in the integration of a complete solution to increase security based on dynamic code transformation, covering 4 of the 5 NIST11National Institute of Standards and Technology functions of cybersecurity via monitoring (identify, detect), obfuscation (protect), and dynamic adaptation (react).

Fast yet accurate performance and timing prediction of complex parallel data flow applications on multi-processor systems remains a difficult discipline. The reason for it comes from the complexity of the data flow applications and the hardware platform with shared resources, like buses and memories. This combination may lead to complex timing interferences that are difficult to express in pure analytical or classical simulation-based approaches. In this work, we propose a message-level communication model for timing and performance prediction of Synchronous Data Flow (SDF) applications on MPSoCs with shared memories. We compare our work against measurement and TLM simulation-based performance prediction models on two case-studies from the computer vision domain. We show that the accuracy and execution time of our simulation outperforms existing approaches and is suitable for a fast yet accurate design space exploration.

Timing prediction of complex parallel data flow applications on multiprocessor systems represents a difficult task due to complex interferences caused by platforms shared resources. In this domain, classical analytical or simulation-based approaches demonstrate scalability issues to deliver fast yet accurate predictions. In this work, we present an experimental evaluation of new simulation-based statistical methods for timing analysis of multiprocessor systems. We adopt a measurement-based approach for the creation of probabilistic system-level models of the studied systems. Efficiency of statistical methods is evaluated for platforms with different levels of complexity from the point of view of shared resources. We compare our approach against measurement and traditional simulation methods on two case-studies from the computer vision domain: a Sobel filter and a JPEG decoder. We show that our simulation approach has good potential for fast yet accurate design space exploration.

Architectures are becoming more and more complex to keep up with the increase of algorithmic complexity. To fully exploit those architectures, dynamic resources managers are required. The goal of dynamic managers is either to optimize the resource usage (e.g. cores, memory) or to reduce energy consumption under performance constraints. However, performance optimization being their main goal, they have not been designed to be secure and present vulnerabilities. Recently, it has been proven that energy managers can be exploited to cause faults within a processor allowing to steal information from a user device. However, this exploitation is not often possible in current commercial devices. In this work, we show current security vulnerabilities through another type of malicious usage of energy management, experimentation shows that it is possible to remotely lock out a device, denying access to all services and data, requiring for example the user to pay a ransom to unlock it. The main target of this exploit are embedded systems and we demonstrate this work by its implementation on two different commercial ARM-based devices.

The paper addresses the formal verification of gate-level square-root circuits. Division and square root functions are some of the most complex arithmetic operations to implement and proving the correctness of their hardware implementation is of great importance. In contrast to standard approaches that use satisfiability and equivalence checking techniques, the presented method verifies whether the gate-level square-root circuit actually performs a root operation, instead of checking equivalence with a reference design. The method extends the algebraic rewriting technique developed earlier for multipliers and introduces a novel technique of implicit hardware rewriting. The tool called SPEAR based on hardware rewriting enables the verification of a 256-bit gate-level square-root circuit with 0.26 million gates in under 18 minutes.

Division is one of the most complex arithmetic operations to implement and its hardware implementation requires thorough verification at the gate level. Dividers are difficult to verify using standard Boolean methods, such as equivalence checking or SAT-based techniques, as they require “bit-blasting” onto bit-level netlists. Other methods, such as theorem provers, concentrate mostly on proving correctness of the division algorithm. However, verification of low-level hardware implementations has received only a limited attention. This paper addresses the problem of verifying gate-level divider circuits by extending an algebraic model, successfully used to prove multipliers and other arithmetic circuits, to dividers. The method verifies whether the gate-level divider circuit actually performs a division, without a need for a reference design.

As FPGA use becomes more diverse, the shared use of these devices becomes a security concern. Multi-tenant FPGAs that contain circuits from multiple independent sources or users will soon be prevalent in cloud and embedded computing environments. The recent discovery of a new attack vector using neighboring long wires in Xilinx SRAM FPGAs presents the possibility of covert information leakage from an unsuspecting user's circuit. The work described in this paper makes two contributions that dramatically extend this finding. First, we rigorously evaluate several Intel SRAM FPGAs and confirm that long wire information leakage is also prevalent in these devices. Second, we present the first successful attack on an unsuspecting circuit in an FPGA using information passively obtained from neighboring long-lines. Information obtained from a single AES S-box input wire combined with analysis of encrypted output is used to rapidly expose an AES key. This attack is performed remotely without modifying the victim circuit, using electromagnetic probes or power measurements, or modifying the FPGA in any way. We show that our approach is effective for three different FPGA devices. Our results demonstrate that the attack can recover encryption keys from AES circuits running at 10MHz, and has the capability to scale to much higher frequencies.

Field Programmable Gate Arrays (FPGAs) used in mission-critical applications such as aerospace, nuclear, and defense require high reliability in spite of internal faults. Fortunately, today's FPGAs have the ability to dynamically reconfigure themselves in the field, which may help to mitigate the effects of certain faults affecting the FPGA devices. Although the reconfiguration process can remove only the upsets affecting the configuration bitstream, unfortunately, there are other sources of faults that might directly affect hardware resources of reconfigurable FPGAs. Their nature and consequences differ from those which occur in the configuration bitstream and their effects cannot be corrected by performing configuration writeback. This paper proposes a fault-aware configurable logic block architecture to detect such faults in FPGA-implemented logic circuits. The fault coverage of the proposed architecture is also discussed. Hardware complexity estimations suggest higher efficiency of the approach proposed over similar existing ones.

The deployment of an application onto a multicore archi- tecture is often a long and difficult process. This is due to the fact that the characteristics of both the architecture and the application are taken into account late in the development process. It's therefore necessary to have tools pruning the solution space efficiently and accurately. In order to define such a tool, this work defines the basic metrics and step for a design space exploration ("DSE") flow. To this end our proposal have been tested and validated for a space application that requires both a high computing power and an architecture compatible with the space constraints. The results obtained are promising and have shown the viability of the approach.

In this paper, we propose a new approach to implement a reliable softcore processor on SRAM-based FPGAs, which can mitigate radiation-induced temporary faults (single-event upsets (SEUs)) at moderate cost. A new Enhanced Lockstep scheme built using a pair of MicroBlaze cores is proposed and implemented on Xilinx Virtex-5 FPGA. Unlike the basic lockstep scheme, ours allows to detect and eliminate its internal temporary configuration upsets without interrupting normal functioning. Faults are detected and eliminated using a Configuration Engine built on the basis of the PicoBlaze core which, to avoid a single point of failure, is implemented as fault-tolerant using triple modular redundancy (TMR). A softcore processor can recover from configuration upsets through partial reconfiguration combined with roll-forward recovery. SEUs affecting logic which are significantly less likely than those affecting configuration are handled by checkpointing and rollback. Finally, to handle permanent faults, the tiling technique is also proposed. The new Enhanced Lockstep scheme requires significantly shorter error recovery time compared to conventional lockstep scheme and uses significantly smaller number of slices compared to known TMR-based design (although at the cost of longer error recovery time). The efficiency of the proposed approach was validated through fault injection experiments.

Dynamically reconfigurable architectures, which can offer high performance, are increasingly used in different domains. High-speed reconfiguration process can be carried out by operating at high frequency but can also augment the power consumption. Thus the effort on increasing performance by accelerating the reconfiguration should take into account power consumption constraints. In this paper, we present an ultra-fast power-aware reconfiguration controller (UPaRC) to boost the reconfiguration throughput up to 1.433 GB/s. UPaRC can not only enhance the system performance, but also auto-adapt to various performance and consumption conditions. This could enlarge the range of applications and optimize for each selected application during run-time. An investigation of reconfiguration bandwidths at different frequencies and with different bitstream sizes are experimentally quantified and presented. The power consumption measurements are also realized to emphasize energy-efficiency of UPaRC over state-of-the-art reconfiguration controllers-up to 45 times more efficient.

This paper presents the implementation of the error recovery scheme from temporary faults, applicable for datapaths of coarse-grained reconfigurable architectures. We have chosen the DART architecture as a vehicle to study various aspects related to implementation of the instruction retry in a complex highly parallel reconfigurable system. Synthesis results have confirmed the time, hardware, and power consumption efficiency of the proposed approach, which can be applied independently on the concurrent error detection scheme actually used.

The recent developments in the partial and dynamic Reconfigurable Computing (RC) domain demand better ways to manage the simultaneous task execution. In this context, Operating System (OS) services like scheduling, placement, inter-task communication have been developed to make this type of platform more flexible. In order to provide efficient communication scheme between these hardware tasks, a high performance communication infrastructure must be developed and efficient communication services must be proposed. The contribution presented in this paper mainly focuses on the hardware communication service and the communication schemes supported by this new OS service. Performance and implementation cost of our hardware communication service are evaluated and comparisons with the state of the art are given. Compared to related work OS4RS, our proposal is 60× faster to establish communication between hardware tasks.

One trend dealing with the growing computational power needs is to implement multi-processor system-on-a-chip (MPSoC) using Commercial Off-The-Shelf (COTS) partially reconfigurable architectures. However the low Non-Recurring Engineering (NRE) cost solution provided by commercial FPGAs must take into account the high sensitivity to electronic defects. Fault-tolerance schemes, which prevent their architectures from being defective during products life-time, can decrease the system computing power. Therefore, building such fault-tolerant system needs an analytical model to analyze the effect of fault mitigation schemes on the system performance. This paper presents an analytical approach for a fault-tolerant dynamic multi-processor system-on-a-chip (FT-DyMPSoC) which is able to resist to predominant fault in FPGAs - Single Event Upset. The analytical model is introduced to assess the performance, the reliability and the trade-off of a fault-tolerant MPSoC system. Several comparisons with classical fault-tolerance solutions to enhance our solution advantages are also given.

Constant evolution of norms and applications, usually implemented on system-on-chip (SOC), increases architecture performance and flexibility requirements. Current architectures are consequently becoming more complex and difficult to develop. One of the solutions is to develop design frameworks based on high-level architecture description languages (ADL). These ADLs are useful for a rapid description of the hardware that should be implemented on an architecture. Designers can use ADL for the development of generic frontend tools. Our framework aims at designing dynamically reconfigurable architecture with the help of an ADL. This paper presents xMAML, an architecture description language dedicated to the instantiation of dynamically reconfigurable heterogeneous computing units. From this ADL, a synthesizable model is produced after exploration, simulation and validation phases. As proof of concept, exploration for a WCDMA receiver on two dynamically reconfigurable architectures is presented.

With increasing embedded application complexity, designers have proposed to introduce new hardware architectures based on heterogeneous processing units on a single chip. For these architectures, the scheduling service of a realtime operating system must be able to assign tasks on different execution resources. This paper presents a model of artificial neural networks used for real-time task scheduling to heterogeneous system-on-chip architectures. Our proposition is an adaptation of the Hopfield model and the main objective concerns the minimization of the neuron number to facilitate future hardware implementation of this service. In fact, to ensure rapid convergence and low complexity, this number must be dramatically reduced. So, we propose new constructing rules to design smaller neural network and we show, through simulations, that network stabilization is obtained without reinitialisation of the network.

We introduce a new ternary link including a binary-to-ternary encoder and a ternary-to-binary decoder in voltage-mode multiple-valued logic (MVL). This link improves the transistor count compared to existing designs and it has no DC current path. The complete link was simulated with SPICE and a 0.13mum CMOS technology. It additionally shows interesting advantages on power consumption for global interconnects compared to full-swing signaling binary systems (up to 56.4% less energy consumption). Its low propagation delay is also an advantage in the design of high-speed on-chip links for asynchronous systems

In addition to the high performance requirements inherent to multimedia processings or to W -CDMA, future generation mobile telecommunications bring new constraints to the semiconductor design world. In fact, the traditional solutions based on the use of hardware devices (ASIC) or software ones (DSP) are unable to associate the flexibility and the high level of performance to the low energy consumption required by this application domain. In this paper, we study the efficiency of an architecture based on the use of the functional reconfiguration for such systems. Thanks to the implementation of key applications of UMTS, we will show that reconfigurable architectures can offer new compromises to associate high performances and low energy consumption in a flexible architecture and so, can be the solution to the set of problems associated with the future generation mobiles telecommunications systems.