Carlos Sánchez-López

dblp:99/660 · DBLP profile ↗
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6ranked-venue papers
4as first author
3since 2021 · last 2025
0000-0002-3214-5832ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 4 first-author · 3 since 2021
YearPublicationVenuePosition
2025 Comparison of integer-order chaotic attractors as randomness source in collision-free robotic exploration methods
Carlos Sánchez-López, María del Rocío Ochoa Montiel, E. Reyes-Pérez, Carlos Muñiz-Montero
Integr.1
2024 Collision-free arbitrary-order chaotic path generator for differential robots
Carlos Sánchez-López
Integr.1
2023 Artificial synapse topologies using arbitrary-order memristors
Carlos Alejandro Velázquez-Morales, Carlos Sánchez-López, Carlos Hernández-Mejía, Luis Abraham Sánchez-Gaspariano
Integr.2
2019 Optimization and CMOS design of chaotic oscillators robust to PVT variations: INVITED
Victor Hugo Carbajal-Gomez, Esteban Tlelo-Cuautle, Jesús M. Muñoz-Pacheco, Luis Gerardo de la Fraga, Carlos Sánchez-López, Francisco V. Fernández 0001
Integr.5
2011 On the trade-off between the number of scrolls and the operating frequency of the chaotic attractors
abstract
A trade-off analysis on the number of scrolls and the operating frequency is presented. To do so, nonlinear system parameters, real physical active device parameters and the operating frequency are taken into account to model the behavior of the saturated nonlinear function series approximated by a piecewise-linear description. As a consequence, not only the trade-off between the number of scrolls and the operating frequency is investigated, which depends directly on the behavior at the operating frequency of the nonlinear function, but also chaotic attractors are efficiently synthesized without the application of scaling techniques. Theoretical calculations are in good agreement with numerical simulations and a prediction on the maximum number of scrolls that can be synthesized for a particular frequency is also given.
Carlos Sánchez-López, Jesús M. Muñoz-Pacheco, Esteban Tlelo-Cuautle, Victor Hugo Carbajal-Gomez, Rodolfo Trejo-Guerra
ISCAS1
2009 Symbolic Behavioral Model Generation of Current-mode Analog Circuits
abstract
A novel extended method to approximate the behavioral model of current-mode analog circuits (CMACs) is presented. The nullor is employed to model the behavior of a MOS transistor (MOST) together with its parasitic elements. In a first part, the signal-path (SP) into a CMAC is approached by using the nullor properties. In the second part, the behavioral model associated to each MOST is generated and it is more simple in comparison with the original model. As a consequence, in the third part, an admittance matrix of reduced size is built and used to compute small-signal characteristics of CMACs, where the order is given by the number of SP-nodes minus the number of nullors. The proposed technique is illustrated by computing the fully-symbolic transfer function of a positive second generation current conveyor (CCII+) and compared with Hspice simulation.
Carlos Sánchez-López, Esteban Tlelo-Cuautle
ISCAS1