There is considerable interest in the provision of guaranteed-rate services for IP and ATM networks. Simultaneously, bandwidth demands make input-buffered architectures attractive, and in some cases, necessary. We consider the problem of how to support guaranteed-rate services in a single-stage, input-buffered switch suitable for a LAN switch, an ATM switch or an IP router. Such a switch must be feasible at high transmission speeds, offering both guaranteed-rate performance for CBR channels (e.g. for real-time connections) and best-effort services for traditional data traffic. We consider a switch scheduling mechanism that employs idling hierarchical round-robin (HRR) scheduling and fabric arbitration at the connection-level for guaranteed-rate service using the Slepian-Duguid algorithm. The switch uses cell level arbitration for best-effort service. This overall switch scheduling mechanism is a variation of DEC's AN2 design.

The paper is concerned with the design of a class of bandwidth scheduling policies that are suitable for public, wide-area asynchronous transfer mode (ATM) networks. The authors specify design goals for such strategies including ease of implementation and the ability to guarantee minimum bandwidths to individual buffers. Packetized generalized processor sharing is briefly discussed and a minimum bandwidth result for self-clocked fair queueing is given. The authors revisit an approach originally proposed by Zhang (1991) and prove that it is appropriate for ATM. Some novel, related approaches are described and analyzed.