This brief contribution proposes a new class of systolic-arrays to perform Binary Reed-Solomon (RS) decoding procedures including erasure correction. Such RS decoder is suitable for VLSI implementation since the arrays consist of simple processing elements of the same type.>

In recent years, many systolic algorithms have been proposed as solutions to computationally demanding problems in signal and image processing and other areas. Such algorithms exploit the regularity and parallelism of problems to achieve high performance and low I/O requirements. Since systolic algorithms generally consist of a few types of simple processors, or systolic cells, connected in a regular pattern, they are less expensive to design and implement than more general machines.

The main contribution of this paper is the design of a hardware sorter. This sorter is configured as a balanced, fixed binary tree of node units; the configuration of the sorter is independent of the length of data to be sorted. Each node unit can be realized on a single LSI chip. The logic of the hardware sorter design is heavily influenced by a specific, compressed, representation of sorted data. Using this hardware sorter and a few auxiliary functions based on the sorted property, we demonstrate the design of a relational data base machine.