With widespread use of raster scan displays and the ever-increasing desire for faster interactivity, higher image complexity, and higher resolution in displayed images, several techniques have been proposed for rasterizing primitive graphical objects. This paper characterizes the performance of these techniques and shows how they evolve for more complex images on higher resolution displays. This characterization will not only show the strengths and deficiencies of existing rasterization techniques, but will also reveal new architectures for future raster graphics systems.

The desire for higher performance and higher resolution continuously increases the pixel update rates needed in high performance graphics systems. The increasing density of memory chips on the other hand reduces the pixel update rate that can be provided by the frame buffer. We present the design of a VLSI chip and a graphics system that can sustain sub-nanosecond pixel rendering rates for three-dimensional polygons and can be used to render about a million Z-Buffered and Gourard shaded polygons per second. The chip has been designed at the IBM Research Division's Thomas J. Watson Research Center.

This paper describes a display system designed to make the recording and rearrangement of bits in a frame-buffer display system convenient and rapid.The advantage of frame-buffer displays is that because the intensity of each pixel can be specified independently, any picture can be displayed.The disadvantage is that a great many bits in the frame-buffer memory must be changed to make major changes in the picture.The 8 by 8 display described in this paper gets its name from the fact that in a single memory cycle it can access any 8 by 8 square of pixels.Internal shifters and special memory addressing circuits are provided to make the access independent of word boundaries in the memory.Pixel manipulation functions are included to process the 64 pixels thus accessed, mask them, overwrite them with new information, or combine them logically with other pixels.The resulting data can be stored into any other 8 by 8 square of pixels in a subsequent memory cycle.Looping mechanisms implemented in microcode provide RasterOp functions that transfer information from any rectangular area of the display to any other area with or without intervening pixelmodification operations.The prototype system is able to copy the entire 768 by 1024 array of the display in 52 ms, or two frame times.The ability to rearrange data quickly has proved to be an asset for character generation, line drawing, and picture construction, as well as for scrolling and other rearrangements of material already displayed on the screen.A simple model is developed to compare the performance of the 8 by 8 memory system with conventional frame-buffer organization.Execution traces of Smalltalk display programs are applied to the model to obtain figures of merit for different hardware organizations.

While simple line-drawing techniques produce “jagged” lines on raster images, more complex anti-aliasing, or filtering, techniques use gray-scale to give the appearance of smooth lines and edges. Unfortunately, these techniques are not frequently used because filtering is thought to require considerable computation. This paper presents a simple algorithm that can be used to draw filtered lines; the inner loop is a variant of the Bresenham point-plotting algorithm. The algorithm uses table lookup to reduce the computation required for filtering. Simple variations of the algorithm can be used to draw lines with different thicknesses and to smooth edges of polygons.

Interactive use of a display requires the capability to update the display rapidly. This paper describes an on-going project at Carnegie-Mellon University in which we are designing a frame buffer raster-scan display system which has the high performance typically required for interactive display applications. The system is intended to be a display for personal computers, computer generated graphic images, and image processing applications. Built using smart VLSI memory chips, the system will use parallel processing techniques to provide high performance.