There are situations (e.g. for reverse engineering or formal verification) circuit designers would need to extract complicated arithmetic circuitry deeply embedded inside a fully synthesized (or manually touched) million-gate flattened netlist without the knowing of module boundary and IO positions. Besides not knowing the IO and boundary, a formal verification task like comparing two netlists implementing (4A+3B)×C and 4A×C+3B×C respectively is quite challenging for it is an NP-Complete Circuit-SAT problem too. To tackle this problem, we propose a novel Complementary Greedy Coupling (CGC) approach coupling reverse engineering and SAT techniques together for each of them only performs well at proving equality or inequality respectively. The scheme is quite powerful, being able to handle commonly implemented arithmetic modules (Ripple/CLA adders, MUX, various multipliers and their combinations) with runtime complexity nearly linear to the number of circuit gates. For an example, our scheme can verify two 32-bit multipliers (Wallace vs Modified-Booth) within 5 seconds (regardless of their equality or inequality), while running SAT alone might take 1010 centuries. We compared our tool Easy-LEC with the two on market commercial tools using the 182 open benchmarks posted for ICCAD CAD Contest 2014. Besides running at least 400 to 1400 times faster, our scheme also solves 32% to 45% more cases (93% vs 61% or 48%).

A macro-fault is defined as a group of signal faults such that the errors induced cannot be observed unless two or more faults (either permanent or temporary) in the group happen simultaneously. Since adding a redundant (alternative) wire for an existing (target) wire can mask some certain faults of these two wires mutually, a macro-fault can be formed by redundant wire addition. The faults that are dominated by or equivalent to the masked faults are also included in the macro-fault. As the feature size of integrated circuit technologies continue to scale down, manufacturing fault-free chips is getting more difficult and fault tolerance techniques will become more critical. In the past, redundancy has been adopted for memory for improving fault tolerance. For critical circuit components, even the costly triple modular redundancy techniques have to be applied. In this work, we study the implications of our new fault model, macro-fault, on the potential impact on fault tolerance and manufacturing yield. Based on the findings, a heuristic approach based on redundant wire addition is designed for improving fault tolerance. The approach can be incorporated with other fault tolerance techniques to form a hierarchical cross-layer fault tolerance scheme.

Rewiring is a flexible and useful logic transformation technique through which a target wire can be removed by adding its alternative logics without changing the circuit functionality. In today's deep sub-micron era, circuit wires have become a dominating factor in most EDA processes and there are situations where removing a certain set of (perhaps extremely unwanted) wires is very useful. However, it has been experimentally suggested that the rewiring rate (percentage of original circuit wires being removable by rewiring) is only 30 to 40% for optimized circuits in the past. In this paper, we propose a generalized error cancellation modeling and flow to show that theoretically almost every circuit wire is removable under this flow. In the Flow graph Error Cancellation based Rewiring (FECR) scheme we propose here, a rewiring rate of 95% of even optimized circuits is obtainable under this scheme, affirming the basic claim of this paper. To our knowledge, this is the first known rewiring scheme being able to achieve this near complete rewiring rate. Consequently, this wire-removal process can now be considered as a powerful atomic and universal operation for logic transformations, as virtually every circuit node can also be removed through repetitions of this rewiring process. Besides, this modeling can also serve as a general framework containing many other rewiring techniques as its special cases.

Rewiring is known to be a class of logic restructuring technique that is at least equally powerful in flexibility compared to other logic transformation techniques. Especially it is wiring sensitive and is particularly useful for interconnect-based circuit synthesis processes. One of the most well-studied rewiring techniques is the ATPG-based Redundancy Addition and Removal (RAR) technique which adds a redundant alternative wire to make an originally irredundant target wire become redundant and thus removable. In this article, we propose a new Error-Cancellation-based Rewiring scheme (ECR) which can also identify non-RAR-based rewiring operations with high efficiency. In ECR scheme, it is not necessary for alternative wires to be redundant. Based on the notion of error cancellation, we analyze and reformulate the rewiring problem, and a more generalized rewiring scheme is developed to detect more rewiring cases which are not obtainable by existing schemes while it still maintains a low runtime complexity. Comparing with the most recent non-RAR rewiring tool IRRA, the total number of alternative wires found by our approach is about doubled (202%) while the CPU time used is just slightly more (8%) upon benchmarks preoptimized by ABC’s rewriting. Our experimental results also suggest that the ECR engine is more powerful than IRRA in FPGA technology mapping.

All of today's known clock gating techniques only disable clocks on valid (”correct”) clock gating conditions, like idle states or observability don't cares (ODC), whose applying will not change the circuit functionality. In this paper, we explore a technique that allows shutting down certain clocks during invalid cycles, which if applied alone will certainly cause erroneous results. However, the erroneous results will be corrected either during the current or later stages by injecting other clock gating conditions to cancel out each other's error effects before they reach the primary outputs. Under this model, conditions across multiple flip-flop stages can also be analyzed to locate easily correctable erroneous clock gating conditions. Experimental results show that by using this error cancellation technique, a total power (including dynamic and leakage power) cut of up to 23% and in average of around 6% could be stably achieved, no matter with or without applying Power Compiler (which brought a power cut of 4% in average) together. The results indicate that the power saving conditions found by this new technique were nearly orthogonal (independent) to what can be done by the popular commercial power optimization tool. The idea of these new multi-stage logic error cancellation operations can potentially be applied to other sequential logic synthesis problems as well.

Rewiring is known to be a new class of logic restructuring technique at least equally powerful in flexibility compared to other logic transformation techniques while being wiring-sensitive, a property particularly useful for interconnect based circuit synthesis processes. One of the most mature rewiring techniques is the ATPG-based Redundancy Addition and Removal (RAR) technique which adds a redundant alternative wire to make an originally irredundant target wire become redundant and thus removable. In this paper, we propose a new Error Cancellation based Rewiring scheme (ECR) which can also do non-RAR based rewiring operations with high efficiency. Based on the notion of error cancellation, we analyze and reformulate the rewiring problem and develop a generalized rewiring scheme being able to detect more rewiring cases which are not obtainable by existing schemes while still maintains low runtime complexity. Comparing with the most recent non-RAR rewiring tool IRRA, the total number of alternative wires found by our approach is about twice while CPU time is just slightly more (26%) upon benchmarks pre-optimized by rewriting of ABC.

Traditionally, clock gating for power saving is mainly done at Register Transistor Level (RTL), while in a lower logical level some synthesis techniques, e.g. Observability Don't Care (ODC) can also be used to provide more power savings. In this paper, we propose an effective logic level ODC-based clock gating scheme that aims to reduce the intra-module dynamic power of sequential circuits. It is accompanied with a rewiring-based pruning scheme to trim down the incurred area overhead. Switching activity is put into account in the optimization processes. Extensive experimental results obtained by using ModelSim and PowerCompiler on the ISCAS-89 benchmarks showed that without rewired area trimming, an average of 40% on clock power and 12% on total dynamic power can be saved with a total cell area overhead of 6%. When rewiring was applied to trim down the area overhead, a similar clock power saving of 40% and an appealing 17% of total dynamic power saving can be achieved with area similar (-1%) to the original non ODC-clock-gated circuits.