Summary In this article, we propose an ensemble neural network approach so that multiple neuron network models can be deployed concurrently for detecting anomalies in a system. Additionally, a high‐performance architecture integrating the neural networks for reconfigurable hardware is also designed to exploit the parallelism of the technology. We carefully implement four different models for detecting SYN, DNS, UNP, and ICMP attacks with the same configuration of neural networks on the NetFPGA platform. The neural networks can be executed in the pipeline to improve performance. Experiments with the generated dataset are conducted to test both performance in terms of throughput and accuracy. Our experimental results show that the system can process packets with throughput up to 30.48Gbps and is able to recognize 99.98% attacking packets with only 0.98% false alarms.

Abstract Traffic is very terrible in most big cities. These cities need many traffic police to control traffic congestion. They can change the duration of traffic lights to reduce levels of congestion of corners. However, the time changed by them is determined just only the feeling of themselves. Making decisions suitable for current congestion at that moment is not trivial. The resistant questions are how to define the logical time of traffic lights or how is an effect of this corner to the consecutive one. Maybe we need to increase the time of the green light at the next corner because of the traffic jam at this corner. The link between two corners is interaction inside concurrent processes. Besides, some exceptional cases also need to be handled, for instance, ambulances or fire trucks. The green light needs to be turned on when they come, and turn back the red light state later. This article proposes a tentative approach that uses context types, including locations, priorities of cars, velocity, and remaining time (the car comes to the corner) to determine traffic light periods. The context‐aware is applied in the infrastructure of the Internet of Things when transferring information to the corner. Maybe, in the future, the other systems such as Arduino, Raspberry pi, or other embedded systems will be joined in the designs as acting part (turn the traffic lights on/off ) and communicating role (connecting to the Internet via wifi) to control the duration of the traffic lights.

Summary Over the last decades, Bioinformatics has been being in its honeymoon phase with more and more new algorithms as well as their improvements proposed. In Bioinformatics, the sequence alignment step is considered as an integral part that directly contributes to the DNA, RNA, or protein identifications. Despite the undeniable enhancements from the provided algorithms and computing architectures in the recent years, it is still far more to state that sequence alignment has already achieved the ideal performance. In this work, we focus on one of the most perfect justifiable steps in a state‐of‐the‐art DNA/RNA alignment algorithm, the seed extension step in the BWA‐MEM algorithm. We propose a high‐speed and less power consumption FPGA‐based IP core that is designed in a pipeline model under various FPGA technologies. Our core is able to operate at more than 200 MHz in almost all FPGA architectures and even up to 529 MHz on a Xilinx Virtex 6 FPGA device. The core can provide speed‐ups by up to 350× when compared with an Intel Core i5 general purpose processor.

As one of the main types of Distributed Denial of Service (DDoS) attacks, SYN flood attacks have caused serious issues for servers when legitimate clients may be denied connections. There is an essential demand for a sufficient approach to mitigate SYN flood attacks. In this paper, we introduce an efficient high-throughput and low-latency SYN flood defender architecture, carefully designed with a pipeline model. A mathematical model is also introduced with the architecture for estimating SYN flood protection throughput and latency. The first prototype version based on the architecture with Verilog-HDL can function as standalone to alleviate high-rate SYN flood attacks and can be integrated into an OpenFlow switch for handling network packets. Our experiments with NetFPGA-10G platforms show that the core can protect servers against SYN flood attacks by up to 28+ millions packets per second that outperforms most well-known hardware-based approaches in the literature.

High-level synthesis (HLS) is an automated design process that deals with the generation of behavioral hardware descriptions from high-level algorithmic specifications. The main benefit of this approach is that ever-increasing system-on-chip (SoC) design complexity and ever-shorter time-to-market can still be both manageable and achievable. This advantage, coupled with the increasing number of available heterogeneous platforms that loosely couple general-purpose processors with Field Programmable Gate Array-based co-processors, led to an increasing attention for HLS tool development and optimization from both the academia as well as the industry. However, in order for HLS to fully reach its potential, it is imperative to look simultaneously at local HLS optimizations as well as to HLS system-level integration and design space exploration issues. In this paper, we present the Delft Workbench tool-chain that takes C-code as input and generates, in a semi-automatic way, a complete system. Subsequently, we describe the design and output code optimization of the DWARV 3.0 HLS compiler using the CoSy compiler framework. Based on this experience, we provide an overview of similarities and differences in leveraging this commercial compiler framework to build a hardware compiler as opposed to building a software compiler. Finally, we report speedups up to 3.72x at application level and development times measurable in hours rather than weeks.

The communication infrastructure is one of the important components of a multicore system along with the computing cores and memories. A good interconnect design plays a key role in improving the performance of such systems. In this paper, we introduce a hybrid communication infrastructure using both the standard bus and our area-efficient and delay-optimized network on chip for heterogeneous multicore systems, especially hardware accelerator systems. An adaptive data communication-based mapping for reconfigurable hardware accelerators is proposed to obtain a low overhead and latency interconnect. Experimental results show that the proposed communication infrastructure and the adaptive data communication-based mapping achieves a speed-up of 2.4× with respect to a similar system using only a bus as interconnect. Moreover, our proposed system achieves a reduction of energy consumption of 56% compared to the original system.

Multicore architectures, especially hardware accelerator systems with heterogeneous processing elements, are being increasingly used due to the increasing processing demand of modern digital systems. However, data communication in multicore architectures is one of the main performance bottle-necks. Therefore, reducing data communication overhead is an important method to improve the speed-up of such systems. In this paper, we propose a heuristic-based approach to address the data communication bottleneck. The proposed approach uses a detailed quantitative data communication profiling to generate interconnect designs automatically that are relatively simple, low overhead and low area solutions. Experimental results show that we can gain speed-up of 3.05× for the whole application and up to 7.8× speed-up for accelerator functions in comparison with software.