Static timing analysis (STA) is essential for timing closure. To address the complicated effects emerging at advanced technology nodes, the Current Source Model (CSM) has been developed to compute timing waveforms for timing propagation. Compared with Non-Linear Delay Model (NLDM), CSM provides superior accuracy but suffers from the efficiency and scalability issue. In this paper, we propose a multi-stage CSM timing propagation framework with three acceleration techniques with the assistance of NLDM. Our acceleration techniques are general and compatible with any CSM-based STA engine. Experimental results demonstrate the effectiveness of our acceleration techniques: Compared with CSM-based analysis, we achieve 4× speedups with only 0.4% accuracy loss.

Timing macro modeling has been widely employed to enhance the efficiency and accuracy of parallel and hierarchical timing analysis. However, existing studies primarily focused on generating an accurate and compact timing macro model for single-corner libraries, making it difficult to adapt these approaches to multi-corner situations. This either incurs substantial engineering effort or results in significant performance degradation. To tackle this challenge, we offer a fresh perspective on the timing macro modeling problem by drawing inspiration from recommendation systems and formulating it as a matrix completion task. We propose a neural collaborative filtering-based framework capable of capturing the convoluted relationships between circuit pins and timing corners. This framework enables the precise identification of timing variant regions across different corners. Additionally, we design several training features and implement various training techniques to enhance precision. Experimental results show that our framework reduces model sizes by more than 10% compared to state-of-the-art single-corner approaches, while maintaining competitive timing accuracy and exhibiting significant runtime improvements. Furthermore, when applied to unseen corners, our framework consistently delivers superior performance, demonstrating its potential for use in off-corner chiplets in a heterogeneous integration system.

Due to rapidly growing design complexity, timing macro modeling has been widely adopted to enable hierarchical and parallel timing analysis. The main challenge of timing macro modeling is to identify timing variant pins for achieving high timing accuracy while keeping a compact model size. To tackle this challenge, prior work applied ad-hoc techniques and threshold setting. In this work, we present a novel timing macro modeling approach based on graph neural networks (GNNs). A timing sensitivity metric is proposed to precisely evaluate the influence of each pin on the timing accuracy. Based on the timing sensitivity data and the circuit topology, the GNN model can effectively learn and capture timing variant pins. Experimental results show that our GNN-based framework reduces 10% model sizes while preserving the same timing accuracy as the state-of-the-art. Furthermore, taking common path pessimism removal (CPPR) as an example, the generality and applicability of our framework on various timing analysis models and modes are also validated empirically.

As technology advances, the complexity and size of integrated circuits continue to grow. Hierarchical design flow is a mainstream solution to speed up timing closure. Static timing analysis is a pivotal step in the flow but it can be timing-consuming on large flat designs. To reduce the long runtime, we introduce ATM, a high-accuracy extracted timing model for hierarchical timing analysis. Interface logic model (ILM) and extracted timing model (ETM) are the two popular paradigms for generating timing macros. ILM is accurate but large in model size, and ETM is compact but less accurate. Recent research has applied graph compression techniques to ILM to reduce model size with simultaneous high accuracy. However, the generated models are still very large compared to ETM, and its efficiency of in-context usage may be limited. We base ATM on the ETM paradigm and address its accuracy limitation. Experimental results on TAU 2017 benchmarks show that ATM reduces the maximum absolute error of ETM from 131 ps to less than 1 ps. Compared to the ILM-based approach, our accuracy differs within 1 ps and the generated model can be up to 270x smaller.

It is crucial for future 5G networks to intelligently understand how users move so that the networks can allocate different resources efficiently. In this paper, we try to find practical features to identify four common types of motorized transportations, including High-Speed Rail (HSR), subway, railway, and highway. We propose a system architecture that can provide accurate, real-time, and adaptive solution by using cellular information only. Because we do not use GPS as that in most of the prior studies, we can reduce energy consumption, size of log data, and computational time. Around 500-hour data are collected for performance evaluation. Experimental results confirm the effectiveness of the proposed algorithm, which can improve well-known machine learning algorithms to approximately 98% classification accuracy. The results also show that battery consumption can be reduced about 37%.

As design complexity rapidly grows, a modem design contains more complex constraints and has more clock domains. To these stringent timing requirements, a design is iteratively optimized. Along with intensive optimizations, fast timing analysis guiding designers to fix timing violations is desired. Thus far, previous works have focused on either timing exception handling or path search only. Different from them, in this paper, we tackle these two issues together for the urgent need in modern design. We first generalize timing exceptions to model all common timing exceptions and other path-specific timing quantities. Then, we propose a novel timing analysis flow that performs fast path search for generalized timing exception handling. Furthermore, we develop three delicate techniques to achieve fast path search, including local slack bounds, dynamic slack recovering, and slack priority queue. Experimental results show that our model is general, and our flow is promising with high efficiency and scalability.

Mobile Crowd Sensing (MCS) is a promising paradigm to collect large-scale network data globally. However, how to motivate people to collect and share data is a challenge. We believe the major reason why many MCS systems are not pervasive is because there are no incentives for people to use them. In this paper, we present SensingGO, a system which encourages people to keep sensing data by integrating incentive mechanisms. The sensed data are then transmitted to our backend server. The data we collected and the source code of SensingGO are open to anyone freely. We also demonstrate the analysis of real mobile data collected from SensingGO.

As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this article, we present compact and accurate timing macro modeling, which is the key to efficient and accurate hierarchical timing analysis. Our goal is to contain only a minimal amount of interface logic in our timing macro model. The main idea is to separate the interface logic into variant and constant timing regions. Then, the variant timing region is reserved for accuracy, while the constant timing region is reduced for compactness. For reducing the constant timing region, we propose anchor pin insertion and deletion by generalizing existing timing graph reduction techniques. Furthermore, we devise a lookup table index selection technique to achieve high model accuracy over the possible operating condition range. Compared with two common models used in industry, extracted timing model and interface logic model, our model has high model accuracy and small model size. Based on the TAU 2016 and 2017 timing macro modeling contest benchmark suites, our results show that our algorithm delivers superior efficiency and accuracy: Hierarchical timing analysis using our model can significantly reduce runtime and memory compared with flat timing analysis on the original design. Moreover, our algorithm outperforms TAU 2016 and 2017 contest winners in model accuracy, model size, model generation performance, and model usage performance.

In this paper, we present DATC Robust Design Flow Database covering the stages from logic synthesis to physical design [1]. Based on this database, design flow and cross-stage optimization research can be conducted via various EDA tools developed from academia.

As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this paper, we propose compact and accurate timing macro modeling, which is the key to achieve efficient and accurate hierarchical timing analysis. Our macro model tries to contain only a minimal amount of interface logic. For timing graph reduction, we propose anchor pin insertion and deletion by generalizing existing reduction techniques. Furthermore, we devise a lookup table index selection technique to achieve high model accuracy over the possible operating condition range. Compared with two common models used in industry, extracted timing model and interface logic model, our model has high model accuracy and small model size. Based on the TAU 2016 timing contest on macro modeling benchmark suite, our results show that our algorithm delivers superior efficiency and accuracy: Hierarchical timing analysis using our model can significantly reduce runtime and memory compared with flat timing analysis on the original design. Moreover, our algorithm outperforms TAU 2016 contest winner in model accuracy, model size, model usage runtime and memory.

To achieve timing closure, performance-driven optimizations are repeatedly performed throughout the modern IC design flow. Along with these optimization operations, how to incrementally update timing information efficiently and accurately becomes a crucial task for fast turnaround time. On the other hand, to avoid wasteful over-optimization, clock path pessimism should be removed during timing analysis. In order to provide prompt timing information without over-pessimism during iterative optimizations, in this paper, we aim at fast incremental timing and CPPR analysis. We present two delicate techniques, lazy evaluation and lazy propagation, to avoid redundant updates. Our experiments are conducted on the benchmark suite released by TAU 2015 timing analysis contest. Experimental results show that our timer delivers the best results in terms of accuracy, runtime, and memory over all participating teams.