A novel double floating-gate unified memory device is experimentally demonstrated for the first time. The device can be used to store both volatile and nonvolatile memory states simultaneously. Simulations of scaled devices show that the device offers several advantages compared to conventional memory devices. Such a device could have a dramatic impact on next generation memory architectures.

New architectures for the switch box and connection block are proposed for use in an energy efficient field programmable gate array (FPGA) with bidirectional wiring. Power-hungry SRAMs are replaced by non-volatile nanocrystal floating gate (NCFG) devices that retain their state while the system power is off and do not need to be configured at boot up. The NCFG-based FPGA is benchmarked against both a traditional bidirectional and a modern unidirectional SRAM-based FPGA using a 32-tap FIR Filter designed in HSPICE based on predictive BSIM4.0 CMOS with 45nm gate length technology and a previously developed physical model of the NCFG device. Compared to the traditional bidirectional and the modern unidirectional SRAM-based interconnect the total gate area is reduced by 87% and 63%, respectively. Simulations demonstrate a reduction of 58% in static and 34% in dynamic power consumption compared to the traditional bidirectional SRAM-based FPGA while the signal propagation delay through a switch box is decreased by 28%. When compared to the modern unidirectional SRAM-based FPGA the proposed design has roughly comparable power consumption but the circuit complexity is greatly reduced as a result of doubling the available routing channels. Alternatively the number of the routing channels may be reduced to save area and power whereas the complexity remains similar. The potential benefits from choosing the proposed design can be summarized as small area, low power consumption, high speed and high functionality, which typically trade off and cannot be achieved by the SRAM-based counterparts simultaneously. Compared to previous designs that use continuous floating gate devices in FPGAs, the approach described in this work requires less overhead, lower voltages, and offers improved reliability.