Precise on-chip phase control of microwave transmission is critical to today’s signal processing and wireless communication electronics. Thus far, achieving even modest phase-shifting resolution has involved a complex mix of semiconductor switches and passive electromagnetic structures. These delay circuits operate near resonances that heavily attenuate and distort signals, limiting modulation bandwidth. In this article, we introduce a mechanism whereby miniature waveguide reflectors based on coupled resonances can be reprogrammed to evade loss. Central to their operation is that loss from these resonances is confined to low frequencies, while at high frequencies, the waveguides’ reflectivity is maximized and broadband phase variations, induced by those resonances, still persist. Since performance in the low-loss post-resonance spectrum is largely agnostic to the number of switches, ultra-fine digital tuning is possible. This breaks the historical tradeoff between loss and precision. When inserted in a reflective-type structure, a phase resolution of under 0.3° is achieved, surpassing state-of-the-art CMOS circuits by over three orders (bits) of magnitude while incurring only$5~\pm ~2.5$dB of loss over the 20-30 GHz 5G MIMO band. The phase- shifter is highly linear, with an input third-order intercept point (IIP3) of over 25 dBm. Moreover, it consumes no DC power and occupies a sub-wavelength footprint of 0.064 mm2 in a 28 nm Fully Depleted Silicon-on-Insulator (FDSOI) CMOS platform. This makes it an optimal candidate for seamless integration in on-chip multi-gigabit data links, radio astronomy transceivers and control hardware for millimeter-wave qubits.

There has been a resurgence of interest in vector architectures evident by recent adoption of vector extensions in mainstream instruction set architectures. Traditionally, vector engines leverage this abstraction by exploiting its inherent regularity to increase performance and efficiency. Recent work on SRAM-based compute-in-memory has shown promise in reducing the area overhead of these engines. In this work, we propose ephemeral vector engines (EVE) where we leverage SRAM-based compute-in-memory techniquesas well as bit-peripheral computations to facilitate efficient vector execution. EVE uses a novel approach of bit-hybrid execution, striking a balance between throughput and latency. Evaluated on the Rodinia and RiVEC benchmark suites, EVE achieves almost 8× speed-up compared to an out-of-order processor and 4.59× compared to an integrated vector unit. EVE achieves speed-ups comparable to an aggressive decoupled vector unit and increases the area-normalized performance by over 2 ×. By repurposing SRAM arrays in the L2 cache to create ephemeral vector execution units, EVE is able to efficiently achieve high performance while incurring as little as 11.7% area overhead.

Practical, in-band, full-duplex (IBFD) systems typically require more than 100 dB of self-interference cancellation (SIC). Digital processing alone is insufficient for achieving this target, which drives us towards supplementary analog mitigation techniques. We propose an analog-domain, self-interference cancellation circuit to enable pass-band, analog SIC in an IBFD system. Analog SIC is limited by several hardware constraints and design choices, including finite tap-delay resolution, non-negative tap constraints, and bit precision quantization. We characterize the performance impact of each of these limitations as a function of signal bandwidth, carrier frequency, bit precision, and other system design parameters. We further characterize the achievable system performance under all of these limitations combined. We simulate several realistic examples to illustrate the relationship between the achievable self-mitigation performance and various system design choices. We implement a simple constrained optimization algorithm informed by these results to optimize the tap-delay weights of the analog circuit under these system constraints. We simulate the achievable mitigation performance and demonstrate as much as 45 dB of analog-domain, self-interference mitigation of a wide-band signal with realistic system configurations.

In this paper, we demonstrate a prototype system for path independent local oscillator (LO) synchronization of a distributed beamformer in wireless ad hoc networks. The system contains a low power full duplex (FD) transceiver IC, a RF phase interpolator IC, and a CDMA encoder/decoder to realize a conjugate loop and synchronize the LO’s of two RF nodes. Both ICs were fabricated in 180nm CMOS technology. The FD transceiver IC consumes 69mW at 700MHz and the RF phase interpolator IC consumes 75mW at 1.4GHz. Using the low power ICs, we demonstrate a simple, lightweight, and robust methodology to synchronize two LO’s with an average phase precision of 2.1° and 94% maximum beamforming gain using RF only transmissions via a single antenna per node.

Vector accelerators can efficiently execute regular data-parallel workloads, but they require expensive multi-ported register files to feed large vector ALUs. Recent work on in-situ processing-in-SRAM shows promise in enabling area-efficient vector acceleration. This work explores two different approaches to leveraging in-situ processing-in-SRAM: BS-VRAM, which uses bit-serial execution, and BP-VRAM, which uses bit-parallel execution. The two approaches have very different latency vs. throughput trade-offs. BS-VRAM requires more cycles per operation, but is able to execute thousands of operations in parallel, while BP-VRAM requires fewer cycles per operation, but can only execute hundreds of operations in parallel. This paper is the first work to perform a rigorous evaluation of bit-serial vs. bit-parallel in-situ processing-in-SRAM. Our results show that both approaches have similar area overheads. For 32-bit arithmetic operations, BS-VRAM improves throughput by 1.3-5.0× compared to BP-VRAM, while BP-VRAM improves latency by 3.0-23.0× compared to BS-VRAM.

Recent advances in reconfigurable RF front end circuits, such as passive mixer first receivers have opened the door to the possibility of building radios that can be programmed to both transmit and receive across octaves of frequency while maintaining reasonable performance and extremely high levels of integration. One of the remaining challenges in software defined radio hardware is the construction of a flexible RF system capable of duplex operation. Specifically, transmitting and receiving on the same antenna across a wide band of frequencies presents a significant challenge. This paper presents some of the primary challenges that arise in this space, as well as some interesting published and potential solutions.

In this paper, we propose a dual-calibration technique to improve the matching accuracy of digital-to-analog converter (DAC) elements and improve nonlinearity induced static errors in a current-steering thermometer DAC. The novelty of the proposed dual-calibration scheme lies in obtaining best samples from the error distribution using redundancy for improved matching followed by adaptively reordering these samples to reduce error accumulation. This technique exploits the 2-D nature of the DAC to achieve lower calibration time. We consider the statistical basis for each of these methods and demonstrate statistical modeling of the proposed technique. We demonstrate a 38% reduction in differential nonlinearity (DNL) and 55% reduction in integral nonlinearity (INL) through simulations. We fabricated an 8-bit current steering thermometer DAC in Taiwan Semiconductor Manufacturing Company 65-nm CMOS process. With only 2 redundant cells per row, we show an improvement of 36% in DNL and 50% in INL from the measurement of 16 chips over the baseline DAC.

In this paper, we present analysis and design of a pulse coupled oscillator capable of synchronizing a peer-to-peer (P2P) network to an arbitrarily slow clock. Slow clocks, while desirable for synchronizing low data rate P2P networks and minimizing power consumption, are difficult to realize with analog relaxation oscillators. We present a digital counter based design as an alternative and characterize the unique issues that emerge from the discreteness of this design in both time and level. We discover that the discrete nature of this circuit gives rise to two alternative approaches to pulse coupling, and find that the one that delays the reset of the counter is a significantly better choice for enabling high quality synchronization with lower cost in time-to-synchronize. We present a final design in 65nm CMOS based upon this analysis.

Recent work has shown that monolithic integration of voltage regulators will be feasible in the near future, enabling reduced system cost and the potential for fine-grain voltage scaling (FGVS). More specifically, on-chip switched-capacitor regulators appear to offer an attractive trade-off in terms of integration complexity, power density, power efficiency, and response time. In this paper, we use architecture-level modeling to explore a new dynamic voltage/frequency scaling controller called the fine-grain synchronization controller (FG-SYNC+). FG-SYNC+ enables improved performance and energy efficiency at similar average power for multithreaded applications with activity imbalance. We then use circuit-level modeling to explore various approaches to organizing on-chip voltage regulation, including a new approach called reconfigurable power distribution networks (RPDNs). RPDNs allow one regulator to "borrow" energy storage from regulators associated with underutilized cores resulting in improved area/power efficiency and faster response times. We evaluate FG-SYNC+ and RPDN using a vertically integrated research methodology, and our results demonstrate a 10-50% performance and 10-70% energy-efficiency improvement on the majority of the applications studied compared to no FGVS, yet RPDN uses 40% less area compared to a more traditional per-core regulation scheme.

Process variation is an obstacle in designing reliable CMOS mixed signal systems with high yield. To minimize the variation in voltage gain due to variations in process, supply voltage, and temperature for common transconductance-based amplifiers, we present a new compensation method based on statistical feedback of process information. We develop the background theory of the scheme and present its performance across process corners. We further apply our scheme to two well known amplifier topologies in the TSMC 65 nm CMOS process as design examples-an inductive degenerated low-noise amplifier (LNA) and a common source amplifier (CSA). Measured results over 100 chips of the LNA show that our compensation technique reduces variation in gain by a factor of 3.7× compared to the baseline case. The CSA exhibits similar reductions in gain variation across 88 measured chips. We also present measured results demonstrating how our technique alleviates voltage gain variations caused by temperature and supply voltage changes.

In this paper we present a simple methodology that utilizes the timing-bins in a globally synchronized wireless sensor network to broadcast event information throughout the network. The proposed scheme enables classification as well as per node localization of an event by using bins as hop-counts. A simple implementation of immediate neighborhood validation is also proposed to prevent false-trigger. The neighborhood validation scheme enables self-healing of a faulty sensor node and can be disabled by incorporating self-validation. The proposed schemes are designed to be used in combination with impulse based UWB systems, and help reduce the need for complex MAC/Routing based packet communication in these networks. The proposed scheme implements dynamic duty-cycling as well as dynamic message sizing, ensuring low power consumption during idle as well as event communication phases. A further extension of this methodology can also be used for normal peer-peer packet based communication in conjunction with the event classification feature.

In this paper, we present a low-cost, low-power integrated dynamic background subtraction scheme for wireless real-time neurochemical monitoring in freely-moving animals. We derive the theoretical dynamic range enhancement of the proposed scheme and analyze the effects that quantization noise and output swing, normalized to full scale, impose on this figure. Preliminary simulation results indicate an effective resolution of 14 bits for a swing of 2.5% full scale using a 9-bit successive- approximation register (SAR) analog-to-digital converter (ADC) in a two-step conversion approach.

In this work, we report the results of an active dispersive delay line (DDL) designed out of a distributed amplifier based transversal filter (DATF) with 12 gain cells, achieving the average gain of 2 dB and group delay variance of 3 ns from 3 to 5 GHz. Simulation based upon the measurements of a gain cell and transmission line fabricated with high speed PC Boards demonstrates that the DDL can be utilized as a real time signal processing block for an ultra-wideband (UWB) system. This work could potentially open the door for CMOS integration of DDLs.

Impulse Radios within communication networks using Pulse Coupled Oscillator (PCO) global synchronization can be efficiently duty cycled for significant power savings. In this paper we utilize the emergent dynamical behavior in the PCO network to enable a simple event communication scheme particular to this type of network. In this scheme, each coupled radio node accesses the channel by simply changing its pulse repetition frequency in response to an event sensed by its sensor. This forces the network to a new, higher operating frequency, which can be locally measured at every node in the network to communicate occurrence of an event in the network. In this paper we show how this synchronization occurs and how it is ideally suited for low power operation. The proposed event propagation scheme enables a node to broadcast information about an event to an entire network in a simple fashion without the need of any data-packet formation or complex MAC/Routing protocols. We show that resynchronization and recovery of the network happens almost immediately. The latency involved corresponds to the distance-delay (due to finite speed of light) plus a very small circuit delay of (4-5ns) per hop related to detection of impulses.

In this paper we present the design and measured results of a duty-cycled, non-coherent Impulse Radio transceiver. The designed transceiver was measured to consume only 19μW at a data-rate of 100kbps. The design gives a BER of 10-5and works for a range of 2.5m at an average Rx-sensitivity of -81dBm, making it useful for low-power short-range wireless communication systems such as body area networks. The transceiver enables both OOK and BPSK schemes and can be configured to use a pseudo-coherent self-correlated signature detection and generation mechanism. This added functionality helps distinguish different types of pulses such as timing and data-pulses in real time. The transceiver was designed in a 90nm CMOS process and occupies 2.3mm2area.

We present the design of a 4.6 GHz LNA in TSMC 65nm with a feedback scheme to compensate for variations across process, supply voltage, and temperature. No post fabrication efforts are required in this compensation method. The proposed method improves the variation in S21of an inductively degenerated cascode LNA from 8.75% to 1.27%, which is a reduction in variation of 85%. The presented scheme is also robust over variations in supply voltage, temperature, and process conditions. The compensation method presented can be utilized to stabilize the gain of a wide variety of amplifiers.

In this paper, we present a successive approximation based compensation scheme to minimize the process and temperature induced variation in a ring oscillator topology. This scheme is able to reduce the standard deviation of the oscillation frequency to less than 2%, as compared to more than 9.3% in a typical uncompensated ring oscillator implemented in 65 nm CMOS process. The improved variation performance of the proposed scheme is supported by simulation results over a wide frequency range and under different process and temperature conditions in 65 nm technology.

In this paper we present the design and the measured results for a FCC-compliant UWB impulse transmitter (Tx) designed to operate in the 3-5GHz range. The transmitter uses a fast start-up, duty-cycled, current-starved ring-oscillator topology. A triangular pulse-shaping technique is utilized for spectrum-shaping to facilitate FCC compliance. The designed transmitter can be controlled to operate in 3-different bands centered at 3.5GHz, 4.0GHz, and 4.5GHz, with good inter-band isolation. The chip was fabricated in a 90nm CMOS technology, and was measured to consume only 2.8µW of leakage power and 2.9µW at 100Kbps of dynamic power. The data-rate can be scaled up to 5Mbps at 29pJ/pulse, while still staying compliant with FCC-mask even with non-random pulsing. The output voltage swing was measured to be ~450-500mV across a 50& load. The total power consumption of ~6µW at 100Kbps is an order of magnitude better than that of state-of-the-art designs, i.e. ~100µW, operating at same pulse rate.

Optical interconnects are touted as the solution to the performance bottleneck of future interconnects in scaled technology nodes. Though significant strides have been made in realizing silicon photonic devices that can give high performance in controlled lab environments, there still exist technical challenges preventing dense integration and reliability in widely varying conditions. This paper examines such problems while suggesting possible solution space and proposing some alternatives. We also calculate the actual power advantage that optical links will have compared to an electrical link while considering the thermal stabilization and other technological issues. We show that the ~4X power advantage that ideal on-chip global optical interconnects have been projected to have is reduced to null when the power required for thermal regulation of critical optical components alone are added into the calculations. We also discuss latency, spatial bandwidth, polarization and a host of other technological issues and reassess the benefits of dense on-chip optical interconnects for dense global routing.

In this paper, we present the design of an ultra-low power impulse radio for an ad-hoc sensor network. This radio is designed to meet the 802.15.4a standard for UWB impulse radio while achieving low power operation by aggressively duty cycling both the transmitter and receiver with nearly the same "on-time". The key advance that enables aggressive receiver duty cycling is a new approach to establishing a robust, low jitter global network clock using a pulse coupled oscillator (PCO) algorithm. In this paper we describe how PCO based synchronization is used to design a radio transceiver capable of balanced two way communication and ad-hoc networking for under 30 uW average power in continuous operation.

In this paper we demonstrate the first 3-node synchronization of on-chip CMOS impulse radios. The synchronization scheme presented here is fast, scalable, low jitter and facilitates aggressive duty-cycling. We show experimentally that in steady state, the nodes are synchronized with cycle-to-cycle jitter of 1% of the period.

In this paper, we present a high speed ring oscillator compensated for process, as well as temperature variation. No post-fabrication efforts or external clock reference is required to implement our process compensation scheme. By adding a novel control loop to the ring oscillator and leveraging a low process variation current source, we are able to reduce the typical variation from 10.2% to 2.7% for a 3-GHz three stage inverter chain ring oscillator. The compensation scheme developed in the paper is not limited to applications in ring oscillators, but can be used in all types of VCO designs.

An optical receiver designed and fabricated in 0.25μm ultra-thin silicon (UTSi) on sapphire technology is flip-chip integrated with p-i-n photodiodes. The receiver includes a transimpedance amplifier (TIA), limiting amplifiers (LA), and an output buffer. The power consumption of the TIA and limiting amplifiers is 67.3 mW. The receiver is shown operating with a gain of 57 dBΩ at a bit rate of 10 Gb/s. The measured sensitivity is −1.7 dBm for a bit error rate of 10−9. This is the first 0.25μm CMOS TIA and LA codesign that operates optically at 10 Gb/s.

In this paper, we present a technique for low-power and low phase noise phase-locked loop designs. This technique introduces a key parameter, PNUP (Phase Noise per Unit Power), to all of the building blocks of a PLL that correlates all the blocks in terms of power and phase noise. By correlating all the independent PLL blocks together, sophisticated PLL design and optimization can be significantly simplified. We demonstrate a 6.8 GHz Frequency synthesizer design in 0.25um SOI process achieving −108dBc/Hz phase noise at 100 KHz offset with only 32.75 mW power consumption.

In this paper, we present a transimpedance amplifier (TIA) based on common-source feedback (CSFB) for use in a hybrid electronic-photonic microwave channelizer. The topology demonstrates improved linearity over conventional techniques, while maintaining comparable gain, bandwidth, and noise. This approach is implemented, fabricated, and tested in 180 nm CMOS. Performance metrics demonstrated include a transimpedance gain of 64 dBOmega, 2GHz bandwidth, input referred noise current of 4.2 pA/Hz1/2, and 5.8 dBm IP3. The circuit shows 124dBHz2/3of spurious-free dynamic range.

We investigate an addition-based current source that reduces the impact of process variation and device mismatch without post-fabrication efforts. By optimizing the transistor size and taking the advantage of the nonlinearity associated with real resistors in 90 nm CMOS technology, we are able to achieve significant performance improvement. Simulation based on the proposed circuit topology shows more than 67% reduction in the current variation of an equally sized single transistor current source.

In this paper, we present a transimpedance amplifier (TIA) for analog optical communication based on common-emitter feedback (CEFB). CEFB is compared to traditional resistive feedback (RFB) in four metrics: gain, bandwidth, noise and linearity. In simulation, CEFB shows a 15% improvement in gain-bandwidth product and a 2dB reduction in noise over RFB. When followed by a common-emitter gain stage, CEFB shows vast improvement in linearity over RFB, 24dB higher IP3 and 57dB higher IP2. This large advantage in linearity makes CEFB especially well suited to analog applications, such as analog optical receivers

In this paper we present our work on variation-tolerant current source design. The three-transistor-plus-resistor circuit we present, offers more than 2times reduction in standard deviation of the output current at reduced circuit complexity (in a 0.18mum technology). Moreover, our circuit can be used to mirror a reference current at various locations on the die without incurring mismatches due to process variations while requiring minimum voltage headroom and layout area. The circuit topology itself is derived from a formal methodology presented here

We present a hybrid opto-electronic system capable of improving the performance of on-chip electrical fanout architectures. Our opto-electronic system employs a layer of optical fanout and utilizes the electrical isolation between the receiving nodes. Through our proof-of-concept links, we show a 15% latency reduction for links as short as 200mum and 50% reduction at 2mm

With the increasing demand for interconnection bandwidth, there is a tremendous interest in low cost optoelectronic integration for high speed interconnects. We present an important step towards this end through our design of a fully integrated opto-electronic detector-receiver circuit. We believe our low voltage supply opto-electronic circuit is the first to be completely integrated in a silicon-based commercial logic process. We obtain operation at 250MHz in 0.25mum technology with a power consumption of 4mW

Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the development of on-chip optical interconnects. In this paper, we investigate the integration of CMOS-compatible optical technology to on-chip cache-coherent buses in future CMPs. While not exhaustive, our investigation yields a hierarchical opto-electrical system that exploits the advantages of optical technology while abiding by projected limitations. Our evaluation shows that, for the applications considered, compared to an aggressive all-electrical bus of similar power and area, significant performance improvements can be achieved using an opto-electrical bus. This performance improvement is largely dependent on the application's bandwidth demand and on the number of implemented wavelengths per optical waveguide. We also present a number of critical areas for future work that we discover in the course of our research

We describe the implementation of one channel of an optoelectronic orientation enhancement algorithm based on a neurally inspired algorithm. An 8/spl times/8 VCSEL (Vertical Cavity Surface Emitting Laser) array, hybridized to CMOS driver circuits, transmits a contrast-enhanced image that would be computed in the early stages of visual processing. A diffractive optical element (DOE) generates a projective field which reinforces pixels of a preferred orientation. A CMOS receiver integrates correlated pulses to produce high output in frequently activated areas. Data from a one channel system shows orientation enhancement.