Neuromorphic TinyML (vTinyML) aims at solving problems in machine perception and intelligence at the edge that necessitate low latency processing, using low resource processors that have neuromorphic event-based sensory interfaces and neuromorphic accelerators. In this paper, we report on a neuromorphic TinyML architecture (vMCU) which can be leveraged to be deployed to process data from event-based sensors on the edge. The core of the system is a RISC-V CPU from SiFive which is used for algorithm development. The CPU interfaces with a set of communication and computation peripherals which are comprised most notably of an event-based physical interface which has a 256Kib FIFO, a programmable 47-bit time-stamping unit and an embedded Compute in Memory (CiM) associative processor employing charge based processing and a pseudo-DRAM cell primitive. The vMCU SOC was fabricated in 65nm CMOS, has a die size of$7\text{mm}\times 4\text{mm}$, runs at 100MHz and has a maximum event throughput at its physical interface of 17Meps. Binary and integer operations on long bit vectors using the CiM accelerator capabilities take a few fJ per Op. vMCU capability consumes 30mW and is demonstrated in various tasks for embedded applications, including character recognition from a DAVIS240C event-based camera.

Neuromorphic processing architectures seek to emulate the functionality of the brain by realizing parallel, efficient, event-based processing which can be directly applied to solve many of the pressing problems within artificial intelligence and big data. However, implementation of these systems leads to slow response times, high power dissipation, or incoherent output. In this paper, an analog cellular neural network processing element is demonstrated to perform asynchronous spatiotemporal filtering operations in an area and power efficient manner. It utilizes a pair of analog memories to encode spike timings and perform event-based bandpass temporal processing. Information from the local clique of temporal filters is leveraged by a parallel, spatial processor which maps CNN arithmetic to the current-domain for compact computation. Preliminary circuit verification demonstrated the ability of the element to perform spatiotemporal filtering operations with latencies less than$1.8\mu\mathrm{s}$while only consuming 1.6pJ/spike.

Event-based vision cameras emulate the functionality of mamalian retina and promise to be a low-latency, energy efficient sensory front-end for machine perception. Despite the large-scale effort to deploy these sensors in a variety of scenarios, a proportionally small amount of effort has been devoted to the design and analysis of embedded architectures that process address events adjacent to the sensor. In this paper, a neuromorphic signal processing pipeline is reported which sparsifies the event stream thereby reducing energy consumption, increasing the signal-to-noise ratio, and improving downstream algorithm performance. It is integrated within a system-on-chip platform that will allow for the prototyping of different standards compliant, hardware modules within a embedded processing framework. We report two such modules which provides adaptive throughput management, spatiotemporal filtering, and programmable feature extraction.

Neuromorphic cameras that offer low latency and dynamic scene sensing are emerging as a viable technology for energy-aware embedded perceptual systems. In this paper we report on neuromorphic architecture and algorithm exploration for an event-based accelerator for neuromorphic cameras. The system includes a RISC-V CPU and associated peripherals that capture and process event-based visual data coming from a neuromorphic dynamic vision sensor. Mapped into a reconfigurable computing platform (FPGA), we demonstrate a set of event-based visual processing tasks including noise filtering, corner detection, and object tracking.

The SpiNNaker is a parallel neuromorphic hardware architecture that enables a wide variety of computations to be performed in a distributed, event-based manner. The authors have previously shown large speedups for performing MCMC inference using spiking neurons on the SpiNNaker as well as the Parallella, an open-source parallel computing device. Both architectures provide platforms for performing innovative low-power computations, and there are other massively parallel chip multiprocessor platforms arriving in the future. This paper explores a complexity analysis for the algorithms in the automated framework developed to take a binary Bayesian network the whole way from reading in its text file description and transforming the network for parallel MCMC sampling to performing sampling on the SpiNNaker. Although it is focused on the SpiNNaker, many of these principles apply when using other neuromorphic chip multiprocessors, as this algorithmic flow has already been used with the Parallella after some modifications.

In this paper we present a clock tree network that is inspired by the shape of an inverted cone. Conical sections are created in the inverted cone, and each of these resulting rings is considered to be one of the many nets in a Fishbone clock tree. When a ring is excited at uniform intervals from the ring below, the symmetry in the circular characteristics of the wire will make the effect of reflections be exactly the same along any place in the wire. The proposed clock tree named Conical-Fishbone clock tree allows ultra-low clock skew while offering the modularity to support a hierarchical design using standard CAD flows. The Conical-Fishbone tree network is employed in the L1- NOC, the L2-NOC and the DDR DRAM PHY of the core (17.47 mm X 14.13 mm) “chiplet” in the 2.5D nano-Abacus SOC currently being fabricated in the Global Foundries 55nm CMOS technology.

In this work, a mixed-signal architecture, inspired from the widely-popular successive approximation analog-to-digital converter, is presented as an energy-efficient alternative to conventional digital signal processors for fixed-point arithmetic. Using a capacitor array, this architecture computes multiply-add operations as charge at the thermal noise limits. Then, using this same array along with a comparator and a successive approximation register (SAR), this charge is efficiently decoded into a digital value using a binary search. This architecture was designed in a 16nm FinFET process, and is capable of computing 8-bit multiply-add operations averagely at 6.85fJ with an efficiency of 146TOPs/W. Compared to a conventional digital implementation performing the same operation in the same process, the proposed design used 37% less energy.

In this work, a charge-based energy-efficient architecture for computing vector-vector multiplications (VVM) is presented. Using an array of capacitors, the inner product of vectors is quantitatively computed as the total charge injected onto the array. By scaling the capacitance to the thermal noise (kTC) limit, this computation can be done efficiently on the order of a few picoJoules (pJ). Furthermore, this charge is then converted into a pulse-density modulated binary output over time through a first-order delta-sigma converter, giving a trade-off of output precision and computation time. This design was fabricated in a 65nm CMOS process and measured to compute 6-bit MACs with a throughput of 350KOPs, and an overall efficiency of 14.6GOP/W at 5-bit precision. Moreover, the computation done on the array in the analog domain, has an efficiency of 284.4GOP/W.

We discuss the architecture, implementation and testing of a neuromorphic Cellular Neural Network (CNN) processor for intelligent IoT devices. The processor is based on a simplicial piecewise linear CNN architecture that allows implementation of linear and nolinear CNNs. A linear array of 64 processing element (PE) with column-shared computation resources, tightly coupled to two data memory caches was synthesized and fabricated in a 55nm CMOS technology using custom layout libraries. The fabricated chip achieves an overall performance of 2.95 TOPS/W with dynamic energy dissipation efficiency of 86.4fJ per OP at V=500mV. The processor can implement different types of processing on 2D data arrays, such as gray-scale morphology, gradient flow, median filters, and approximate Gaussian filters, among others.

We report on the implementation of a path planning algorithm on the TrueNorth neurosynaptic system. Our implementation exploits processing in the temporal domain within the architectural constraints of the TrueNorth chip to deduce the optimal path. The optimal path is computed on the TrueNorth chip for grid maps with dimensions as large as 173 × 168 nodes consuming 70.0mW at an operating voltage of 0.8V.

The interest for more digital functionality in the readout circuits for imagers is growing rapidly. Similarly, there are advantages to having the pixel pitch smaller from visible to long wave IR. The front end is the dominant source of electronic noise for an in-pixel digital design. Limiting the real estate considerably would force the design to smaller feature size, which may worsen the random telegraph signal or noise (RTS/RTN) that will likely be the dominate source for noise for these imagers. This paper summarizes initial results for RTN sensitivities at room temperature to various device types, geometries, and flux rates, evaluated on a digital pixel on 65- and 55-nm CMOS processes.

Summary form only given. The IBM TrueNorth (TN) Neurosynaptic System, is a chip multi processor with a tightly coupled processor/memory architecture, that results in energy efficient neurocomputing and it is a significant milestone to over 30 years of neuromorphic engineering! It comprises of 4096 cores each core with 65K of local memory (6T SRAM)-synapses- and 256 arithmetic logic units - neurons-that operate on a unary number representation and compute by counting up to a maximum of 19 bits. The cores are event-driven using custom asynchronous and synchronous logic, and they are globally connected through an asynchronous packet switched mesh network on chip (NOC). The chip development board, includes a Zyng Xilinx FPGA that does the housekeeping and provides support for standard communication support through an Ethernet UDP interface. The asynchronous Addressed Event Representation (AER) in the NOC is al so exposed to the user for connection to AER based peripherals through a packet with bundled data full duplex interface. The unary data values represented on the system buses can take on a wide variety of spatial and temporal encoding schemes. Pulse density coding (the number of events Ne represents a number N), thermometer coding, time-slot encoding, and stochastic encoding are examples. Additional low level interfaces are available for communicating directly with the TrueNorth chip to aid programming and parameter setting. A hierarchical, compositional programming language, Corelet, is available to aid the development of TN applications. IBM provides support and a development system as well as “Compass” a scalable simulator. The software environment runs under standard Linux installations (Red Hat, CentOS and Ubuntu) and has standard interfaces to Matlab and to Caffe that is employed to train deep neural network models. The TN architecture can be interfaced using native AER to a number of bio-inspired sensory devices developed over many years of neuromorphic engineering (silicon retinas and silicon cochleas). In addition the architecture is well suited for implementing deep neural networks with many applications in computer vision, speech recognition and language processing. In a sensory information processing system architecture one desires both pattern processing in space and time to extract features in symbolic sub-spaces as well as natural language processing to provide contextual and semantic information in the form of priors. In this paper we discuss results from ongoing experimental work on real-time sensory information processing using the TN architecture in three different areas (i) spatial pattern processing -computer vision(ii) temporal pattern processing -speech processing and recognition(iii) natural language processing -word similarity-. A real-time demonstration will be done at ISCAS 2016 using the TN system and neuromorphic event based sensors for audition (silicon cochlea) and vision (silicon retina).

The design of a true Bernoulli Random Number Generator (RNG) source with a true probability p = 0.5 is a challenging problem. In this work, we present a novel design of a True RNG (TRNG) that achieves a true E(p(n)) = 0.5. The architecture is based on the perturbation of a Sigma-Delta modulator using random telegraph noise (RTN).

The ability to recognize the behavior of individuals is of great interest in the general field of safety (e.g. building security, crowd control, transport analysis, independent living for the elderly). Here we report a new real-time acoustic system for human action and behavior recognition that integrates passive audio and active micro-Doppler sonar signatures over multiple time scales. The system architecture is based on a six-layer convolutional neural network, trained and evaluated using a dataset of 10 subjects performing seven different behaviors. Probabilistic combination of system output through time for each modality separately yields 94% (passive audio) and 91% (micro-Doppler sonar) correct behavior classification; probabilistic multimodal integration increases classification performance to 98%. This study supports the efficacy of micro-Doppler sonar systems in characterizing human actions, which can then be efficiently classified using ConvNets. It also demonstrates that the integration of multiple sources of acoustic information can significantly improve the system's performance.

We present an FPGA-based approach for estimating the delayed synaptic weights of spiking neural networks. Our approach makes explicit use of the fact that reverse engineering of a spiking neural network can be cast as a linear programming problem, whereby the objective function is based on the network spiking activity. The solution is obtained by employing the widely used simplex algorithm. Numerical results on a Xilinx Spartan 3 FPGA board show that the present approach can be used to reproduce a desired output from the observed network spiking activity.

Beginning with Amdahl's law, we derive a general objective function that links parallel processing performance gains at the system level, to energy and delay in the subsystem microarchitecture structures. The objective function employs parameterized models of computation and communication to represent the characteristics of processors, memories, and communications networks. The interaction of the latter microarchitectural elements defines global system performance in terms of energy-delay cost. Following the derivation, we demonstrate its utility by applying it to the problem of Chip Multiprocessor (CMP) architecture exploration. Given a set of application and architectural parameters, we solve for the optimal CMP architecture for six different architectural optimization examples. We find the parameters that minimize the total system cost, defined by the objective function under the area constraint of a single die. The analytical formulation presented in this paper is general and offers the foundation for the quantitative and rapid evaluation of computer architectures under different constraints including that of single die area.

We present a high-level analytical model for chip-multiprocessors (CMPs) that encompasses processors, memory, and communication in an area-constrained, global optimization process. Applying this analytical model to the design of a symmetric CMP for speech recognition, we demonstrate a methodology for estimating model parameters prior to design exploration. Then we present an automated approach for finding the optimal high-level CMP architecture. The result is the ability to find the allocation of silicon resources for each architectural element that maximizes overall system performance. This balances the performance gains from parallelism, processor microarchitecture, and cache memory with the energy-delay costs of computation and communication.

In this work, we utilize a CMOS active pixel sensor in a fluorescence imaging setup. The ability to sense small light intensity changes on top of a large baseline with spatial resolution at the subcellular scale is required in fluorescence imaging. The CMOS imager presented in [1] is perfect for this application with the ability to resolve fine features coupled with high dynamic range. By using a custom imager with a relay lens we are able to realize a dramatic decrease in device size, cost and complexity of the whole system.

Spike Timing Dependant Plasticity (STDP) is a biologically-based Hebbian reinforcement learning rule for the unsupervised training of synaptic weights in spiking neural networks. We present a low complexity synthetic implementation of STDP using basic combinational digital logic gates. This approach attains comparable results to more complex implementations while utilizing only a fraction of the area. We use our STDP approach to replicate the experimental results of a balanced excitation experiment.

We present a quantitative analysis of the limits of the time-multiplexed Address Event Representation (AER) bus for on-chip connectivity of silicon neuron arrays. In particular, we evaluate its potential to support high density and low power neural arrays operating in the subthreshold regime. Our analysis shows that due to low clock frequencies when operating in the subthreshold regime, the traditional single AER bus does not scale to large neural arrays. We find that a switched mesh network improves scalability, however, a crosspoint architecture overcomes the bandwidth limitations altogether. By trading off area for improved performance, it increases the number of neurons that can be supported in a single chip neural array.

We report the design and test of a 32×32 array of single photon avalanche diodes. The imager uses a delay-insensitive address-event link for the readout. The chip is fabricated in 0.18μm CMOS in an area of 1.886×1.866 of which 4% is occupied by the readout circuits.

We present a micropower QCIF image sensor fabricated in 0.18μm CMOS technology. Low-power operation is achieved through a system-on-chip design methodology optimizing from device to architecture, yielding a 3-pin autonomous system. Supply voltage and reference are scaled down to 1.0V and 400mV, respectively. Compared to previous work, this imager consumes 42% less energy per pixel.

In this paper, we report the first silicon-on-insulator (SOI) integration technique for organic field effect transistor (OFET) based circuits. Proposed design flow relies on only basic micro-fabrication processes such as photolithography and physical vapor deposition. This novel fabrication technique allows patterning of conductive silicon gate islands on the subtrate and eases the via and interconnect patterning and deposition for a bottom-gate OFET configuration. We fabricated pand n-type transistors, and proof of concept OFET-based complementary circuits such as inverter and NAND-gate. Fabricated CMOS inverters have full rail-to-rail swing, very high gain (up to 58.3 at 60V, and 18.1 at 20V supply voltages), and outstanding noise margins of around 21V symmetric for NMhigh and NMlow at 60V supply voltage.

In this paper, we report on an 8-bit auto-calibrating successive-approximation-register (SAR) analog-to-digital converter (ADC) for ultra-low power image sensors. The fabricated design includes an on-chip bandgap voltage reference and a tunable clock generator in addition to the SAR ADC core circuitry. Aside from two power pins, the design uses only one extra pin to output the digitized samples serially. Power consumption for the design is 21μW at 0.8V supply voltage, and it is 32μW including ancillary circuits. The sampling rate varies from 370kS/s to 1.6MS/s depending on the supply voltage. The design occupies an area of 0.2mm2in a 0.18μm CMOS process, of which 0.073mm2is for the SAR ADC core.

Accelerometers are common on many devices, including those required for text-entry. We investigate how to enter text with devices that are solely enabled with accelerometers. The challenge of text-entry with such devices can be overcome by the careful investigation of the human limitations in gestural movements with accelerometers. Preliminary studies provide insight into two potential text-entry designs that purely use accelerometers for gesture recognition. In two experiments, we evaluate the effectiveness of each of the text-entry designs. The first experiment involves novice users over a 45 minute period while the second investigates the possible performance increases over a four day period. Our results reveal that a matrix-based text-entry system with a small set of simple gestures is the most efficient (5.4wpm) and subjectively preferred by participants.

This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broadcast the parameters stored in the memory, and in addition, row and column operations can be serialized. Based on a 90nm technology process, the different options will be analyzed and compared using simulations.

Heteroscedastic Linear Discriminant Analysis (HLDA) was introduced in [1] as an extension of Linear Discriminant Analysis to the case where the class-conditional distributions have unequal covariances. The HLDA transform is computed such that the likelihood of the training (labeled) data is maximized, under the constraint that the projected distributions are orthogonal to a nuisance space that does not offer any discrimination. In this paper we consider the case of semi-supervised learning, where a large amount of unlabeled data is also available. We derive update equations for the parameters of the projected distributions, which are estimated jointly with the HLDA transform, and we empirically compare it with the case where no unlabeled data are available. Experimental results with synthetic data and real data from a vowel recognition task show that, in most cases, semi-supervised HLDA results in improved performance over HLDA. Index Terms: heteroscedastic linear discriminant analysis, nuisance space, semi-supervised learning. 1.

In this paper we present the circuits and simulation results for a silicon neuron which is based on a modified version of the Mihalas-Niebur neural model [1]. This silicon neuron produces 15 of the 20 known neural spiking and bursting behaviors. It has low complexity and reliable matching and can thus be easily integrated into more complex neuromorphic systems. Implemented in a 0.15um 1.5V CMOS process, each neuron consumes about 7.5nW of power at 1kHz and occupies an area of 70um by 70um.

A low-power tunable transmitter for ultra-wide band (UWB) radio was designed and fabricated. The design is based on a ring oscillator VCO, to produce short pulses. Both the pulse duration and frequency is controllable by two voltage biases. The transmitter can be used in both pulse-amplitude modulation (PAM) and pulse-position modulation (PPM). The circuit was fabricated on a 0.5mum silicon-on-sapphire CMOS process, and has been experimentally characterized with a transmitter and receiver module. The UWB transmitter produces monocycle pulses of 800 ps duration. The power consumption is 75muW when the pulse frequency is 3 MHz. The core pulse generator occupies 0.0091mm2of silicon area.

As people live longer in the new millennium, it becomes a necessity to develop affordable technologies to improve the quality of life. This paper provides an overview of such techniques in drug delivery and clinical care, namely: (i) health care from organ functions to the cell behaviors; (ii) the development of implantable biosensors and instrumentation; (iii) the process and visualization systems; and (iv) nanotechnology for drug delivery. The goal is to stimulate cross-disciplinary research in the circuits and systems society aimed towards optimal clinical care and personalized therapeutic intervention.

We report on the design fabrication and testing of a wide range transconductance amplifier fabricated in the 0.18μm MIT Lincoln Labs 3D SOI-CMOS process. The amplifier is designed to operate in subthreshold and employs self-biased cascode transistors to minimize the bias lines transversing the 3 tiers in the technology.

While there has been a growing emergence of circuit designs for the life sciences, there is an important issue that remains largely unaddressed. Although advanced design techniques have been applied to circuits capable of measuring very small amplitude, high signal to noise ratio signals, with many custom circuit designs for these applications (Harrison and Charles, 2003), there remains a proverbial elephant in the room. The systems used to measure these signals provide no means of accurate thermal control. This is especially surprising considering the huge dependance in the behavior of both biological and electrical systems upon temperature. In fact, the vast majority of electrical cellular assays are performed on dying cells! We present a systematic method of incorporating a high-accuracy, closed-loop thermal feedback system into hybrid systems for the life sciences. We introduce a thermal stabilization chip containing a heater and PTAT temperature sensor including the heater control circuit. We then provide a description of the PID control loop. This is followed by both computational data via finite element analysis and empirical data that assesses the thermal performance of the chip. Finally, we demonstrate the advantages of the system with comparative results of cell culture.

We present hybrid silicon/silicone microsystem for closed-loop temperature control with applications in the life sciences. The system architecture includes an integrated CMOS die for localized thermal cycling and a disposable PDMS microfluidic structure for aseptic fluidic manipulation. Chip design, experimental results and finite element analysis are presented. This work is based on criteria for a clinical diagnostics system comprised of disposable microfluidics for use in tandem with CMOS electronics.

Analog neural signals must be converted into spike trains for transmission over electrically leaky axons. This spike encoding and subsequent decoding leads to distortion. We quantify this distortion by deriving approximate expressions for the mean square error between the inputs and outputs of a spiking link. We use integrate-and-fire and Poisson encoders to convert naturalistic stimuli into spike trains and spike count and inter-spike interval decoders to generate reconstructions of the stimulus. The distortion expressions enable us to compare these spike coding schemes over a large parameter space. We verify that the integrate-and-fire encoder is more effective than the Poisson encoder. The disparity between the two encoders diminishes as the stimulus coefficient of variation (CV) increases, at which point, the variability attributed to the stimulus overwhelms the variability attributed to Poisson statistics. When the stimulus CV is small, the interspike interval decoder is superior, as the distortion resulting from spike count decoding is dominated by a term that is attributed to the discrete nature of the spike count. In this regime, additive noise has a greater impact on the interspike interval decoder than the spike count decoder. When the stimulus CV is large, the average signal excursion is much larger than the quantization step size, and spike count decoding is superior.

We report on a system designed for the magnetic control of nanoparticles and nanorods. This is accomplished by arrays of current-carrying wires (electromagnets) and the associated control circuitry onto a single chip. The chip serves both as the source of localized programmable magnetic fields and the substrate on which the nanostructures rest. Sensing can be similarly performed through on-chip electromagnetic or optical measurements. As proof of concept, we utilize the catalysis of hydrogen-peroxide decomposition by platinum to propel hybrid nanorods through a fluid medium, and demonstrate basic control of nanoparticles in response to the applied currents (electromagnetic fields).

We report on a custom designed system for the deposition and characterization of polypyrrole bilayer actuators. Unlike conventional commercial electrochemical cells and potentiostats, the system described in this paper has specifications commensurate to its application and thus can be readily implemented using off the shelf electronic components at relatively low cost. Deposition rates and actuation are computer controlled through a standard data acquisition interface card with a program written in Matlab. We also discuss the design of the masks that are employed to fabricate the polypyrrole structures. This is accomplished through silicon compilation using the CAD software LEDIT (1999) from Tanner Research. We have implemented a selection of parameterized routines in the LEDIT script language LComp that greatly reduces design turnaround time.

We discuss the design, fabrication and testing of a hybrid microsystem for stand-alone cell culture and incubation. The micro-incubator is engineered through the integration of silicon CMOS die for the heater and temperature sensor, with multilayer silicone PDMS (polydimethylsiloxane) structures namely, fluidic channels and a 4 mm diameter, 30muL, culture well. A 25 micron thick PDMS membrane covers the top of the culture well, acting as barrier to contaminants while allowing the cells to exchange gases with the ambient environment. The packaging for the microsystem includes a flexible polyimide electronic ribbon cable and four fluidic ports that provide external interfaces to electrical energy, closed loop sensing and electronic control as well as solid and liquid supplies. The complete structure has a size of (2.5 times 2.5 times 0.6 cm3). We have employed the device to successfully culture BHK-21 cells autonomously over a sixty hour period in ambient environment

We fabricated a 3D-integrated multi-chip sensor and actuator and demonstrated the ability of communication with a floating die and no galvanic connection. The prototype was fabricated on a conventional 0.5mum silicon-on-sapphire (SOS) process. We designed a heater and a temperature sensor module with digital output based on a bandgap voltage reference. We used capacitive coupling to provide both intra-die communication of the digital temperature readings and also energy-harvesting by means of a charge pump. The non-galvanically interconnected prototype is an enabling technology for three-dimensional VLSI fabrication, 3D CMOS, wafer stacking and packaging

We designed and fabricated a 4-channel digital isolation amplifier in a 0.5mum silicon-on-sapphire technology. The isolation device was fabricated on a single die, taking advantage of the isolative properties of the sapphire substrate. The individual isolation channels can operate in excess of 40Mbps using digital phase-shift-keying modulation. Modulation of the input signal is used to increase immunity to errors at low input data rates. The device can tolerate ground bounces of 1V/mus and isolate more than 800V. The device uses N+1 capacitors for TV channels as opposed to 2N of previous implementations, thus minimizing the coupling silicon area and increasing reliability. Typical applications are in harsh industrial environments, transportation, medical and life-critical systems

We present a system level architecture for a scalable, mixed-signal, asynchronous processor, aimed at cortical computations. The design has been implemented in MIT Lincoln Lab's three-tier SOI-CMOS 0.18mum digital process. The main circuits are distributed in the two tiers; an asynchronous address-event based read/write middle tier and an odd symmetric spatial filter (8 orientations) on the bottom tier. The top tier includes a photosensitive pixel array (64times64) to facilitate testing and characterization of the system. A highspeed 2-phase asynchronous chip-to-chip communication protocol is built-in to facilitate system scalability

This paper presents the architecture for a SIMD digital visual processor unit (VPU) that is based on the simplicial CNN (S-CNN) algorithm. The system is designed for three dimensional CMOS integration in the three tier MITLL 3D SOI-CMOS 0.18 mum technology. The architecture includes input/output sub-systems, in the third tier, arithmetic logic units (ALU) and register files on the third and second tiers and instruction cache memory and a timing state machine on the first tier. The partition of the architecture exploits its physical realization in three dimensional CMOS. Parallel optical data input through an array of photodetectors and analog interface circuits in the third tier facilitate testing and characterization

Three dimensional (3D) silicon on insulator (SOI)-CMOS technology offers opportunities for integration of truly complex neuromorphic systems that do not suffer from the limitations that hinder neuron-like local connectivity in 2D CMOS technologies. In this paper, we outline the rationale for morphing neural structures into 3D SOI-CMOS systems. We discuss design challenges for mixed signal neuromorphic circuits in single tier and 3D SOI-CMOS. We also report on a SOI-CMOS compatible photodetector with photosensitivity of 30,000 (A/W), which is the highest ever reported in the literature.

We report on dark current measurements from lateral, 100nm thick, PIN photodiodes fabricated in the Peregrine Semiconductor, silicon on sapphire (SOS) CMOS technology. We compare interdigitated photodiode geometries with edgeless structures that do not have active device regions adjacent to LOCOS. We also compare two methods for device design. One employs a polysilicon gate to block the implant in the intrinsic region of the device while the second utilizes a specific mask layer in the technology called an SDBlock mask. Our results suggests that the dark current is primarily a function of the junction width. Furthermore, polysilicon gate devices have lower dark currents than SDBlock structures. Finally, we perform noise measurements and extract flicker noise parameters for the two methods and find that polysilicon gate structures have greater levels of flicker noise than SDblock devices.

We discuss an imaging architecture for sensor network applications, that employs a 32 times 32 address-event representation (AER) imager. At the sensor level, pixels convert light intensity into a pulse density modulated stream of address events. Two different types of COTS wireless radio nodes are used, along with two separate approaches to wireless data transmission - one as a train of AER addresses, and the other as a histogram of the active pixels. Information transmitted in the limited-bandwidth network yields effective means for detection and partial recognition of the object even at very low bit rates, yielding a maximum experimental frame-rate of close to 6fps

We discuss the design of CMOS MEMS in a 3D SOI-CMOS technology. We present layout architectures, preliminary mechanics modeling using finite element analysis and release process flows. An accelerometer structure is used as the model system with electronics embedded into a suspended proof mass. A prototype chip is fabricated in the MIT Lincoln Laboratories that includes test structures and systems for both a capacitive sensed and interferometric sensed accelerometers

We report on the design of stacked standing wave detectors in a 3D SOI CMOS technology. The standing wave detector is the basic block needed to implement a die level CMOS interferometer to measure small displacements. The 3D CMOS process allows for standing wave detectors to be vertically stacked which provides directional information as well as displacement information from the interferometer. We discuss design considerations for the photodiodes and MOS amplifier

We present a low-power VLSI wake-up detector for a sensor network that uses acoustic signals to localize ground-based vehicles. The detection criterion is the degree of low-frequency periodicity in the acoustic signal, and the periodicity is computed from the “bumpiness” of the autocorrelation of a one-bit version of the signal. We then describe a CMOS ASIC that implements the periodicity estimation algorithm. The ASIC is fully functional and its core consumes 835 nanowatts. It was integrated into an acoustic enclosure and deployed in field tests with synthesized sounds and ground-based vehicles.

We present a CMOS integrated circuit (IC) for bearing estimation in the low-audio range that performs a correlation derivative approach in a 0.35-/spl mu/m technology. The IC calculates the bearing angle of a sound source with a mean variance of one degree in a 360/spl deg/ range using four microphones: one pair is used to produce the indication and the other to define the quadrant. An adaptive algorithm decides which pair to use depending on the direction of the incoming signal, in such a way to obtain the best estimate. The IC contains two blocks with 104 stages each. Every stage has a delay unit, a block to reduce the clock speed, and a 10-bit UP/DN counter. The IC measures 2 mm by 2.4 mm, and dissipates 600 /spl mu/W at 3.3 V and 200 kHz. It is purely digital and uses a one-bit quantization of the input signals.

We describe a low-power VLSI wake-up detector for use in an acoustic surveillance sensor network. The detection criterion is based on the degree of low-frequency periodicity in the acoustic signal. To this end, we have developed a periodicity estimation algorithm that maps particularly well to a low-power VLSI implementation. The time-domain algorithm is based on the "bumpiness" of the autocorrelation of one-bit version of the signal. We discuss the relationship of this algorithm to the maximum-likelihood estimator for periodicity. We then describe a full-custom CMOS ASIC that implements this algorithm. This ASIC is fully functional and its core consumes 835 nano-Watts. The ASIC was integrated into an acoustic enclosure and tested outdoors on synthesized sounds. This unit was also deployed in a three-node sensor network and tested on ground-based vehicles.

We examine channel access algorithms and circuits for intra and inter chip communication channels. Classical access techniques such as arbitration, scanning, ALOHA, and priority encoding are compared by assessing throughput, latency, and power consumption. Our results provide guidance in the design of bio-inspired networks of processors, for efficient transmission of information with limited power consumption and reduced latency.

We outline a theoretical framework to analyze information processing in biological sensory organs and in engineered microsystems. We employ the mathematical tools of communication theory and model natural or synthetic physical structures as microscale communication networks, studying them under physical constraints at two different levels of abstraction. At the functional level, we examine the operational and task specification, while at the physical level, we examine the material specification and realization. Both levels of abstraction are characterized by Shannon's channel capacity, as determined by the channel bandwidth, the signal power, and the noise power. The link between the functional level and the physical level of abstraction is established through models for transformations on the signal, physical constraints on the system, and noise that degrades the signal. As a specific example, we present a comparative study of information capacity (in bits per second) versus energy cost of information (in joules per bit) in a biological and in a silicon adaptive photoreceptor. The communication channel model for each of the two systems is a cascade of linear bandlimiting sections followed by additive noise. We model the filters and the noise from first principles whenever possible and phenomenologically otherwise. The parameters for the blowfly model are determined from biophysical data available in the literature, and the parameters of the silicon model are determined from our experimental data. This comparative study is a first step toward a fundamental and quantitative understanding of the tradeoffs between system performance and associated costs such as size, reliability, and energy requirements for natural and engineered sensory microsystems.

A neural architecture that implements a programmable 2D image filter has been presented. The architecture allows to implement any 2D filter F(p,q) decomposable into x-axis and y-axis components F(p,q) = H(p)V(q) such that the product can be approximated by a signed minimum. Positive and negative values of H(p) and V(q) can be programmed. The architecture requires an address even representation (AER) input. This allows to rotate the 2D convolution kernel any angle. Circuit simulation results of critical components were given. System-level behavioral simulations of a 128x128 array have been included which validate the proposed approach.

We describe the implementation of one channel of an optoelectronic orientation enhancement algorithm based on a neurally inspired algorithm. An 8/spl times/8 VCSEL (Vertical Cavity Surface Emitting Laser) array, hybridized to CMOS driver circuits, transmits a contrast-enhanced image that would be computed in the early stages of visual processing. A diffractive optical element (DOE) generates a projective field which reinforces pixels of a preferred orientation. A CMOS receiver integrates correlated pulses to produce high output in frequently activated areas. Data from a one channel system shows orientation enhancement.

We characterized photodetector mismatch in 2 /spl mu/m and 1.2 /spl mu/m CMOS processes. 32/spl times/32 element photodiode and phototransistor arrays were fabricated in each process, Light response measurements were made using a DC light source and neutral density filters. Dark currents were also measured and characterized. Our measurements reveal less than 2% mismatch for photodiodes over 4 orders of magnitude of intensity, and less than 5% mismatch for phototransistors. The oxide profile above the photodetector array is shown to be responsible for edge-effects.

We measure the matching characteristics of floating gate MOSFET devices. Arrays of ten FG PFET devices were fabricated on two different runs of the same process. Matching characteristics were measured: (1) direct from the foundry, (2) after Fowler-Nordheim tunneling, (3) after self-limiting PFET hot-electron injection, and (4) after UV exposure. We also found significant threshold voltage drift in long-term memory tests.

We have designed a CMOS integrated circuit array to perform analog image processing tasks on-chip. The array is capable of real-time spatial and temporal filtering, as well as edge and/or motion enhancement effects. Each cell in the array includes bump pads for bonding the array to HgCdTe LWIR detector arrays, as well as visible light photo-transistors for testing the chip's functionality prior to hybridization.

An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach is valid for any 2D filtering operation as long as the convolutional kernel F(p,q) is decomposable into an x-axis and a y-axis component, i.e. F(p,q)=H(p)V(q), for some rotated coordinate system [p,q]. If it is possible to find a coordinate system [p,q], rotated with respect to the absolute coordinate system a certain angle, for which the above decomposition is possible, then the proposed architecture is able to perform the filtering operation for any angle we would like the kernel to be rotated. This is achieved by taking advantage of the AER and manipulating the addresses in real time. The proposed architecture, however, requires one approximation: the product operation between the horizontal component H(p) and vertical component V(q) should be able to be approximated by a signed minimum operation without significant performance degradation. It is shown that for edge-extraction applications this filter does not produce performance degradation. The proposed architecture is intended to be used in a complete vision system known as the Boundary-Contour-System and Feature-Contour-System Vision Model, proposed by Grossberg and collaborators. The present paper proposes the architecture, provides a circuit implementation using MOS transistors operated in weak inversion, and shows behavioral simulation results at the system level operation and electrical simulation and experimental results at the circuit level operation of some critical subcircuits.

Photoreceptors measure and communicate information about visual stimuli to other neurons. In this process, the visual signal is converted between many different physical states. We present a communication channel model that describes transmission and degradation of the visual signal in the blowfly photoreceptor cell. The model is a cascade of linear systems and noise sources; these elements are derived from fundamental principles when possible, and parameters of the model are estimated from physiological data. We compute capacity and bit-energy using the model. Our results indicate that photon shot noise and channel noise are the dominant noise sources in blowfly phototransduction.

Our goal is to relate the structural and biophysical characteristics of blowfly visual neurons to their functional information processing aspects. Starting with the biophysics of information flow in the the early visual system of the blowfly, we construct a communication channel model that describes transmission and degradation of the visual signal in the photoreceptor and large monopolar cell. The channel model is a cascade of linear bandlimiting sections each followed by additive noise. Each section is modelled from first principles when possible, and parameters are determined from biophysical data available in the literature. The information capacity computed using our model compares favorably with empirical information rates derived from physiological experiments.

Polarization vision is prevalent among insects, and offers visual capabilities that contribute to object discrimination and homing tasks. We present a CMOS imager that is capable of extracting polarization contrast in a scene. A similar visual modality has been seen in Octopus. The polarimetric vector is a more general descriptor of light than intensity information alone, and it contains physical information about the imaged objects in a scene that traditional intensity based sensors ignore. Polarimeters-devices that measure polarization-are used to extract physical features from an image such as specularities, occluding contours, and material properties. Polarization information is used to perform difficult tasks such as image segmentation and surface reconstruction, object orientation, material classification, atmospheric and solar analysis. The polarization contrast retina is a CMOS sensor/imager that uses a birefringent crystal micropolarizer mounted on the focal plane to sense two orthogonal directions of linear polarization. The CMOS imager uses analog translinear circuitry to compute, in real-time on the focal-plane, polarization contrast: a measure of the orientation and degree of linear polarization in an imaged scene.

We present the design of neuromorphic CMOS integrated circuit imager arrays that performs analog computation on-chip prior to conventional off-chip digitizing. These imagers are capable of performing real-time nonuniformity correction using Scribner's scene-based nonuniformity correction (SBNUC) algorithm and can therefore learn to cancel the offsets of the sensor array dynamically.

We present the theory for heteroscedastic discriminant analysis (HDA), a model-based generalization of linear discriminant analysis (LDA) derived in the maximum-likelihood framework to handle heteroscedastic-unequal variance-classifier models. We show how to estimate the heteroscedastic Gaussian model parameters jointly with the dimensionality reducing transform, using the EM algorithm. In doing so, we alleviate the need for an a priori ad hoc class assignment. We apply the theoretical results to the problem of speech recognition and observe word-error reduction in systems that employed both diagonal and full covariance heteroscedastic Gaussian models tested on the TI-DIGITS database.

We have developed a low power analog VLSI chip for real time signal processing motivated by the principles of the human auditory system. An analog cochlear filter bank (which is implemented on the chip) decomposes the input audio signal into several frequency bands that have almost equal bandwidth on a log scale. This step is thus similar to computing the wavelet transform. The chip then computes signal energies and zero crossing time intervals of frequency components in a cochlear filter bank. The chip is intended to work as a front-end of a speech recognition system. We include experimental results on a VLSI implementation of the auditory front-end. We present speech recognition results on the TI-DIGITS database obtained from computer simulations which model the functionality of the feature extraction VLSI hardware. We use hidden Markov models (HMM) in combination with linear discriminant analysis (LDA) for the recognizer design.

We present a fully automated system which unites CCD camera technology with liquid crystal technology to create a polarization camera capable of sensing the partial linear polarization of reflected light from objects at pixel resolution. As polarization sensing not only measures intensity but also additional physical parameters of light, it can therefore provide a richer set of descriptive physical constraints for the understanding of images. Previously it has been shown that polarization cues can be used to perform dielectric/metal material identification, specular and diffuse reflection component analysis, as well as complex image segmentations that would be significantly more complicated or even infeasible using intensity and color alone. Such analysis has so far been done with a linear polarizer mechanically rotated in front of a CCD camera. The full automation of resolving polarization components using liquid crystals not only affords an elegant application, but significantly speeds up the sensing of polarization components and reduces the amount of optical distortion present in the wobbling of a mechanically rotating polarizer. In our system two twisted nematic liquid crystals are placed in front of a fixed linear polarizer placed in front of a CCD camera. The application of a series of electrical pulses to the liquid crystals in synchronization with the CCD camera video frame rate produces a controlled sequence of polarization component images that are stored and processed on Datacube boards. We present a scheme for mapping a partial linear polarization state measured at a pixel into hue, saturation and intensity producing a representation for a partial linear polarization image. Our polarization camera currently senses partial linear polarization and outputs such a color representation image at 5 Hz. The unique vision understanding capabilities of our polarization camera system are demonstrated with experimental results showing polarization-based dielectric/metal material classification, specular reflection and occluding contour segmentations in a fairly complex scene, and surface orientation constraints.

Recently, polarization vision has been shown to simplify some important image understanding tasks that can be more difficult to perform with intensity vision alone. This, together with the more general capabilities of polarization vision for image understanding, motivates the building of camera sensors that automatically sense and process polarization information. Described in this paper are a variety of designs for polarization camera sensors that have been built to automatically sense partial linearly polarized light, and computationally process this sensed polarization information at pixel resolution to produce a visualization of reflected polarization from a scene, and/or a visualization of physical information in a scene directly related to sensed polarization. The three designs for polarization camera sensors presented utilize (i) serial acquisition of polarization components using liquid crystals, (ii) parallel acquisition of polarization components using a stereo pair of cameras and a polarizing beamsplitter, and (iii) a prototype photosensing chip with three scanlines, each scanline coated with a particular orientation of polarizing material. As the sensory input to polarization camera sensors subsumes that of standard intensity cameras, they can potentially significantly expand the application potential of computer vision. A number of images taken with polarization cameras are presented, showing potential applications to image understanding, object recognition, circuit board inspection and marine biology.

We consider the problem of automatic object recognition by small, light-weight, low power, hardware systems. We abstract from biological function and organization and propose hardware architectures and a design methodology to engineer such hardware. Robust, miniature, and energetically efficient VLSI systems for AOR can ultimately be achieved by following a path which optimizes the design at and between all levels of system integration, i.e., from devices and circuit techniques all the way to algorithms and architectural level considerations. By way of example, we discuss two experimental systems for image acquisition and preprocessing fabricated in standard CMOS processes. The first one is a large scale analog system, a contrast sensitive silicon retina, with over 590, 000 transistors operating in subthreshold CMOS. The second system is a mixed analog-digital system for image acquisition and tracking compensation that incorporates a contrast sensitive silicon retina in the image sensing area.

We propose a multi-chip organization for Winner-Takes-All associative memory (WAM) systems for processing sensory information such as speech. Using mixed analog/digital circuit techniques, this hardware solution has great advantages, such as portable size, low power consumption for battery operation and low cost for personal use. A Winner-offset circuit performs a close competitor detection and process variation adjustment to enhance existing memory capacity. We report on experimental data from test chips. Maximum capability of the circuit is estimated based on a process variation model of MOS transistors.>

The lossless property of an MOS floating gate is exploited to implement exact summing operations in the charge domain. Lossless charge sharing in such structures yields circuits with potential applications as building blocks for analog-signal processing. A canonical structure, the Multiple Input Floating-gate Differential Amplifier is proposed and its use in different circuit configurations demonstrated. Experimental data from a multiple differential input operational amplifier are presented. Limitations of the proposed circuits are also discussed.>

In this work, the effects of surface potential fluctuations on the channel charge of a MOSFET are studied. By accounting for surface potential saturation, continuous models from below to above threshold are developed for the effective channel carrier concentration, the effective channel conductivity and, most importantly, the effective channel carrier mobility. The modeled mobility shows a dramatic drop-off around the threshold voltage, in agreement with experimental results. The equations developed herein may be used to improve the accuracy of existing transistor models for circuit simulation.>

We consider the problem of decoding block coded data, using a physical dynamical system. We sketch out a decompression algorithm for fractal block codes and then show how to implement a recurrent neural network using physically simple but highly-nonlinear, analog circuit models of neurons and synapses. The nonlinear system has many fixed points, but we have at our disposal a procedure to choose the parameters in such a way that only one solution, the desired solution, is stable. As a partial proof of the concept, we present experimental data from a small system a 16-neuron analog CMOS chip fabricated in a 2m analog p-well process. This chip operates in the subthreshold regime and, for each choice of parameters, converges to a unique stable state. Each state exhibits a qualitatively fractal shape.

Present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. This approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness.>

An analog CMOS integration of a model for the auditory periphery is presented. The model consists of middle ear, basilar membrane, and hair cell/synapse modules which are derived from neurophysiological studies. The circuit realization of each module is discussed, and experimental data of each module's response to sinusoidal excitation are given. The nonlinear speech processing capabilities of the system are demonstrated using the voiced syllable |ba|. The multichannel output of the silicon model corresponds to the time-varying instantaneous firing rates of auditory nerve fibers that have different characteristic frequencies. These outputs are similar to the physiologically obtained responses. The actual implementation uses subthreshold CMOS technology and analog continuous-time circuits, resulting in a real-time, micropower device with potential applications as a preprocessor of auditory stimuli.

An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

We present a new approach to the engineering of collective analog computing systems that emphasizes the role of currents as an appropriate signal representation and the need for low-power dissipation and simplicity in the basic functional circuits. The design methodology and implementation style that we describe are inspired by the functional and organizational principles of neuronal circuits in living systems. We have implemented synthetic neurons and synapses in analog CMOS VLSI that are suitable for building associative memories and self-organizing feature maps.

The van der Pauw dual technique is used to perform in situ Hall-effect measurements on short-channel GaAs field-effect transistors (GaAs FETs). The technique is briefly described and some practical and theoretical problems associated with this technique are discussed.