Timing errors are an increasing reliability concern in nanometer technology, high complexity and multi-voltage/frequency integrated circuits. A local error detection and correction technique is presented in this work that is based on a new bit flipping flip-flop. Whenever a timing error is detected, it is corrected by complementing the output of the corresponding flip-flop. The proposed solution is characterized by very low silicon area and power requirements compared to previous design schemes in the open literature. To validate its efficiency, it has been applied in the design of a MIPS microprocessor core in a 90 nm technology, while a demonstration version of the same core in an FPGA platform is presented.

Timing errors are a major threat in nanometer technology integrated circuits. Razor is a well known timing error tolerance design technique. However, its silicon area cost makes it unattractive for widespread use. In this work, we reuse the Razor topology in order to achieve low power scan testing operations and make this technique a viable solution which will serve both on-line and off-line testing requirements. In addition, the ability to apply this technique for at-speed scan testing is also explored in this work. According to the experimental results, the scan power consumption is drastically reduced since the signal transitions at the inputs of the combinational logic are eliminated during the scan testing operations.

Timing error tolerance is of great importance in nanometer technology integrated circuits. In this paper, the Time Dilation design technique is proposed that provides concurrent error detection and correction in the field of application and also supports off-line manufacturing scan testing. By utilizing a new scan Flip-Flop, the Time Dilation technique is capable to detect and correct multiple errors at the minimum penalty of one clock cycle delay. The silicon area overhead and the power consumption are substantially reduced, as compared to the Razor design approach, since no additional memory elements are required. At the same time, the proposed technique introduces only negligible performance degradation since no extra circuitry is inserted in the critical paths of a design.

Aging mechanisms, like Negative Bias Temperature Instability (NBTI), are a great concern in CMOS nanometer technologies. In this work, we present pipeline oriented timing error tolerance techniques with a special interest in NBTI related performance degradation. Three scenarios are discussed that provide the required error tolerance in pipeline based designs. Moreover, a new flip-flop is presented, to support two of the above scenarios, which is capable to detect and locally correct timing errors. A main characteristic of the proposed flip-flop is the NBTI resistant error handling operation. Simulation results validate the efficiency of the new design.

A method for the optimization of the efficiency of alternate tests for adjustable RF mixers is presented in this paper. Alternate tests provide a cost- and time-effective substitute for their conventional specification-based counterparts by attempting to predict rather than directly measuring a circuit's performance from its response to suitable test stimuli. In order to provide post-manufacture yield recovery through calibration, integrated RF circuits-especially nanometric circuits-are often designed to present some form of adjustability. Such a property offers a set of discrete states of operation, from which a performance-compliant state is selected by calibration. In general, an alternate test can be conducted for each discrete state of operation, thus providing a large set of test observables from which regression models can be constructed to predict performance in all available states. However, test time and cost concerns impose that the derivation of the predictive models should be performed through an optimization procedure that aims to select a subset of the test observables that minimizes a certain cost criterion. In this paper, alternate tests for adjustable RF mixers are considered where the test response consists of dc voltage levels that appear at certain circuit nodes while the mixer operates in homodyne mode. Selection algorithms are applied to determine the optimum observables from the test response. Simulations on a typical RF mixer, designed in an 0.18- μm CMOS technology, have shown significant improvement in the corresponding alternate test efficiency.

Strengthening failure mechanisms accentuate timing errors as a real threat in nanometer technology microprocessor cores. In this work, we present a low-cost and low-power, multiple timing error detection and correction technique, which is based on a new flip-flop design. This flip-flop exploits a transition detector for error detection along with an asynchronous local error correction scheme to provide timing error tolerance. The proposed and the well known Razor techniques were applied separately in the design of two versions of a 32-bit MIPS microprocessor core using a 90nm CMOS technology. Comparisons based on the experimental results validate the efficiency of the new design approach.

A Build-In Self-Test (BiST) circuit suitable for embedded RF Mixers in System-on-Chip applications is presented in this paper. This is a defect-oriented test scheme that dynamically sets the Mixer to operate in homodyne mode. The DC level generated at its output is used to control the oscillation frequency of a simple voltage controlled oscillator. Deviations of the oscillation frequency from the expected range of values indicate a defective Mixer. The proposed BiST technique has been applied to a typical receiver's differential RF Mixer using a 0.35μm CMOS technology. Simulation results validated the efficiency of the BiST circuit which was capable to provide a high fault coverage of catastrophic faults (which exceeds 91%) and a small test application time (1μs), at a silicon area cost approximately 16% of the Mixer area.

Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency.

A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for the implementation of high fan-in embedded checkers, is presented. The new checker is characterised by high testability, high speed operation and low silicon area requirements. The circuit has been designed, for various fan-in values, in a 0.18 mum technology and electrical simulations have been carried out to validate its operation, considering process, power supply and temperature variations as well as variations of the electrical parameters.

We present two full-custom implementations of the Register Alias Table (RAT) for a 4-way superscalar dynamically-scheduled processor in a commercial 130nm CMOS technology. The implementations differ in the way they organize the embedded global checkpoints (GCs) which support speculative execution. In the first implementation, representative of early designs, the GCs are organized as shift registers. In the second implementation, representative of more recent proposals, the GCs are organized as random access buffers. We measure the impact of increasing thenumber of GCs on the latency, energy, and area of the RAT. The results support the importance of recent techniques that reduce the number of GCs while maintaining performance.

A new differential current mirror logic (DCML) family is presented. It is based on a dynamic differential topology and uses current mirrors to enhance current sensing and a sense amplifier to speed up output evaluation. Its performance in terms of delay, power and area is compared to that of cross coupled differential domino (CCDD) logic. Simulations, using a 0.18mum technology to implement high fan-in XOR/XNOR gates, were utilized to evaluate the performance of the two topologies. It is shown that for fan-ins higher than 4 the proposed logic family presents increasing reduction in delay and energy against single and multi-stage CCDD implementations, with the single-stage CCDD circuits degrading fast and being inefficient for fan-ins higher than 10. In parallel, the silicon area penalty of the DCML towards single-stage CCDD is very small and constant regardless of the gate fan-in, while multi-stage CCDDs take a much grater area than DCML which increases with the number of gates used in the multi-stage implementation

A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for high n-variable (high fan-in) implementations, is presented. The checker is characterized by high testability, high operating frequencies and low silicon area requirements. The circuit has been designed, for various n-variable values, in a 0.18/spl mu/m technology and SPICE simulations have been carried out to validate its operation.

We propose a new concurrent soft and timing error detection circuit that exploits the time redundancy approach to achieve tolerance with respect to transient and delay faults. The idea is based on current mode sense amplifier topologies to provide fast error detection times.

Summary form only given. A new Built-in Self Test (BIST) scheme is presented that can be used for both off-line production or periodic testing of delay faults as well as for concurrent detection of faults causing signal delays in the field. The scheme is based on the I/sub DDT/ monitoring of the outputs of the circuit under test (CUT). The proposed scheme has minimal impact on the performance and silicon area of the design since the same response verifier circuit is used for both off-line and concurrent detection of errors in the field.

This paper presents an Improved Power-Delay Product (PDP) CMOS clock driver based on the charge recycling technique. Two NMOS pass transistors driven by appropriate control signals are used to accomplish the charge recycling procedure. Simulations have shown an up to 18% improvement of PDP over an equivalent conventional CMOS driver.

This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump utilises the cross-connected NMOS, voltage doubler, as a pumping stage. For low-voltage operation, where the performance of the NMOS is limited due to body effect, PMOS are used to increase the pumping gain. Simulations at 50 MHz have shown that for power supply voltages of 2 V, 1.5 V, 1.2 V and 0.9 V an output voltage of 11.5 V, 8.4 V, 6.5 V and 4 V can be generated respectively, using five pumping stages.