Demo Data from EDBT 2026 / reviewers in the wild / expert
Gheorghe Almási 0001
dblp:a/GeorgeAlmasi · also George Almási 0001
· DBLP profile ↗
29ranked-venue papers
8as first author
2since 2021 · last 2025
0009-0005-3879-6870ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 24 · 7 first-author · 1 since 2021Security and privacy · 2 · 2 since 2021Software engineering, systems software and programming languages · 2 · 1 first-authorDatabases, data management, data science and information retrieval · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
10 papers |
Parallel and multicore computing · 52% High-performance computing · 28% Storage systems · 5% | |
| Software engineering, system software, and programming languages
5 papers |
Compilers and program optimization · 76% Programming languages and type systems · 12% Runtime systems and virtual machines · 12% | |
| Theoretical computer science
1 paper |
Graph algorithms and graph theory · 50% Distributed computing theory · 50% |
Topics — the 29 heaviest of 32, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
parallel programming models |
0.4 | 4 | 2011 | ClusterSs: a task-based programming model for clusters · HPDC 2011 Fast PGAS Implementation of Distributed Graph Algorithms · SC 2010 Performance without pain = productivity: data layout and collective communication in UPC · PPoPP 2008 |
Parallel and multicore computing › parallel programming models › distributed memory programming models
partitioned global address space |
0.3 | 3 | 2010 | Fast PGAS Implementation of Distributed Graph Algorithms · SC 2010 Performance without pain = productivity: data layout and collective communication in UPC · PPoPP 2008 Shared memory programming for large scale machines · PLDI 2006 |
High-performance computing
cluster computing |
0.1 | 1 | 2011 | ClusterSs: a task-based programming model for clusters · HPDC 2011 |
Parallel and multicore computing
dataflow computing |
0.1 | 1 | 2011 | ClusterSs: a task-based programming model for clusters · HPDC 2011 |
Parallel and multicore computing › parallel programming models
task-based programming |
0.1 | 1 | 2011 | ClusterSs: a task-based programming model for clusters · HPDC 2011 |
Distributed computing theory
distributed graph algorithms |
0.1 | 1 | 2010 | Fast PGAS Implementation of Distributed Graph Algorithms · SC 2010 |
Graph algorithms and graph theory
graph algorithms |
0.1 | 1 | 2010 | Fast PGAS Implementation of Distributed Graph Algorithms · SC 2010 |
High-performance computing › supercomputing
bluegene/l |
0.1 | 3 | 2006 | Unlocking the Performance of the BlueGene/L Supercomputer · SC 2004 An overview of the BlueGene/L Supercomputer · SC 2002 High performance file I/O for the Blue Gene/L supercomputer · HPCA 2006 |
Storage systems
data layout |
0.1 | 1 | 2008 | Performance without pain = productivity: data layout and collective communication in UPC · PPoPP 2008 |
Interconnection networks and networks-on-chip › network topology
torus network |
0.1 | 2 | 2006 | Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006 Unlocking the Performance of the BlueGene/L Supercomputer · SC 2004 |
Compilers and program optimization › memory optimization
data locality optimization |
0.1 | 1 | 2006 | Programming for parallelism and locality with hierarchically tiled arrays · PPoPP 2006 |
Compilers and program optimization
optimizing compiler |
0.1 | 1 | 2006 | Shared memory programming for large scale machines · PLDI 2006 |
Compilers and program optimization › loop transformation
tiling |
0.1 | 1 | 2006 | Programming for parallelism and locality with hierarchically tiled arrays · PPoPP 2006 |
Parallel and multicore computing
data-parallel programming |
0.1 | 1 | 2006 | Programming for parallelism and locality with hierarchically tiled arrays · PPoPP 2006 |
Memory systems › memory bandwidth
memory bandwidth optimization |
0.1 | 1 | 2006 | Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006 |
Parallel and multicore computing › parallel computing › parallel communication
one-sided communication |
0.1 | 1 | 2006 | Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006 |
High-performance computing
parallel i/o |
0.1 | 1 | 2006 | High performance file I/O for the Blue Gene/L supercomputer · HPCA 2006 |
Distributed systems › distributed communication
remote memory access |
0.1 | 1 | 2006 | Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006 |
High-performance computing
supercomputing |
0.1 | 2 | 2006 | An overview of the BlueGene/L Supercomputer · SC 2002 High performance file I/O for the Blue Gene/L supercomputer · HPCA 2006 |
Integrated circuit design › digital circuit design › arithmetic circuit design
floating-point unit |
0.0 | 1 | 2004 | Unlocking the Performance of the BlueGene/L Supercomputer · SC 2004 |
High-performance computing
supercomputer architecture |
0.0 | 1 | 2004 | Unlocking the Performance of the BlueGene/L Supercomputer · SC 2004 |
Runtime systems and virtual machines › dynamic compilation
just-in-time compilation |
0.0 | 1 | 2002 | MaJIC: Compiling MATLAB for Speed and Responsiveness · PLDI 2002 |
Integrated circuit design
system-on-chip |
0.0 | 1 | 2002 | An overview of the BlueGene/L Supercomputer · SC 2002 |
High-performance computing
scientific computing systems |
0.0 | 1 | 2010 | Fast PGAS Implementation of Distributed Graph Algorithms · SC 2010 |
High-performance computing
collective communication |
0.0 | 1 | 2008 | Performance without pain = productivity: data layout and collective communication in UPC · PPoPP 2008 |
Parallel and multicore computing › parallel programming models
shared-memory parallelization |
0.0 | 1 | 1999 | MATmarks: A Shared Memory Environment for MATLAB Programming · HPDC 1999 |
High-performance computing
distributed memory systems |
0.0 | 1 | 2006 | Shared memory programming for large scale machines · PLDI 2006 |
Storage systems › file systems › distributed file system
parallel file system |
0.0 | 1 | 2006 | High performance file I/O for the Blue Gene/L supercomputer · HPCA 2006 |
Performance modeling and evaluation
benchmarking |
0.0 | 1 | 2004 | Unlocking the Performance of the BlueGene/L Supercomputer · SC 2004 |
Methods — techniques the papers use, named apart from their topics
asynchronous message · 0.1array operation overloading · 0.1affinity test elimination · 0.1interrupt-driven communication · 0.1hierarchical partitioning · 0.1global arrays · 0.1MPI-IO · 0.1ARMCI · 0.1performance analysis · 0.0benchmarking · 0.0speculative ahead-of-time compilation · 0.0just-in-time compilation · 0.0shared memory commands · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Towards Continuous Integrity Attestation and Its Challenges in Practice: A Case Study of KeylimeabstractContinuous integrity attestation is vital for cloud providers to ensure the integrity of remote systems in a continuous manner. Current solutions, such as Keylime, rely on Trusted Platform Module (TPM) and Linux’s Integrity Measurement Architecture (IMA) but often struggle to balance minimizing false alerts and maintaining effective threat detection. In this paper, we examine common causes of attestation failures in Keylime through active experiments. We find that false positives often stem from unscheduled OS updates, and we propose a dynamic policy generation scheme as a solution (validated over 66 days of experiments). Our false negative experiments reveal vulnerabilities in existing designs, including five common issues across Keylime and IMA. Exploiting these issues, attackers could evade detection in all tested scenarios. Our findings offer insights into common failures of continuous integrity attestation, and our proposed solution is being integrated into Keylime with community support, enhancing cloud security. Our code will be available at https://github.com/mruffin/Dynamic-Policy-Generator. Margie Ruffin, Chenkai Wang 0001, Gheorghe Almási 0001, Abdulhamid Adebayo, Hubertus Franke, Gang Wang 0011 |
DSN | 3 |
| 2023 | Remote attestation of confidential VMs using ephemeral vTPMsabstractTrying to address the security challenges of a cloud-centric software deployment paradigm, silicon and cloud vendors are introducing confidential computing – an umbrella term aimed at providing hardware and software mechanisms for protecting cloud workloads from the cloud provider and its software stack. Today, Intel Software Guard Extensions (SGX), AMD secure encrypted virtualization (SEV), Intel trust domain extensions (TDX), etc., provide a way to shield cloud applications from the cloud provider through encryption of the application’s memory below the hardware boundary of the CPU, hence requiring trust only in the CPU vendor. Unfortunately, existing hardware mechanisms do not automatically enable the guarantee that a protected system was not tampered with during configuration and boot time. Such a guarantee relies on a hardware root of trust, i.e., an integrity-protected location that can store measurements in a trustworthy manner, extend them, and authenticate the measurement logs to the user (remote attestation). Vikram Narayanan, Cláudio Carvalho, Angelo Ruocco, Gheorghe Almási 0001, James Bottomley, Mengmei Ye, Tobin Feldman-Fitzthum, Daniele Buono, Hubertus Franke, Anton Burtsev |
ACSAC | 4 |
| 2012 | Composable, non-blocking collective operations on power7 IHabstractThe Power7 IH (P7IH) is one of IBM's latest generation of supercomputers. Like most modern parallel machines, it has a hierarchical organization consisting of simultaneous multithreading (SMT) within a core, multiple cores per processor, multiple processors per node (SMP), and multiple SMPs per cluster. A low latency/high bandwidth network with specialized accelerators is used to interconnect the SMP nodes. System software is tuned to exploit the hierarchical organization of the machine. Ilie Gabriel Tanase, Gheorghe Almási 0001, Hanhong Xue, Charles Archer |
ICS | 2 |
| 2012 | Network Endpoints for Clusters of SMPsabstractModern large scale parallel machines feature an increasingly deep hierarchy of interconnections. Individual processing cores employ simultaneous multithreading (SMT) to better exploit functional units, multiple coherent processors are collocated in a node to better exploit links to cache, memory and network (SMP), and multiple nodes are interconnected by specialized low latency/high speed networks. Current trends indicate ever wider SMP nodes in the future. To service these nodes, modern high performance network devices (including Infiniband and all of IBM's recent offerings) offer the ability to sub-divide the network devices' resources among the processing threads. System software, however, lags in exploiting these capabilities, leaving users of e.g., MPI[14], UPC[19] in a bind, requiring complex and fragile workarounds in user programs. In this paper we discuss our implementation of endpoints, the software paradigm central to the IBM PAMI messaging library [3]. A PAMI endpoint is an expression in software of a slice of the network device. System software can service endpoints without serializing the many threads on an SMP by forcing them through a critical section. In the paper we describe the basic guarantees offered by PAMI to the programmer, and how these can be used to enable efficient implementations of high level libraries and programming languages like UPC. We evaluate the efficiency of our implementation on a novel P7IHsystem with up to 4096 cores, running micro benchmarks designed to find performance deficiencies in the endpoints implementation of both point-to-point and collective functions. Ilie Gabriel Tanase, Gheorghe Almási 0001, Hanhong Xue, Charles Archer |
SBAC-PAD | 2 |
| 2012 | A high-productivity task-based programming model for clustersabstractSUMMARY Programming for large‐scale, multicore‐based architectures requires adequate tools that offer ease of programming and do not hinder application performance. StarSs is a family of parallel programming models based on automatic function‐level parallelism that targets productivity. StarSs deploys a data‐flow model: it analyzes dependencies between tasks and manages their execution, exploiting their concurrency as much as possible. This paper introduces Cluster Superscalar (ClusterSs), a new StarSs member designed to execute on clusters of SMPs (Symmetric Multiprocessors). ClusterSs tasks are asynchronously created and assigned to the available resources with the support of the IBM APGAS runtime, which provides an efficient and portable communication layer based on one‐sided communication. We present the design of ClusterSs on top of APGAS, as well as the programming model and execution runtime for Java applications. Finally, we evaluate the productivity of ClusterSs, both in terms of programmability and performance and compare it to that of the IBM X10 language. Copyright © 2012 John Wiley & Sons, Ltd. Enric Tejedor, Montse Farreras, David Grove, Rosa M. Badia, Gheorghe Almási 0001, Jesús Labarta |
Concurr. Comput. Pract. Exp. | 5 |
| 2011 | ClusterSs: a task-based programming model for clustersabstractProgramming for large-scale, multicore-based architectures requires adequate tools that offer ease of programming while not hindering application performance. StarSs is a family of parallel programming models based on automatic function level parallelism that targets productivity. StarSs deploys a data-flow model: it analyses dependencies between tasks and manages their execution, exploiting their concurrency as much as possible. We introduce Cluster Superscalar (ClusterSs), a new StarSs member designed to execute on clusters of SMPs. ClusterSs tasks are asynchronously created and assigned to the available resources with the support of the IBM APGAS runtime, which provides an efficient and portable communication layer based on one-sided communication.This short paper gives an overview of the ClusterSs design on top of APGAS, as well as the conclusions of a productivity study; in this study, ClusterSs was compared to the IBM X10 language, both in terms of programmability and performance. A technical report is available with the details. Enric Tejedor, Montse Farreras, David Grove, Rosa M. Badia, Gheorghe Almási 0001, Jesús Labarta |
HPDC | 5 |
| 2010 | Fast PGAS Implementation of Distributed Graph AlgorithmsabstractDue to the memory intensive workload and the erratic access pattern, irregular graph algorithms are notoriously hard to implement and optimize for high performance on distributed-memory systems. Although the PGAS paradigm proposed recently improves ease of programming, no high performance PGAS implementation of large-scale graph analysis is known. We present the first fast PGAS implementation of graph algorithms for the connected components and minimum spanning tree problems. By improving memory access locality, compared with the naive implementation, our implementation exhibits much better communication efficiency and cache performance on a cluster of SMPs. With additional algorithmic and PGASspecific optimizations, our implementation achieves significant speedups over both the best sequential implementation and the best single-node SMP implementation for large, sparse graphs with more than a billion edges. Guojing Cong, Gheorghe Almási 0001, Vijay A. Saraswat |
SC | 2 |
| 2009 | Scalable RDMA performance in PGAS languagesabstractPartitioned global address space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, or cluster ofSMPs. Users can program large scale machines with easy-to-use, shared memory paradigms. In order to exploit large scale machines efficiently, PGAS language implementations and their runtime system must be designed for scalability and performance. The IBM XLUPC compiler and runtime system provide a scalable design through the use of the shared variable directory (SVD). The SVD stores meta-information needed to access shared data. It is dereferenced, in the worst case, for every shared memory access, thus exposing a potential performance problem. In this paper we present a cache of remote addresses as an optimization that will reduce the SVD access overhead and allow the exploitation of native (remote) direct memory accesses. It results in a significant performance improvement while maintaining the run-time portability and scalability. Montse Farreras, Gheorghe Almási 0001, Calin Cascaval, Toni Cortes |
IPDPS | 2 |
| 2008 | The deep computing messaging framework: generalized scalable message passing on the blue gene/P supercomputerabstractWe present the architecture of the Deep Computing Messaging Framework (DCMF), a message passing runtime designed for the Blue Gene/P machine and other HPC architectures. DCMF has been designed to easily support several programming paradigms such as the Message Passing Interface (MPI), Aggregate Remote Memory Copy Interface (ARMCI), Charm++, and others. This support is made possible as DCMF provides an application programming interface (API) with active messages and non-blocking collectives. DCMF is being open sourced and has a layered component based architecture with multiple levels of abstraction, allowing the members of the community to contribute new components to its design at the various layers. The DCMF runtime can be extended to other architectures through the development of architecture specific implementations of interface classes. The production DCMF runtime on Blue Gene/P takes advantage of the direct memory access (DMA) hardware to offload message passing work and achieve good overlap of computation and communication. We take advantage of the fact that the Blue Gene/P node is a symmetric multi-processor with four cache-coherent cores and use multi-threading to optimize the performance on the collective network. We also present a performance evaluation of the DCMF runtime on Blue Gene/P and show that it delivers performance close to hardware limits. Sameer Kumar 0001, Gábor Dózsa, Gheorghe Almási 0001, Philip Heidelberger, Dong Chen 0005, Mark Giampapa, Michael Blocksome, Ahmad Faraj, Jeff Parker, Joe Ratterman, Brian E. Smith, Charles Archer |
ICS | 3 |
| 2008 | Evaluating the effect of replacing CNK with linux on the compute-nodes of blue gene/labstractThe Blue Gene machines in production today run a small single-user, single-process kernel (CNK) having a limited functionality. Motivated by the desire to provide applications with a much richer operating environment, we evaluate the effect of replacing CNK with a standard Linux kernel on the compute nodes of Blue Gene/L. We show that with a relatively small amount of effort we were able to improve benchmark performance under Linux up to a level that is comparable to CNK. Edi Shmueli, Gheorghe Almási 0001, José R. Brunheroto, José G. Castaños, Gábor Dózsa, Sameer Kumar 0001, Derek Lieber |
ICS | 2 |
| 2008 | Performance without pain = productivity: data layout and collective communication in UPCabstractThe next generations of supercomputers are projected to have hundreds of thousands of processors. However, as the numbers of processors grow, the scalability of applications will be the dominant challenge. This forces us to reexamine some of our fundamental ways that we approach the design and use of parallel languages and runtime systems. Rajesh Nishtala, Gheorghe Almási 0001, Calin Cascaval |
PPoPP | 2 |
| 2006 | High performance file I/O for the Blue Gene/L supercomputerabstractParallel I/O plays a crucial role for most data-intensive applications running on massively parallel systems like Blue Gene/L that provides the promise of delivering enormous computational capability. We designed and implemented a highly scalable parallel file I/O architecture for Blue Gene/L, which leverages the benefit of the hierarchical and functional partitioning design of the system software with separate computational and I/O cores. The architecture exploits the scalability aspect of GPFS (General Parallel File System) at the backend, while using MPI I/O as an interface between the application I/O and the file system. We demonstrate the impact of our high performance I/O solution for Blue Gene/L with a comprehensive evaluation that consists of a number of widely used parallel I/O benchmarks and I/O intensive applications. Our design and implementation is not only able to deliver at least one order of magnitude speed up in terms of I/O bandwidth for a real-scale application HOMME (achieving aggregate bandwidth of 1.8 GB/Sec and 2.3 GB/Sec for write and read accesses, respectively), but also supports high-level parallel I/O data interfaces such as parallel HDF5 and parallel NetCDF scaling up to a large number of processors. Hao Yu 0008, Ramendra K. Sahoo, C. Howson, Gheorghe Almási 0001, José G. Castaños, Manish Gupta 0002, José E. Moreira, Jeff Parker, Thomas Engelsiepen, Robert B. Ross, Rajeev Thakur, Robert Latham, William Gropp |
HPCA | 4 |
| 2006 | Scaling MPI to short-memory MPPs such as BG/LabstractScalability to large number of processes is one of the weaknesses of current MPI implementations. Standard implementations are able to scale to hundreds of nodes, but not beyond. The main problem in these implementations is that they assume some resources (for both data and control-data) will always be available to receive/process unexpected messages. As we will show, this is not always true, especially in short-memory machines like the BG/L that has 64K nodes but each node only has 512Mbytes of memory.The objective of this paper is to present one algorithm that improves the robustness of MPI implementations for short-memory MPPs, taking care of data and control-data reception, the system will scale up to any number of nodes. The proposed solution achieves this goal without any observable overhead when there are no memory problems. Furthermore, in the worst case, when memory resources are extremely scarce, the overhead will never double the execution time (and we should never forget that in this extreme situation, traditional MPI implementations would fail to execute). Montse Farreras, Toni Cortes, Jesús Labarta, Gheorghe Almási 0001 |
ICS | 4 |
| 2006 | Hierarchically tiled arrays for parallelism and localityabstractParallel programming is facilitated by constructs which, unlike the widely used SPMD paradigm, provide programmers with a global view of the code and data structures. These constructs could be compiler directives containing information about data and task distribution, language extensions specifically designed for parallel computation, or classes that encapsulate parallelism. In this paper, we describe a class developed at Illinois and its Matlab implementation. This class can be used to conveniently express both parallelism and locality. A C++ implementation is now underway. Its characteristics will be reported in a future paper. We have implemented most of the NAS benchmarks using our HTA Matlab extensions and found during that HTAs enable the fast prototyping of parallel algorithms and produce programs that are easy to understand and maintain. Ganesh Bikshandi, Daniel Hoeflinger, Gheorghe Almási 0001, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Christoph von Praun |
IPDPS | 4 |
| 2006 | Achieving strong scaling with NAMD on Blue Gene/LabstractNAMD is a scalable molecular dynamics application, which has demonstrated its performance on several parallel computer architectures. Strong scaling is necessary for molecular dynamics as problem size is fixed, and a large number of iterations need to be executed to understand interesting biological phenomenon. The Blue Gene/L machine is a massive source of compute power. It consists of tens of thousands of embedded Power PC 440 processors. In this paper, we present several techniques to scale NAMD to 8192 processors of Blue Gene/L. These include topology specific optimizations, new messaging protocols, load-balancing, and overlap of computation and communication. We were able to achieve 1.2 TF of peak performance for cutoff simulations and 0.99 TF with PME. Sameer Kumar 0001, Chao Huang 0029, Gheorghe Almási 0001, Laxmikant V. Kalé |
IPDPS | 3 |
| 2006 | Shared memory programming for large scale machinesabstractThis paper describes the design and implementation of a scalable run-time system and an optimizing compiler for Unified Parallel C (UPC). An experimental evaluation on BlueGene/L®, a distributed-memory machine, demonstrates that the combination of the compiler with the runtime system produces programs with performance comparable to that of efficient MPI programs and good performance scalability up to hundreds of thousands of processors.Our runtime system design solves the problem of maintaining shared object consistency efficiently in a distributed memory machine. Our compiler infrastructure simplifies the code generated for parallel loops in UPC through the elimination of affinity tests, eliminates several levels of indirection for accesses to segments of shared arrays that the compiler can prove to be local, and implements remote update operations through a lower-cost asynchronous message. The performance evaluation uses three well-known benchmarks --- HPC RandomAccess, HPC STREAM and NAS CG --- to obtain scaling and absolute performance numbers for these benchmarks on up to 131072 processors, the full BlueGene/L machine. These results were used to win the HPC Challenge Competition at SC05 in Seattle WA, demonstrating that PGAS languages support both productivity and performance. Christopher Barton, Calin Cascaval, Gheorghe Almási 0001, Yili Zheng, Montse Farreras, Siddhartha Chatterjee, José Nelson Amaral |
PLDI | 3 |
| 2006 | Programming for parallelism and locality with hierarchically tiled arraysabstractTiling has proven to be an effective mechanism to develop high performance implementations of algorithms. Tiling can be used to organize computations so that communication costs in parallel programs are reduced and locality in sequential codes or sequential components of parallel programs is enhanced.In this paper, a data type - Hierarchically Tiled Arrays or HTAs - that facilitates the direct manipulation of tiles is introduced. HTA operations are overloaded array operations. We argue that the implementation of HTAs in sequential OO languages transforms these languages into powerful tools for the development of high-performance parallel codes and codes with high degree of locality. To support this claim, we discuss our experiences with the implementation of HTAs for MATLAB and C++ and the rewriting of the NAS benchmarks and a few other programs into HTA-based parallel form. Ganesh Bikshandi, Daniel Hoeflinger, Gheorghe Almási 0001, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Christoph von Praun |
PPoPP | 4 |
| 2006 | Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputerabstractThis paper discusses the design and implementation of a one-sided communication interface for the IBM Blue Gene/L supercomputer. This interface facilitates ARMCI and the Global Arrays toolkit and can be used by other one-sided communication libraries. New protocols, interrupt driven communication, and compute node kernel enhancements were required to enable these libraries. Three possible methods for enabling ARMCI on the Blue Gene/L software stack are discussed. A detailed look into the development process shows how the implementation of the one-sided communication interface was completed. This was accomplished on a compressed time scale with the collaboration of various organizations within IBM and open source communities. In addition to enabling the one-sided libraries, bandwidth enhancements were made for communication along a diagonal on the Blue Gene/L torus network. The maximum bandwidth improved by a factor of three. This work will enable a variety of one-sided applications to run on Blue Gene/L. Michael Blocksome, Charles Archer, Todd Inglett, Patrick McCarthy, Michael B. Mundy, Joe Ratterman, A. Sidelnik, Brian E. Smith, Gheorghe Almási 0001, José G. Castaños, Derek Lieber, José E. Moreira, Sriram Krishnamoorthy, Vinod Tipparaju, Jarek Nieplocha |
SC | 9 |
| 2005 | Early Experience with Scientific Applications on the Blue Gene/L Supercomputer
Gheorghe Almási 0001, Gyan Bhanot, Dong Chen 0005, Maria Eleftheriou, Blake G. Fitch, Alan Gara, Robert S. Germain, John A. Gunnels, Manish Gupta 0002, Philip Heidelberger, Michael Pitman, Aleksandr Rayshubskiy, James C. Sexton, Frank Suits, Pavlos Vranas, Robert Walkup, T. J. Christopher Ward, Yuriy Zhestkov, Alessandro Curioni, Wanda Andreoni, Charles Archer, José E. Moreira, Richard Loft, Henry M. Tufo, Theron Voran, Katherine Riley |
Euro-Par | 1 |
| 2005 | Scaling physics and material science applications on a massively parallel Blue Gene/L systemabstractBlue Gene/L represents a new way to build supercomputers, using a large number of low power processors, together with multiple integrated interconnection networks. Whether real applications can scale to tens of thousands of processors (on a machine like Blue Gene/L) has been an open question. In this paper, we describe early experience with several physics and material science applications on a 32,768 node Blue Gene/L system, which was installed recently at the Lawrence Livermore National Laboratory. Our study shows some problems in the applications and in the current software implementation, but overall, excellent scaling of these applications to 32K nodes on the current Blue Gene/L system. While there is clearly room for improvement, these results represent the first proof point that MPI applications can effectively scale to over ten thousand processors. They also validate the scalability of the hardware and software architecture of Blue Gene/L. Gheorghe Almási 0001, Gyan Bhanot, Alan Gara, Manish Gupta 0002, James C. Sexton, Robert Walkup, Vasily V. Bulatov, Andrew W. Cook, Bronis R. de Supinski, James N. Glosli, Jeffrey A. Greenough, François Gygi, Alison Kubota, Steve Louis, Thomas E. Spelce, Frederick H. Streitz, Peter L. Williams, Robert K. Yates, Charles Archer, José E. Moreira, Charles A. Rendleman |
ICS | 1 |
| 2005 | Optimization of MPI collective communication on BlueGene/L systemsabstractBlueGene/L is currently the world's fastest supercomputer. It consists of a large number of low power dual-processor compute nodes interconnected by high speed torus and collective networks, Because compute nodes do not have shared memory, MPI is the the natural programming model for this machine. The BlueGene/L MPI library is a port of MPICH2.In this paper we discuss the implementation of MPI collectives on BlueGene/L. The MPICH2 implementation of MPI collectives is based on point-to-point communication primitives. This turns out to be suboptimal for a number of reasons. Machine-optimized MPI collectives are necessary to harness the performance of BlueGene/L. We discuss these optimized MPI collectives, describing the algorithms and presenting performance results measured with targeted micro-benchmarks on real BlueGene/L hardware with up to 4096 compute nodes. Gheorghe Almási 0001, Philip Heidelberger, Charles Archer, Xavier Martorell, C. Christopher Erway, José E. Moreira, Burkhard D. Steinmacher-Burow, Yili Zheng |
ICS | 1 |
| 2004 | Implementing MPI on the BlueGene/L Supercomputer
Gheorghe Almási 0001, Charles Archer, José G. Castaños, C. Christopher Erway, Philip Heidelberger, Xavier Martorell, José E. Moreira, Kurt W. Pinnow, Joe Ratterman, Nils Smeds, Burkhard D. Steinmacher-Burow, William Gropp, Brian R. Toonen |
Euro-Par | 1 |
| 2004 | Unlocking the Performance of the BlueGene/L SupercomputerabstractThe BlueGene/L supercomputer is expected to deliver new levels of application performance by providing a combination of good single-node computational performance and high scalability. To achieve good single-node performance, the BlueGene/L design includes a special dual floating-point unit on each processor and the ability to use two processors per node. BlueGene/L also includes both a torus and a tree network to achieve high scalability. We demonstrate how benchmarks and applications can take advantage of these architectural features to get the most out of BlueGene/L. Gheorghe Almási 0001, Siddhartha Chatterjee, Alan Gara, John A. Gunnels, Manish Gupta 0002, Amy Henning, José E. Moreira, Robert Walkup |
SC | 1 |
| 2003 | An Overview of the Blue Gene/L System Software Organization
Gheorghe Almási 0001, Ralph Bellofatto, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Crumley, C. Christopher Erway, Joseph Gagliano, Derek Lieber, Xavier Martorell, José E. Moreira, Alda Sanomiya, Karin Strauss |
Euro-Par | 1 |
| 2002 | MaJIC: Compiling MATLAB for Speed and ResponsivenessabstractThis paper presents and evaluates techniques to improve the execution performance of MATLAB. Previous efforts concentrated on source to source translation and batch compilation; MaJIC provides an interactive frontend that looks like MATLAB and compiles/optimizes code behind the scenes in real time, employing a combination of just-in-time and speculative ahead-of-time compilation. Performance results show that the proper mixture of these two techniques can yield near-zero response time as well as performance gains previously achieved only by batch compilers. Gheorghe Almási 0001, David A. Padua |
PLDI | 1 |
| 2002 | An overview of the BlueGene/L SupercomputerabstractThis paper gives an overview of the BlueGene/L Supercomputer. This is a jointly funded research partnership between IBM and the Lawrence Livermore National Laboratory as part of the United States Department of Energy ASCI Advanced Architecture Research Program. Application performance and scaling studies have recently been initiated with partners at a number of academic and government institutions,including the San Diego Supercomputer Center and the California Institute of Technology. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures. Narasimha R. Adiga, Gheorghe Almási 0001, George S. Almási, Yariv Aridor, Rajkishore Barik, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Waiman Chan, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, K. M. Desai, Alina Deutsch, Tamar Domany, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, C. Christopher Erway, J. Esch, Blake G. Fitch, Joseph Gagliano, Alan Gara, Rahul Garg 0001, Robert S. Germain, Mark Giampapa, Balaji Gopalsamy, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, R. D. Jackson, T. Jamal-Eddine, Gerard V. Kopcsay, Elie Krevat, Manish P. Kurhekar, Alphonso P. Lanzetta, Derek Lieber, L. K. Liu, M. Lu, Mark P. Mendell, A. Misra, Yosef Moatti, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Adam J. Oliner, Vinayaka Pandit, R. B. Pudota, Rick A. Rand, Richard D. Regan, Bradley Rubin, Albert E. Ruehli, Silvius Vasile Rus, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, M. Sharma, Edi Shmueli, Sarabjeet Singh, Peilin Song, Vijay Srinivasan, Burkhard D. Steinmacher-Burow, Karin Strauss, Christopher W. Surovic, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, P. Verma, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, W. Barrett, C. Engel, B. Drehmel, B. Hilgart, D. Hill, F. Kasemkhani, David J. Krolak, Chun-Tao Li 0001, Thomas A. Liebsch, James A. Marcella, A. Muff, A. Okomo, M. Rouse, A. Schram, M. Tubbs, G. Ulsh, Charles D. Wait, J. Wittrup, Myung Bae, Kenneth A. Dockser, Lynn Kissel, Mark K. Seager, Jeffrey S. Vetter, K. Yates |
SC | 2 |
| 1999 | MATmarks: A Shared Memory Environment for MATLAB ProgrammingabstractMATmarks is an extension of the MATLAB tool that enables shared memory programming on a network of workstations by adding a small set of commands. The authors present a high level overview of the MATmarks system, the commands we added to MATLAB, and the performance gains we achieved as a result. Gheorghe Almási 0001, Calin Cascaval, David A. Padua |
HPDC | 1 |
| 1995 | A Parallel Algorithm for Computing Polygon Set Operations
Raghu Karinthi, Kankanahalli Srinivas, Gheorghe Almási 0001 |
J. Parallel Distributed Comput. | 3 |
| 1994 | Model Based Information AccessabstractThe engineering data of a large enterprise is typically distributed over a wide area and archived in a variety of databases and file systems. Access to such information is crucial to a team member, particularly in a concurrent engineering setting. However, this is not easy, because (1) a model of the relevant information is not available, and (2) there is no simple way to access the information without being knowledgeable about various computer data formats, file systems, and networks. We have developed a system called the Information Sharing System (ISS) to enable access to diverse and distributed information within a corporation. Such data could be stored in different repositories such as databases and file systems including those that contain multiple media. Our paper describes the methodology of the ISS, the details of the implementation and extensions planned for the future. Vasudevan Jagannathan, Raghu Karinthi, Gheorghe Almási 0001 |
Int. J. Cooperative Inf. Syst. | 3 |