The explosive growth of data-intensive applications and Generative AI (GAI) workloads has led to unprecedented demands on computing resources. Virtual Machine (VM) migration is pivotal in dynamically adjusting resource distribution across workloads. However, traditional reactive approaches often fall short in adapting to network changes and dynamic workloads. This paper presents a Digital Twin (DT) framework integrated with a data center to enhance resource utilization. The framework combines real-time monitoring, time-series forecasting, and Mixed-Integer Linear Programming (MILP) optimization to predict future bandwidth demands, CPU utilization, and memory usage, thereby determining optimal VM migration and placement strategies. Our analysis reveals that integrating forecasting with optimization reduces CPU load variance across servers by up to 50%. Compared to prior reactive or heuristic-based methods, our forecast-aware optimization framework achieves significantly more uniform resource distribution. Furthermore, capping server CPU load at 50% of capacity nearly eliminates variance, underscoring the effectiveness of the proposed model in stabilizing data center workloads.

An architectural framework is studied that can perform dynamic reconfiguration. A basic objective is to dynamically reconfigure the architecture so that its configuration is well matched with the current computational requirements. The reconfigurable resources of the architecture are partitioned into N slots. The configuration bits for each slot are provided through a connection to one of N independent busses, where each bus can select from among K configurations for each slot. Increasing the value of K can increase the number of configurations that the architecture can reach, but at the expense of more hardware complexity to construct the busses. Our study reveals that it is often possible for the architecture to closely track ideal desired configurations even when K is relatively small (e.g., two or four). The input configurations to the collection of busses are defined as steering vectors; thus, there are K steering vectors, each having N equal sized partitions of configuration bits. A combinatorial approach is introduced for designing steering vectors that enables the designer to evaluate trade-offs between performance and hardware complexity associated with the busses.

A new dynamic vector approach for the selection and management of the configuration of a reconfigurable superscalar processor is proposed. This new method improves on previous work that used steering vectors to guide the selection of functional units to be loaded into the processor. Dependencies among instructions in the instruction buffer are analyzed to enable a new scoring method. The dynamic vector technique is shown to reduce the amount of reconfiguration required while preserving execution resources. Simulation results reveal that, given enough configurable space, the configuration of the processor approaches a stable state.

A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex family of FPGAs. The instruction set of the PowerPC 405 is extended by selecting additional instructions from the full 32-bit PowerPC instruction set architecture (ISA), of which the PowerPC 405 ISA is a subset. The selected instructions are supported in hardware using the reconfigurable resources of the FPGA. The proposed design process gathers execution statistics for a target application through profiling or simulation. These statistics are then used to estimate the speedup that would be achieved if selected instructions from the full PowerPC ISA are added to the ISA of the PowerPC 405 processor. An experimental study of two embedded benchmarks show significant speedup when this approach is used to extend the PowerPC 405 processor to support various floating-point operations through the use of floating-point cores developed by QinetiQ.

In this paper, we derive a time-complexity bound for the gradient projection method for optimal routing in data networks. This result shows that the gradient projection algorithm of Goldstein-Levitin-Poljak type formulated by Bertsekas (1982), Bertsekas and Gallager (1987) and Bertsekas et al. (1984) converges to within /spl epsi/ in relative accuracy in O(/spl epsi//sup -2/h/sub min/N/sub max/) number of iterations, where N/sub max/ is the number of paths sharing the maximally shared link, and h/sub min/ is the diameter of the network. Based on this complexity result, we also show that the one-source-at-a-time update policy has a complexity bound which is O(n) times smaller than that of the all-at-a-time update policy, where n is the number of nodes in the network. The result of this paper argues for constructing networks with low diameter for the purpose of reducing complexity of the network control algorithms. The result also implies that parallelizing the optimal routing algorithm over the network nodes is beneficial.

Space-time adaptive processing (STAP) refers to a class of signal processing techniques used to process returns of an antenna array radar system. STAP algorithms are designed to extract desired target signals from returns comprised of Doppler shifts, ground clutter, and jamming interference. STAP simultaneously and adaptively combines the signals received on multiple elements of an antenna array-the spatial domain-and from multiple pulse repetition periods-the temporal domain. The output of STAP is a weighted sum of multiple returns, where the weights for each return in the sum are calculated adaptively and in real-time. The most computationally intensive portion of most STAP approaches is the calculation of the adaptive weight values. Calculation of the weights involves solving a set of linear equations based on an estimate of the covariance matrix associated with the radar return data. Existing approaches for STAP typically rely on the use of multiple digital signal processors (DSPs) or general-purpose processors (GPPs) to calculate the adaptive weights. These approaches are often based on solving multiple sets of linear equations and require the calculation of numerous vector inner products. This paper proposes the use of FPGAs as vector coprocessors capable of performing inner product calculation. Two different "inner-product co-processor" designs are introduced for use with the host DSP or GPP. The first has a multiply-and-accumulate structure, and the second uses reduction-style tree structure having two multipliers and an adder.

The focus of this paper is the implementation and utilization of an inexpensive heterogeneous multicomputer cluster for the study of load balancing techniques. The basic conclusion of the paper is that excellent performance is possible provided that the proper choices among various parameters and implementation options of the load balancing schemes are employed.

In a heterogeneous computing (HC) environment consisting of different types of machines, an application program is decomposed into subtasks, each of which is computationally homogeneous. The goal is to execute subtasks on the machines in such a way that the total program execution time is minimized. A mathematical framework is presented that models the matching of subtasks to machines, scheduling of subtasks' computation, scheduling of intermachine communication steps, and selection of sources of shared data items for intermachine communication (data relocation). The goal of this work is to generate a provably optimal scheme for communicating shared data among subtasks as an enhancement to any given matching and scheduling. Initially, it is assumed that at any instant in time, only one machine is being used for program execution and only one subtask is being executed. Based on this assumption, a polynomial algorithm is introduced to optimize scheduling and data relocation with respect to any given matching of subtasks to machines. The data relocation scheme is then extended to reduce intermachine data communication time in an HC environment with a given matching and scheduling of subtasks' computation where: multiple subtasks' computations can be performed concurrently on different machines; subtask computation steps can be overlapped with other subtasks' communication steps for intermachine data transfers; and machines in the HC suite are interconnected by a shared-bus type of network.

Optimal trajectory planning problems are often formulated as constrained variational problems. In general, solutions to variational problems are determined by appropriately discretizing the underlying objective functional and solving the resulting nonlinear differential equation(s) and/or nonlinear programming problem(s) numerically. These general solution techniques often require a significant amount of time to be computed, and therefore are of limited value when optimal trajectories need to be frequently computed and/or recomputed. In this paper, a realistic class of optimal trajectory planning problems is defined for which the existence of fast numerical solution techniques are demonstrated. To illustrate the practicality of this class of trajectory planning problems and the proposed solution techniques, three optimal trajectory planning problems for spray coating applications are formulated and solved. Based on the proposed discretization technique, it is shown that these problems can be reduced to either a linear program or a quadratic program, which are readily solved.

Automated spray coating is an important component of finishing operations in many industries. Robotic manipulators are used in such units to traverse around the object to be coated. This paper describes a framework for determining a good spatial path for the manipulator, in order to achieve uniform deposition over the surface and reduce wastage of coating material outside the surface. By imposing an arc-length based conditioning, the formulated variational problem is shown to be well-posed. The variation in deposition rate, the deposition outside the surface, and the arc length are minimized in a weighted combination. The necessary conditions for a minimizing spatial path are given by a set of nonlinear differential equations that are numerically solved.

Derives a time complexity bound for the gradient projection method for optimal routing in data networks. This result shows that the gradient projection algorithm of the Goldstein-Levitin-Poljak type formulated by Bertsekas (1982) converges to within /spl epsiv/ in relative accuracy in O(/spl epsiv//sup 2/h/sub min/N/sub max//sup L/) iterations, where N/sub max//sup L/ is the number of paths sharing the maximally shared link, and h/sub min/ is the diameter of the network. Based on this complexity result, the authors also show that the one-source-at-a-time update policy has a complexity bound which is O(n) times smaller than that of the all-at-a-time update policy [Bertsekas, 1982], where n is the number of nodes in the network. The result of the paper argues for constructing networks with low diameter for the purpose of reducing the complexity of the network control algorithms. The result also implies that parallelizing the optimal rotating algorithm over the network nodes is beneficial.

The transmission of digitized images over limited bandwidth channels motivates the use of data compression techniques. Many data compression techniques are not suitable for such applications because compression ratios of more than 20:1 are often required. One technique that can provide this level of compression is vector quantization. The processes of codebook generation and, especially, encoding and decoding are tasks well suited for execution on a massively parallel machine. For codebook generation, an SIMD algorithm is developed whose control flow is based on sequencing through the training data, rather than the tree structure, to achieve improved performance. Results from execution on the 16384 processor MasPar MP-1 SIMD machine are presented. The approaches taken could be adapted for other SIMD as well as MIMD machines.

The problem of how to optimally traverse a spray applicator around a surface to be coated is formulated as a type of optimization problem known as a constrained variational problem. An optimal trajectory for a spray applicator is defined to be one that results in minimal variation in accumulated film thickness on the surface. For each surface point and for each feasible position and orientation of the applicator, a value for the instantaneous rate of film accumulation is assumed to be known. Empirical data and/or estimates for these values can be readily incorporated in the formulation. By making realistic approximations, the proposed constrained variational problem is transformed into a finite dimensional constrained optimization problem. Numerical studies are included that illustrate the utility of the problem formulation and the effectiveness of applying standard nonlinear programming techniques for determining solutions.>

A performance metric called receptivity is introduced for quantifying the degree of concurrent communication possible in high-speed wide area networks (WAN's). Given a stochastic demand pattern model, receptivity is defined to be the probability that all requested connections can be established concurrently. Because calculation of the exact value of receptivity is shown to (generally) have an exponential complexity, an analytic estimate for its value is derived. The derived estimate is dependent on network parameters such as the number of links, link capacity values, and a weighted hop distance metric (which depends on the topological structure of the network and its relationship to parameter values of the stochastic model for the demand patterns). The derived estimate for the proposed metric compares reasonably well with simulated values for several asymmetric topological structures ranging from planar meshes to random graphs. The utility of the estimate is twofold. First, it can be computed quickly, i.e., in polynomial time. Second, its simple analytic form provides the network architect with insight into some of the inherent limitations and consequences associated with topological design choices for high-speed WAN's.>

A distributed algorithm is presented that can be used to solve the single-destination shortest path (SDSP) problem or the all-pairs shortest path (APSP) problem for a class of clustered data networks. The network graph is assumed to be characterized with a balanced hierarchically clustered (BHC) topology. The BHC topology is introduced in this paper and is shown to be a realistic characterization for a large class of interconnected data networks. For certain types of BHC topologies, the SDSP problem can be solved with computation and communication time complexities of O(log n), assuming one processor is available at each of the n number of nodes. Assuming p processors are available at each node, computation and communication time complexities of O((n/p) log n) and O(n log n) are achievable, respectively, for solving the APSP problem. It is also shown that the algorithm converges in an asynchronous environment.>

A network performance measure, called receptivity, is introduced which quantifies a computer network's ability to accommodate concurrent communication. Receptivity is basically defined as the probability that a rejection of a communication request does not occur, i.e., it is the probability that the network will be receptive to all expected concurrent communication requests. A graph-theoretic result is derived which places upper bounds on the maximum number of concurrently communicating origin-destination pairs which a given computer network can accommodate. The bound is dependent on several important network parameters including the number of network links, the maximum link capacity, and a measure of the network's average minimum hop distance. The upper bound result is used as a basis for estimating receptivity. The estimate for receptivity compares favorably with simulated values of receptivity for several example networks.>

A distributed algorithm is presented which finds the shortest path from every node in the network to a given destination node. The network topology is assumed to be organizable into a generalized balanced-tree hierarchy (BH). The BH topology is introduced and characterized, and it is shown that most large interconnected data networks are of this type. It is also shown that the algorithm converges in an asynchronous environment. Therefore, some of the difficulties associated with synchronizing the order of events can be avoided in the actual implementation of the proposed algorithm.>