Neuromorphic computing is becoming common in diverse systems, including time-sensitive, real-time systems. This requires that large data sets be processed quickly with low latency. A stream processing architecture helps achieve this goal by beginning processing as soon as samples are received. In this paper, to achieve a low-latency implementation, neurons are parsed into fine-grain operations and scheduled onto stages of the pipeline. Wide datapaths that process multiple samples in each stage of the pipeline greatly improve throughput and latency. Also, the sparsity of partially connected neural networks allows proposed schedulers to further decrease latency. These schedulers use 'greedy' heuristics based on data dependencies to develop a reduced latency schedule. The schedulers were testing against sets of 1000 partially-connected neural networks, with sets ranging in number of layers from three to fifteen. The set of heuristics developed showed reductions of up to 67% over a sequential schedule.

Diagnosing and solving problems in a contemporary data-center can be a daunting task. By merging network topology information with state collection, this poster abstract explores a new way to look at the network monitoring and troubleshooting problem. Abstracting the entire network as an entity simplifies the debugging process, making possible comprehensive root-cause analysis and exonerating the network administrator from dealing with many devices, delivering gains in productivity and efficiency. Such an amalgamation allows the translation of a performance query expressed in a domain specific language to small pieces of code operating on different devices in the network collecting necessary state. This merging results in lesser overhead per switch and reduces the strain on devices and provides a simple abstraction to the administrator.

The ever changing nature of network technology requires a flexible platform that can change as the technology evolves. In this work, a complete networking switch designed in OpenCL is presented, identifying several high-level constructs that form the building blocks of any network application targeting FPGAs. These include the notion of an on-chip global memory and kernels constantly processing data without the intervention of the host. The use of OpenCL is motivated by the ability to rapidly change designs and to be maintainable by a wider developer community. Pieces of the design that cannot be realized using current OpenCL technology are also identified and a solution to the problem is presented.

Processing of parallel data streams requires permutation units for many algorithms where the streams are not independent. Such algorithms include transforms, multi-rate signal processing, and Viterbi decoding. The absolute order of data elements from the permutation is not important, only that data elements are located correctly for the next processing step. This paper describes a method to find permutations that require a minimum amount of memory and latency. The required permutations are generated based on the data dependencies of a computation set. Additional constraints are imposed so that the parallel streaming architecture processes the data without flow control. Results show agreement with brute force methods, which become computationally infeasible for large permutation sets.

Streaming architectures are a popular choice for data intensive application due to their high throughput requirements. When assembling components for a streaming application, it is often necessary to build translation blocks between them to match the ordering of the data elements required for the subsequent processing. This paper addresses this need by developing a technique that realizes arbitrary permutations in a streaming architecture. It is parametrized to accommodate any size data sequence and streaming width. This technique is applied to an architecture that receives continuous input at a rate of k elements per clock cycle, and after an initial start-up latency, outputs continuously at the same rate. In addition, the memory usage and latency through the memory array is minimized. This design is evaluated for permutations parametrized by size and stream width in terms of the memory elements and depths required. The class of stride permutation is considered for specific experimental evaluation. On average, this technique and architecture has only half the latency and requires half the memory of other techniques.

This paper presents a Zynq capable version of GNU Radio - an open-source rapid radio deployment tool - with an enhanced flow that utilizes the processing capability of FPGAs. This work features TFlow - an FPGA back-end compilation accelerator for instant FPGA assembly. The Xilinx Zynq FPGA architecture integrates the FPGA fabric and CPU onto a single chip, which eliminates the need for a controlling host computer; thus, providing a single, portable, low-power, embedded platform. By exploiting the computational advantages of FPGAs in the GNU Radio flow, a larger class of software defined radios can be implemented. Once the FPGA is programmed with a design, modules can be parameterized to realize an even larger class of applications and further solidify the concept of rapid assembly of software defined radios.

High-level FPGA synthesis tools aim to increase the productivity of FPGAs and to adopt them among software developers and domain experts. OpenCL is a specification introduced for parallel programming across heterogeneous platforms. In this paper, an automated compilation flow to generate customized application-specific hardware descriptions from OpenCL computation kernels is reported. The flow uses Xilinx AutoESL tool to obtain the design specification for OpenCL kernel cores. The provided architecture integrates generated cores with memory and OpenCL host application interfaces. The host program in the OpenCL application is compiled and executed to demonstrate a proof-of-concept implementation towards achieving an end-to-end flow that provides abstraction of hardware at the front-end.

In the current era of big-data computing, most non-engineer domain experts lack the skills needed to design FPGA-based hardware accelerators to address big-data problems. This work presents bFlow, a development environment that facilitates the assembly of such accelerators, specifically those targeting FPGA-based hybrid computing platforms, such as the Convey HC series. This framework attempts to address the above problem by making use of an abstracted, graphical front-end more friendly to users without computer engineering backgrounds than traditional tools, as well as by accelerating bitstream compilation by means of incremental implementation techniques. bFlow's performance, usability, and application to big-data life-science problems was tested by participants of an NSF-funded Summer Institute organized by the Virginia Bioinformatics Institute (VBI). In about one week, a group of four non-engineering participants made significant modifications to a reference Smith-Waterman implementation, adding functionality and scaling theoretical throughput by a factor of 32.

No abstract available.

This paper presents bFlow, an FPGA development framework for the rapid prototyping and implementation of hardware accelerators for hybrid computing platforms. This framework makes use of an abstracted, graphical front-end usable by those without computer engineering backgrounds, as well as an accelerated back-end that speeds up compilation times, increasing turns-per-day. bFlow's performance, usability, and application to the acceleration of big-data life-science problems verified by participants of the NSF-funded Summer Institute organised by the Virginia Bioinformatics Institute (VBI). In less than two weeks, a group of four non-computer science/computer engineering participants made modifications to a reference Smith-Waterman implementation, adding functionality and scaling throughput by a factor of four to 600 million base pairs per second.

This paper presents an alternative FPGA design compilation flow that reduces the back-end time required to implement a design. Beginning with the GReasy front-end and proceeding through the TFlow back-end, this flow consists of a rapid method for design assembly, decoupled from the vendor tools. This enables software-like turnaround time for faster prototyping and increased productivity.

This paper describes an alternative FPGA design compilation flow to reduce the back-end time required to implement a Xilinx FPGA design. Using a library of precompiled modules and associated meta-data, bitstream-level assembly of desired designs can occur in a fraction of the time of traditional back-end tools. Modules are bound, placed, and routed using custom bitstream assembly with the primary objective of rapid compilation while preserving performance. Since vendor tools are not needed for assembly, compilation can be performed in embedded and/or untethered environments. As a result, large device compilations can be assembled in seconds. This turbo flow (TFlow) enables software-like turn-around time for faster prototyping and increased productivity.

In the current era of big-data computing, most non-engineer domain experts lack the skills needed to design FPGA-based hardware accelerators to address big-data problems in their fields. This work presents bFlow, a development environment that facilitates the assembly of such accelerators, specifically those targeting FPGA-based hybrid computing platforms, such as the Convey HC series. This framework attempts to address the above problem by making use of an abstracted, graphical front-end more friendly to users without computer engineering backgrounds than traditional, HDL-based design environments, as well as by accelerating bitstream compilation by means of incremental implementation techniques. bFlow's performance, usability, and application to big-data life-science problems were tested by participants of an NSF-funded Summer Institute organized by the Virginia Bioinformatics Institute (VBI). In about one week, a group of four non-engineering participants made significant improvements to a reference Smith-Waterman implementation, adding functionality and scaling theoretical throughput by a factor of 32.

In this article, the RapidRadio framework for signal classification and receiver deployment is discussed. The framework is a productivity-enhancing tool that reduces the required knowledge base for implementing a receiver on an FPGA-based SDR platform. The ultimate objective of this framework is to identify unknown signals and to build FPGA-based receivers capable of receiving them. RapidRadio divides the process of radio creation into two phases; the analysis phase and radio synthesis phase. The analysis phase guides the user through the process of classifying an unknown signal and determining its modulation scheme and parameters, resulting in a radio receiver model. In the second phase, this model is transformed into a functional receiver in an FPGA-based platform.

We present and describe Torc - (Tools for Open Reconfigurable Computing) - an open-source infrastructure and tool set, provided entirely as C++ source code and available at http://torc.isi.edu. Torc is suitable for custom research applications, for CAD tool development, and for architecture exploration.

The programmable interconnection resources are one aspect that distinguishes FPGAs from other devices. The abundance of these resources in modern devices almost always assures us that the most complex design can be routed. This underutilized resource can be used for other unintendedpurposes. One such use, explored here, is to concatenate large networks together to form pseudo-equipotential geometric shapes. These shapes can thenbe evaluatedin terms of their abilitytoradiate(modulated)energyoffthechiptoanearby receiver. In this paper, an unconventional method of building such transmitters on an FPGA is proposed. Arbitrary shaped antennas are created using a unique flow involving an experimental router and binary images. An experiment setup is used to measure the performance of the antennas created.

This work presents an Embedded Routing Database (ERDB), which contains the complete description of the inter-tile routing shapes available in various Xilinx FPGA tiles, and the mapping of Programmable Interconnection Point (PIP) bits within the FPGA configuration bit stream. ERDB provides the RC system with knowledge of its own architecture and facilitates RC systems in implementing autonomic (self-managing and adaptive) computing. ERDB also protects the integrity of the RC system and supports design Intellectual Property (IP) protection. The paper describes the automated generation of a size-optimised ERDB (3.7 MB memory footprint for the Virtex-5 LX50T device) and its application within the Secure Reconfiguration Controller (SeReCon), as a minimised FPGA fabric description for on-line verification of IP core's integrity during partial reconfiguration. Results demonstrate the feasibility and accuracy of the SeReCon/ERDB-based design (IP core) routing verification that, when applied to an example IP block, detects >99% of the configured PIPs.

Orthogonal Frequency Division Multiplexing (OFDM) can provide a flexible usage of the spectrum by controlling individual sub carriers. Sets of sub carriers can be zero-modulated to avoid interfering narrowband primary users, making OFDM a strong candidate for Cognitive Radio implementations. This paper presents the design and implementation of a non-contiguous OFDM physical layer (PHY) capable of supporting arbitrary allocation vectors and spectrum sensing for cognitive radio applications. Least squares methods applied on an arbitrary set of pilot sub carriers are used to estimate and track the phase errors caused by residual carrier frequency offset and by non-ideal sampling frequency at the receiver. A full FPGA prototype was developed and evaluated using Virtex-4 devices, including over-the-air testing in the 2.05 GHz radio band.

No abstract available.

In an engineering perspective, agility is one property that a designer must consider when creating a product that is expected to undergo change throughout its lifetime. For embedded computing systems, traditionally the system hardware is fixed, and the system software provides the means of achieving agility. Altering software functionality is relatively easy to do, and software compile times are fast. There are situations, however, where for performance reasons, agility beyond software is needed. In theory, FPGAs offer a degree of agility to system hardware through the mechanism of altering functionality under software control. In practice, however, FPGAs are not very agile at all, requiring long design times and complicated compilation processes. In this talk, the use-model of contemporary FPGAs is reexamined, and alternative ways of hardware/software interaction are presented with the objective of achieving a higher degree of hardware agility.

More than a dozen Wireless @ Virginia Tech faculty are working to address the broad research agenda of cognitive radio and cognitive networks. Our core research team spans the protocol stack from radio and reconfigurable hardware to communications theory to the networking layer. Our work includes new analysis methods and the development of new software architectures and applications, in addition to work on the core concepts and architectures underlying cognitive radios and cognitive networks. This paper describes these contributions and points towards critical future work that remains to fulfill the promise of cognitive radio. We briefly describe the history of work on cognitive radios and networks at Virginia Tech and then discuss our contributions to the core cognitive processing underlying these systems, focusing on our cognitive engine. We also describe developments that support the cognitive engine and advances in radio technology that provide the flexibility desired in a cognitive radio node. We consider securing and verifying cognitive systems and examine the challenges of expanding the cognitive paradigm up the protocol stack to optimize end-to-end network performance. Lastly, we consider the analysis of cognitive systems using game theory and the application of cognitive techniques to problems in dynamic spectrum sharing and control of multiple-input multiple-output radios.

The difficult aspect of hardware reconfiguration is not creating the computational blocks, which are generally available from FPGA vendors and third parties, but linking the blocks in a manner that suits each application's unique connectivity, bandwidth, and latency requirements. Our approach uses the standard Xilinx implementation tools to generate dynamic module partial bitstreams, but choosing the module's coordinates and completing connections to other modules are runtime operations. Scripts automatically add interface wrappers to dynamic modules and generate a library of relocatable partial bitstreams. The library is used by an efficient runtime system that completes application requests for instancing and connecting modules, effectively insulating the designer from FPGA reconfiguration complexities. In this way, a large sandbox may be allocated to dynamic modules rather than fixed module slots and interconnect. Application engineers interact with the Wires on Demand (WoD) system through a runtime software API, and do not have to master hardware description languages and implementation tools.

While there have been many reported implementations of networks-on-chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication on an FPGA is already costly due to the die resources and time delays inherent in the reconfigurable structure. Layering another general-purpose network on top of the reconfigurable network simply incurs too many performance penalties. There is, however, already a largely unused, global network available in FPGAs. As a proof-of-concept, we demonstrate that the Xilinx FPGA configuration circuitry, which is normally idle during system operation, can function as a relatively high-performance NoC. MetaWire performs transfers through an overclocked Virtex-4 internal configuration access port (ICAP) and is shown to provide a bandwidth exceeding 200 MBytes/sec.

It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents a dynamic router for Xilinx FPGAs, designed to run on stand-alone embedded systems. With information obtained from Xilinxpsilas XDL tool, a compact routing database for the Virtex-II/IIP/4 devices is built which only requires 96 KB of storage. A channel routing algorithm is used because of its deterministic execution time and because all routing resources in the channel are available. Sample channels are routed with the router and compared with the Xilinx PAR tool. Improvements in both execution time and in memory usage of several orders of magnitude are observed.

Nodes in sensor fields and in autonomous swarms of mobile robots need to communicate; this usually requires individual nodes to either consume a significant amount of energy, carefully position themselves, precisely align carrier phase, or use complex coding. We propose an alternative strategy of allowing multiple independent and mobile wireless transmitters to share the power-consumption burden by combining low-power transmissions into a unified higher-power transmission. This is not a distributed beamforming or space-time coding approach. Instead, all nodes simultaneously broadcast the same symbol on the same channel without using different code books and without aligning carriers. This paper describes modulation, synchronization, and node selection schemes which make this possible. It also covers both baseband and over-the-air test results.

Sensor networks can be used for various application areas such as health, military, and home. Research in collaborative methods and wireless communication has enabled the development of sensor networks. This paper presents a collaborative signal reinforcement scheme for sensor networks in which a cluster of mobile, independent and interchangeable nodes collaborate to send a message to a distant node. The presented scheme offers several advantages over contemporary solutions, including higher fault tolerance, power efficiency, scalability and lower complexity and cost. The primary emphasis of the paper is placed on a novel signal reinforcement modulation method that enables the collaborative scheme. Simulations are presented that validate this collaborative scheme. Furthermore, experimental results obtained from a laboratory hardware prototype are also presented in support of the presented methods.

In systems typified by software defined radio, existing flows for run-time FPGA reconfiguration limit resource efficiency when constructing a variety of datapaths. Our approach allocates a sandbox region in which modules from a library can be flexibly placed and interconnected. An efficient run-time framework makes use of lightweight placement and routing techniques to respond on-demand to application requests. Compile time tools automate the task of adding interface wrappers to modules, insulating the designer from reconfiguration details.

This paper presents ADB, an alternate wire database, suitable for routing, tracing, and browsing in Xilinx Virtex, Virtex-E, Virtex-II, and Virtex-II Pro FPGAs. While mainstream design flows and place-and-route tools make good use of available routing resources, they often do so at the cost of comparatively large processing times. An alternative scheme is to modify or generate configuration bitstreams directly, in order to achieve more dynamic designs and to reduce processing times and memory footprints. ADB includes a complete set of compact wire databases for the indicated families, and can generate the necessary bitstream configurations with the help of JBits or an independent bitstream interface. These wire databases can also be used in standalone mode to facilitate routing research in situations where real device data might not normally be available.

Modular arithmetic is typically the computational bottleneck in a hardware implementation of public key cryptography algorithms. This paper focuses on an implementation of modular multiplication on the Quicksilver COSM adaptive computing machine as a run-time-reconfigurable user authentication context candidate. The design is targeted specifically to the COSM adaptive computing machine, taking into account the underlying architecture of the device.

Future surveillance operations will require easily deployable "microsensors" that are capable of autonomous detection and identification of objects. These devices will operate under severe limitations on energy consumption, to enable battery-powered operation. They will assess sensor inputs locally, transmitting data only after objects of interest have been detected and extracted from sensor data. This paper describes a prototype system that detects and tracks moving objects in image sequences obtained from an infrared video camera. Computation in the system is distributed across an FPGA and a DSP chip. The current system analyzes input images, in search of objects that meet predefined criteria. If these criteria are met, the system extracts a sub-image (or "chip") that contains an object of interest, and then transmits that to a central site for manual review and further analysis.

A new architecture for Golomb ruler derivation has been developed so that rulers up to 24 marks can be proven on it. In this architecture, 8-mark stubs that are derived on a personal computer are subsequently processed by the FCCM, called GE2, allowing for parallel processing of as many stubs as are the available FPGAs. Actual runs of the new design have been performed on the TOP parallel FPGA machine at Virginia Tech. This paper presents the design improvements over the original architecture, which include single FPGA implementation, hardware/software codesign, FIFO based I/O, design for parallel execution, and performance results from actual runs.

The evolution of computer networking technology will likely require hardware that is flexible enough to adapt to changing standards while maintaining the highest possible performance. Much research has recently been done in active networks, which increase network flexibility by allowing the routers to be reprogrammed, often at the cost of lower throughput. A reconfigurable router implemented on a Custom Computing Machine (CCM) can provide the flexibility required for active networking while approaching the high throughput of inflexible application-specific integrated circuit (ASIC)-based routers. This paper presents an implementation of a prototype reconfigurable router on the Wildforce platform. The prototype implements IPv4 routing with a throughput of up to 576 Mbps, using a stream-based approach that facilitates dynamic reconfiguration.

Many applications require the use of multiple, loosely-coupled adaptive computing boards as part of a larger computing system. Two such application classes are embedded systems in which multiple boards are required to physically interface to different sensors/actuators and applications whose computational demands require multiple boards. In addition to the adaptive computing boards, the computing systems for these application classes typically include general-purpose microprocessors and high-speed networks. The development environment for applications on these large computing systems is not unified. Typically, a developer uses VHDL simulation and synthesis tools to program the FPGAs on the adaptive computing boards. External control for the board, such as downloading new configurations or setting clock speeds, is provided through a vendor-specific API. This API is typically accessed in a C host program that the developer must write in a high-level language environment. Finally, the developer is responsible for writing the networking code that allows interaction between the separate adaptive computing boards and general-purpose microprocessors. No tools are available for either debugging or performance monitoring in this agglomerated system. Development on these systems is time-consuming and platform-specific. A standard ACS API is proposed to provide a developer with a single API for the control of a distributed system of adaptive computing boards, including the interconnection network.

Flexible and fast routers are generally considered a contradiction in terms since maintaining high-throughput requires fast but fixed-configuration application specific integrated circuits (ASICs) while flexibility requires slower but flexible configuration of general-purpose processors. A configurable stream-based reconfigurable router is a fast, flexible solution that includes the best features of both hardware and software processing through the efficient use of field-programmable gate array (FPGA) technology, active VHDL, and hardware/software partitioning and scheduling algorithms. This paper discusses the architecture of the stream-based reconfigurable router and presents the design, implementation, and evaluation of a prototype reconfigurable router.

Custom Computing Machines (CCM's) have demonstrated significant performance advantages over general-purpose processors for certain classes of problems. However, problems can always be found which require computational resources in excess of those available on a particular CCM. Exploiting the reconfigurable nature of FPGAs can alleviate this limitation. The FPGAs' computational resources can be time multiplexed to allow different portions of the computation to execute in stages. Intermediate results are saved to memory and passed on to later stages of the computation. This technique is used in this work to implement an image interpolation engine on the Xilinx XC6264 Reference Board. The engine utilizes 2-5-2 splines to take advantage of their computationally convenient powers-of-two arithmetic.

Software radios have emerged as important tools in the development of new signal processing algorithms, networking protocols, and propagation experiments in wireless environments. With a software radio, the signal processing and modem management can be changed in a timely matter. This enables users to explore a variety of domains before committing a design to silicon. Contemporary DSP-based software radios have proven indispensable in the wireless research community. The capabilities of these platforms, however, are somewhat limited due to the confined computational capacity of current DSPs. This paper presents a stream-based CCM soft radio consisting of a variety of FPGAs, memories, and a programmable radio interface, providing a pathway from antenna to wired network. CCM techniques are well suited for the computations associated with wireless modem management, and provide a substantial computational margin over contemporary alternatives, allowing live experiments using advanced digital signal processing.

This paper presents an approach for implementing a scalable high-performance digital filter using the WILDFORCE configurable computing platform. Although not designed specifically for signal processing, configurable computing platforms offer more flexibility for algorithms than application-specific hardware, which is often needed for instances when factors such as environment or product volume dictate alterations in computing. The added flexibility enables users to construct deep pipelines to exploit properties of specific computations. In this paper, wide 32-bit floating-point arithmetic operators have been implemented which provide compatibility with hosts machines. The filter achieves 160 MFLOPs on a single WILDFORCE configurable computing platform.

The wormhole run-time reconfiguration (RTR) computing paradigm is a method for creating high performance computational pipelines. The scalability, distributed control and data flow features of the paradigm allow it to fit neatly into the configurable computing machine (CCM) domain. To date, the field has been dominated by large bit-oriented devices whose flexibility can lead to lowered silicon utilization efficiencies. In an effort to raise this efficiency, the Colt CCM has been created based on the wormhole RTR paradigm. This paper outlines methods of implementation and performance for several common operations using these concepts. They serve as indicators of the diversity of algorithms that can be instantiated through the high-speed run-time reconfiguration that these devices make possible. Particular attention is paid to floating point multiplication. Also discussed is the topic of data dependent computation which would seem to be counter intuitive to the wormhole RTR paradigm. The paper concludes with a summary of performance of the three computations.

Configurable Computing Machines (CCMs) are an emerging class of computing platform which provide the computational performance benefits of ASICs, yet retain the flexibility and rapid reconfigurability of general purpose microprocessors. In these platforms, computational "hardware" is essentially swapped in and out of the platform as needed, much like paging in virtual memory systems. For an efficient platform, the swapping of the computational hardware (referred to as Run-Time Reconfiguration, or RTR) must be rapid. Thus far, the means of altering the configuration of CCMs has relied on global control strategies that present a fundamental bottleneck to the potential bandwidth of configuration information flowing into the CCM. Wormhole Run-time Reconfiguration is presented as a distributed control methodology that is applicable not only to the problem of device-level CCM reconfiguration, but to system-wide concurrent computing as a whole. The Virginia Tech Colt/Stallion integrated circuits are computational FPGAs incorporating Wormhole RTR concepts, and are discussed as a case study. Keywords: Configurable computing, FPGA, digital signal processing, data flow, VLSI 1.

Sound preparation for a career in computing systems design includes articulation in computer architecture and organization, compiler design, and operating systems. Contemporary instructional approaches towards this collective topic address each of the components in isolation. When taught in isolation, the interaction and trade-offs between the system hardware and the system software, while being critical factors for determining system performance, may not be adequately stressed. This paper presents a course structure which combines computer architecture, computer design, and system software design to convey the principals of constructing contemporary general-purpose computing solutions. Rapid prototyping technology is utilized in the laboratory component of the course for implementing full-custom processors, which are used as platforms for executing and evaluating prototype software.

The increasing size and speed of modern FPGAs allow complex computations, on the order of an average sized program, to be performed in a small collection of processing elements. It is well documented that the execution of large sections of a program within the "virtual hardware" offered by an attached FPGA processor can provide substantial speedup over the ordinary execution within a sequential, general-purpose processor. Unfortunately, the development tools currently available for FPGAs do not allow for easily configuring multi-FPGA custom computing machines. Configuration of an FPGA architecture requires scheduling: the mapping of computations onto existing functional units. To take advantage of all available logic, computations may span processing elements, calling for partitioning of a subroutine between one or more FPGAs. In this paper, an architecture-independent design tool is presented for translating programs written in C to a dataflow representation and then efficiently scheduling and partitioning the resulting graphs onto multi-FPGA computing platforms.

Many algorithms rely on floating point arithmetic for the dynamic range of representations and require millions of calculations per second. Such computationally intensive algorithms are candidates for acceleration using custom computing machines (CCMs) being tailored for the application. Unfortunately, floating point operators require excessive area (or time) for conventional implementations. Instead, custom formats, derived for individual applications, are feasible on CCMs, and can be implemented on a fraction of a single FPGA. Using higher-level languages, like VHDL, facilitates the development of custom operators without significantly impacting operator performance or area. Properties, including area consumption and speed of working arithmetic operator units used in real-time applications, are discussed.

An explicit-duration hidden Markov model (HMM) algorithm for speech recognition has been proposed that potentially provides a more precise and versatile duration model than the implicit models ordinarily used, but at the cost of increased computation. The authors address the computational issues involved in conventional and explicit-duration HMM training by providing an analysis of the algorithm, suggesting serial enhancements and two efficient parallel implementations, and presenting experimental results on both common network workstations as well as a parallel system.>

Substantial gains can be achieved by allowing the configuration and fundamental operations of a processor to adapt to a user's program. A method is presented for improving the performance of many computationally intensive tasks by extracting information at compile-time to synthesize new operations that augment the functionality of a core processor. The newly synthesized operations are targeted to RAM-based reconfigurable logic located within the processor. A proof-of-concept system called PLADO, consisting of a C configuration compiler and a hardware platform, is presented. Computation and performance results confirm the concept viability, and demonstrate significant speed-up.>