Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to house hardware-based custom implementations of these kernels to speed up these applications. In this paper, we demonstrate a methodology for algorithm acceleration. We used SAR as a case study to illustrate the tremendous potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show an average speed-up of 188 when using the FPGA-based hardware accelerator as opposed to using a software implementation running on a typical general purpose processor.

The paper presents a medical image coding technique that is suitable for interactive telemedicine over networks. The new encoding scheme allows a server to transmit progressively only a part of a compressed image over a network as requested by a client. This technique is different from the region scalable coding scheme in JPEG 2000 since it does not require that a region of interest (ROI) be defined when encoding occurs. In our method, a medical image is encoded at full resolution and stored in the server. A user can receive a basic image at low resolution and then specify a ROI. The server can then provide full resolution for the ROI. Our technique allows a user to select the ROI after the compression has been done. We employ integer wavelet lifting to support lossless coding for medical images that strictly require lossless compression. The paper shows the benefits of the proposed technique with examples and simulation results.

This paper is an extension of our previous paper to improve the capability of detecting corners. We proposed a method of boundary smoothing for curvature estimation using a constrained regularization technique in the previous paper. We propose another approach to boundary smoothing for curvature estimation in this paper to improve the capability of detecting corners. The method is based on a minimization strategy known as mean field annealing which is a deterministic approximation to simulated annealing. It removes the noise while preserving corners very well. Thus, we can detect corners easier and better in this approach than in the constrained regularization approach. Finally, some matching results based on the corners detected by corner sharpness in the mean field annealing approach are presented as a demonstration of the power of the proposed algorithm.

Many digital signal and image processing algorithms can be speeded up by executing them in parallel on multiple processors. The speed of parallel execution is limited by the need for communication and synchronization between processors. In this paper, we present a paradigm for parallel processing that we call the block data flow paradigm (BDFP). The goal of this paradigm is to reduce interprocessor communication and relax the synchronization requirements for such applications. We present the block data parallel architecture which implements this paradigm, and we present methods for mapping algorithms onto this architecture. We illustrate this methodology for several applications including two-dimensional (2-D) digital filters, the 2-D discrete cosine transform, QR decomposition of a matrix and Cholesky factorization of a matrix. We analyze the resulting system performance for these applications with regard to speedup and efficiency as the number of processors increases. Our results demonstrate that the block data parallel architecture is a flexible, high-performance solution for numerous digital signal and image processing algorithms.

This paper presents an approach to using commercial digital signal processors to develop a high performance multiprocessing system for block data processing. We use a restricted dataflow multiprocessor architecture and block data processing to achieve high performance. We call this architecture the Block Data Flow Architecture (BDFA). Block data processing algorithms for many applications have been developed by other researchers. Although many of these algorithms were developed for single processor systems, the algorithms can be mapped onto the BDFA because of its inherent support for block data processing. This paper highlights a few of these algorithms and presents the BDFA as a high performance architecture to implement these algorithms. In addition, we evaluate the potential of using Texas Instruments' TMS320C40 (C40) as a node processor in the BDFA.

This paper presents a method of optimal boundary smoothing for curvature estimation and a method of corner detection for consistent representation of objects for computer vision applications. The existing methods for curvature estimation have a common problem in determining a unique smoothing factor. We propose a constrained regularization (CR) approach to overcome that problem. The curvature function computed on the preprocessed boundary, which is obtained by the CR approach, gives consistent corner detection results. Ideal corners rarely exist for a real boundary. They are often rounded due to the smoothing effects of the preprocessing. In addition, a human recognizes both sharp corners and slightly rounded segments as corners. Hence, we establish a criterion, called "corner sharpness", which is qualitatively similar to a human's capability to detect corners.>

An adaptive filter that addresses the problems of convergence to a stable filter, the optimization of multimodal performance surface, and the computational complexity of implementing an infinite impulse response (IIR) filter is described. The adaptive filter is based on describing the adaptive IIR filter in its state space form. The adaptive state space filter algorithm can best be described as a recursive form of the matrix minimum principle. The adaptive state space is a two-part algorithm. The first part is a recursive algorithm for optimizing a predictor matrix which describes the transformation from past data to future data. The second part determines the system parameters from the optimized predictor matrix by the decomposition of the predictor matrix and the use of projection techniques. Assurance of convergence to a stable filter is also proven.>

Computing a curvature function on a digitized boundary is an ill-posed problem due to the discrete nature of the boundary. The authors use a constrained regularization technique to obtain the optimal smooth boundary before computing the curvature function. A corner sharpness is defined for robust corner point detection. Matching results in the presence of occlusion using a 2-D Hopfield neural network are also shown to produce excellent results using this boundary representation. The human cognition system recognizes both ideal corner points and slightly rounded segments as corner points. A criterion to mimic a human's capability of detecting corner points and to compensate for the smoothing effect of the preprocessing in detecting corner points in the curvature function space is established.>

The authors study sampling errors in perfect reconstruction transmultiplexers using QMFs (quadrature mirror filters), conjugate QMFs, and a matrix formalism. They derived an expression for the total spectral leakage as a function of sampling error at the receiver. Simulation results are in close agreement with previously published experimental data. This expression was to detect and correct the sampling errors. Thus, it was possible to preserve the perfect reconstruction property even in the presence of sampling errors. It was observed that the ratio of the crosstalk energy to the main received energy is not a very good measure of the system performance and the reconstructed signal suffers from crosstalk more than indicated by this ratio when the sampling error is increased.>

An analysis is made of the mean square error for the fast least mean square (LMS)-sine algorithm. It is shown that during the very early stages of adaptation the mean square error increases to accommodate the transients which take place in the weight updates. At steady state, the mean square error obtained is much less than that for the classical LMS algorithm due to a reduction in the misadjustment error. It is also shown through simulations that the behavior of the error is as anticipated by the analytical results.>

The authors present a new algorithm for computing the initial state of a N-D DLSI system. The algorithm is based on suppression of any transients due to initial conditions and can be applied to initialize 1-D and 2-D systems as well. They present a 1-D example on the use of the algorithm to show its effectiveness, and also successfully use the algorithm for suppressing transients associated with the implementation of spatial domain filters.>

An analytical derivation is presented of the stability conditions for the fast transversal filter (FTF) implementation of the recursive least-squares (RLS) adaptive filter algorithm. It is shown that the rescue variable should be less than a threshold value that is derived. Simulation results are reported which confirm that the derived rescue variable can be used to ensure the stability of the RLS adaptation algorithm.>

The authors present a high-performance VLSI architecture for two-dimensional (2-D) digital signal processing applications. The architecture uses a specially designed digital signal processor (DSP) as a node in a multiprocessor system for real-time or near-real-time 2-D signal processing. The DSP is custom-designed and has a throughput of two multiplications and three additions in a single cycle. It has wavefront-array-processor properties and operates asynchronously in a multiprocessor system. This architecture extends the concept of using a single processor to the use of a multiprocessor system.>

This paper describes two methods of constructing multidimensional block systems and polyphase networks from a given scalar system. The stability of the block system is also investigated. It is shown that the poles of the block system are closer to the origin than the poles of its scalar counterpart. Moreover, the scalar transfer function can be derived from the block transfer function. Finally, we show that the scalar and block systems have the same overall input-output map although the properties and architectures of the systems are quite different.

In this paper, a generic computational primitive is developed for the implementation of any arbitrary order one-dimensional or two-dimensional FIR or IIR digital filter. This computational primitive can form the basis for a single chip processor for one-dimensional and two-dimensional digital signal processing. A multiprocessor architecture for real-time implementation of spatial domain filters is developed with each processing unit in the network implementing the computational primitive. This multiprocessor system has a simple control scheme, a simple interconnection network, a very high efficiency, and low data transfers and storage requirements. Thus, it avoids the bottlenecks associated with traditional parallel computers and multiprocessor systems.

An image may be considered to be a finite extent two dimensional sequence with truncation occuring at the edges of the image. The corresponding data set is equivalent to the product of a two dimensional rectangular window function and an infinite duration two dimensional function. The edge transients associated with data truncation can propagate throughout the output image when infinite impulse response spatial domain filters are used. These transient effects can completely obscure the output image with certain types of filters. This paper presents a technique which can be used to eliminate the edge transients associated with data truncation for spatial domain filter applications.