The main goal of this panel is to share survey data being collected on booming enrollments in computer science. Survey data are being collected from two source types: institutions and students. The institution data are being collected through both the CRA Taulbee Survey, which represents computer science departments in North America with doctoral degrees, and the ACM NDC Survey, which represents computer science departments at U.S. 4-year and master's universities and colleges. The student data are being collected via the Data Buddies Project, run by the CRA's Center for Evaluating the Research Pipeline. The institution data will allow us to answer questions such as "what 'boom' are institutions seeing and how are different types of institutions responding to this boom?" The student data will allow us to answer questions such as "why are students suddenly eager for our classes?". The survey data will help us understand (1) the intensity of the "boom" at different types of institutions, (2) how institutions are responding to the increasing demand for computing education, and (3) whether the current enrollment "boom" represents the "third bubble" or whether it is here to stay. The data will also allow us to ask questions that attempt to understand the impact of the boom on underrepresented students. Data collection is ongoing; we will present results "hot off the presses".

DMA transfer between a CPU and an FPGA often becomes a bottleneck of current reconfigurable machines. The DMA transfer of the machines like SRC-6 supports streaming processing with on-board memory interleaving, but as a pre-processing of the interleaving, the CPU must reorder the data for applications with severe FPGA resource constraints. This paper empirically evaluates this overhead to reveal the trade-off point. The results show that a speedup is achieved by interleaved streaming DMA when 150KB or lower data strings are transferred.

No abstract available.

No abstract available.

This paper presents and discusses implementation of a barotropic operator used in ocean model simulation called Parallel Ocean Program (POP) using SRC-6 MAP. While a lot of high-end reconfigurable machines on which users can implement applications with a programming language are now available, enough implementation experience has not been accumulated for practical applications. In this paper, several implementation techniques accompanied by modification on original application source code are empirically evaluated and analyzed. The results show that appropriate use of internal memory and streaming DMA make 100 MHz FPGAs achieve comparative performance with GHz processors by using 100 MHz FPGAs.

This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This architecture is based on multiple FPGAs organized in a scalable direct network that is substantially more interconnect-efficient than currently used crossbar technology. In addition, we discuss several ancillary issues and propose solutions required to support this architecture and achieve maximal performance for general-purpose applications; these include supporting IP, mapping techniques, and routing policies that enable greater flexibility for architectural evolution and code portability

The authors propose an improvement to a limited resource Montgomery multiplier design, the MWR2MM algorithm proposed by Tenca and Koc, which is suitable for implementation on large FPGAs. The design can be scaled to utilize available FPGA multipliers, CLB logic and frequencies of operation

The RSA algorithm is the standard for public-key cryptography today, with Montgomery multiplication the most common mechanism of implementation due to modulo operations using a bitwise shift in place of a division operation. Several Montgomery designs have been proposed for ASIC and FPGA implementation based on limited resource availability to satisfy the computational burden. FPGAs are now available that have large configurable logic resources in addition to dedicated high-speed ALU logic for operations such as multiplication. This paper describes an improvement to a limited resource Montgomery multiplier design, the MWR2MM algorithm proposed by Tenca and Koc, which is suitable for implementation on large FPGAs. The design can be scaled to utilize available FPGA multipliers, CLB logic and frequencies of operation. Implementation and design choices are discussed for an RSA core based on this design, and a comparison against the OpenSSL open source cryptographic library is given. Our results show a 1024-bit RSA core on a 100MHz Virtex2 Pro 100 FPGA platform to be 3.13x faster than an equivalent software implementation on a 2.8 GHz Intel Xeon PC workstation.

Benchmark one of the DARPA HPCS discrete mathematics suite for high productivity computing involves multiple precision arithmetic. The benchmark computes the product of two given N times N matrices whose entries are multiple precision integers, with the product being taken modulo another multiple precision integer M. The authors describe algorithms and methodologies for three implementations of this benchmark on SRC computers' SRC-6 reconfigurable platform and present performance results. The use of pipeline parallelism from inner loops, parallel code sections, and the two FPGA chips on the SRC hardware can speed up performance by as much as 20times compared to a software only implementation

The synergistic advances in high-performance computing and reconfigurable computing, based on field programmable gate arrays (FPGAs), has resulted in hybrid parallel systems of microprocessors and FPGAs. Such systems support both fine-grain and coarse-grain parallelism, and can dynamically tune their architecture to fit various applications. Programming these systems can be quite challenging as programming of FPGA devices can involve hardware design. This tutorial will introduce the field of reconfigurable supercomputing and its advances in systems, programming, applications and tools. Reconfigurable system developments at SRC, Cray, SGI, and Star Bridge will be highlighted, and case studies including full application developments will be presented along with the live demonstrations. This tutorial will be the first to show scalability studies for real-life applications over entire HPRC systems. This will reveal the tremendous promise held by this class of architectures in performance, power and cost improvements. Challenges that remain will be also discussed.

High-Performance Reconfigurable Computers (HPRCs) based on the combination of conventional processors and FPGAs have been gaining attention in the past few years. Their benefits were particularly harnessed in compute-intensive integer applications. However, there has been doubt that the same benefits can be attained for general scientific applications. Fortunately, the trend in reconfigurable chip sizes and diversity of resources may be relieving some of those concerns. Yet, with the hardware reconfigurability, it is feared that domain scientists have to learn how to design hardware if they were to use such machines effectively. In order to address the overarching question, this panel will address the following questions: Can FPGAs deliver order-of-magnitude performance gains in scientific floating-point applications in the foreseeable future? Can programming HPRCs programmability become similar to that of HPCs in its level of difficulty? What are the major developments in the industry or the community that make all this possible?

This paper describes the implementation and performance of PBPI, a parallel implementation of Bayesian phylogenetic inference method for DNA sequence data. By combining the Markov Chain Monte Carlo (MCMC) method with likelihood-based assessment of phylogenies, Bayesian phylogenetic inferences can incorporate complex statistic models into the process of phylogenetic tree estimation. However, Bayesian analyses are extremely computationally expensive. PBPI uses algorithmic improvements and parallel processing to achieve significant performance improvement over comparable Bayesian phylogenetic inference programs. We evaluated the performance and accuracy of PBPI using a simulated dataset on System X, a terascale supercomputer at Virginia Tech. Our results show that PBPI identifies equivalent tree estimates 1424 times faster on 256 processors than a widely-used, best-available (albeit sequential), Bayesian phylogenetic inference program. PBPI also achieves linear speedup with the number of processors for large problem sizes. Most importantly, the PBPI framework enables Bayesian phylogenetic analysis of large datasets previously impracticable.

The Defense Advanced Research Projects Agency (DARPA) has released high productivity computing systems (HPCS) benchmarks as specifications of performance required to solve important problems. This work reports on the design, implementation, and benchmarking of the benchmark number two, dynamic programming (DP), as developed in a general purpose reconfigurable computer. DP methods are used to solve DNA sequencing problems. DP has been also used successfully for optimal compression of barcode and other data, for control problems such as depth vision systems, and for chess endgames, among others. Clearly, it is helpful to know the application background; however, it is more important to note the benchmark is the product of a set of applications. Nonetheless it is intended to be developed and tested in a manner that is independent of any particular application.

We implement and report performance numbers of an entire molecular dynamics application in floating point on reconfigurable hardware achieving sustainable speedup and scaling with a novel technique based on adaptive processing elements.

The combination of traditional microprocessors workstations and hardware-reconfigurable field programmable gate arrays (FPGAs) has developed a new class of workstations known as reconfigurable computers, with several examples demonstrating significant speedups compared to standalone PC workstations alone. Several platforms implement PC-FPGA communication using common PC peripheral interface buses such as PCI-X. A new approach from SRC Computers implements a highspeed communication interface that increases the throughput compared to PCI interfaces. This paper demonstrates an efficient high-throughput implementation of IDEA encryption using the SRC platform. SRC design choices that influence both throughput and area are evaluated. Detailed analyses of FPGA resource utilizations, data transfer and reconfiguration overheads for the SRC system are provided, and a comparison between SRC and a public domain software implementation of IDEA are given.

Congruential sieves have been constructed as software programs or as physical devices for nearly a century. Factor stencils were used by D.N. Lehmer in his table of prime numbers constructed early in the 20th century, and a sequence of special purpose electrical, electro-mechanical, and electronic devices were built by D.H. Lehmer through the middle part of the century. More recently, special purpose sieves using FPGAs (field programmable gate arrays) have been built and programs on more generic reconfigurable computing machines have been written to implement sieves. We describe here a new implementation of a sieve on the Star Bridge Systems HC 36m reconfigurable computer.

Splash 2 is an attached parallel processor in which the computing elements are user-programmable FPGA devices. The architecture of Splash 2 is designed to accelerate the solution of problems which exhibit at least modest amounts of temporal or data parallelism. Applications are developed by writing descriptions of algorithms in VHDL, which are then iteratively refined and debugged within a simulator. Once an application is determined to be functionally correct in simulation, it is compiled to a gate list and optimized by logic synthesis. The gate list is then mapped onto the FPGA architecture by automatic placement and routing tools to form a loadable FPGA object module. A C language library and a symbolic debugger comprise the execution environment. The Splash 2 system has been shown to be effective on a variety of applications, including text searching, sequence analysis, and image processing.>

Article Free Access Share on Splash 2 Authors: Jeffrey M. Arnold View Profile , Duncan A. Buell View Profile , Elaine G. Davis View Profile Authors Info & Claims SPAA '92: Proceedings of the fourth annual ACM symposium on Parallel algorithms and architecturesJune 1992Pages 316–322https://doi.org/10.1145/140901.141896Published:01 June 1992Publication History 103citation663DownloadsMetricsTotal Citations103Total Downloads663Last 12 Months57Last 6 weeks9 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A special computer for high-precision arithmetic features an ALU that is dynamically reconfigurable under program control. The 256-bit ALU consists of 8 32-Mt slices each of which has its own ALU operation code in each microinstruction. The slices can remain logically separated from each other, or he dynamically connected to either or both of their neighbors under control of a segment control code that is part of each microinstruction. The micro-assembly language designed for the machine includes special features to assist in the control of the segmentation, data addressing, and control sequencing. Estimations of the times required to execute arithmetic operations on the machine show that it will be exceptionally fast for problems in computational number theory and factoring of integers.

Factoring, primality testing, and other problems of current interest [1, 2, 3, 4, 5, for example] in experimental number theory require machines with different architectures from those for any other application. Algorithms for such problems are small, but their execution requires high-speed arithmetic on very long integers interspersed with shorter precision computing that can conveniently be done by several processors acting in parallel. In this paper, we describe the preliminary design of a processor specifically for computational number theoretic problems. The primary component is a 256-bit ALU which is dynamically reconfigurable to provide for parallel independent operations on groups of 32-bit subwords within the 256-bit word.

We shall consider retrieval performance measures for generalized (non-Boolean) queries and indexing functions. The meanings of recall and precision in such a generalized system will be discussed. Finally, we shall explore the meaning and difficulty of using such measures to compare Boolean and non-Boolean retrieval systems.

Abstract There has been a good deal of work on information retrieval systems that have continuous weights assigned to the index terms that describe the records in the database, and/or to the query terms that describe the user queries. Recent articles have analyzed retrieval systems with continuous weights of either type and/or with a Boolean structure for the queries. They have also suggested criteria which such systems ought to satisfy and record evaluation mechanisms which partially satisfy these criteria. We offer a more careful analysis, based on a generalization of the discrete weights. We also look at the weights from an entirely different approach involving thresholds, and we generate an improved evaluation mechanism which seems to fulfill a larger subset of the desired criteria than previous mechanisms. This new mechanism allows the user to attach a “threshold” to the query term.