The increasing complexity of deep neural networks (DNNs) poses significant challenges for edge inference deployment due to resource and power constraints of edge devices. Recent works on unary-based matrix multiplication hardware aim to leverage data sparsity and low-precision values to enhance hardware efficiency. However, the adoption and integration of such unary hardware into commercial deep learning accelerators (DLA) remain limited due to processing element (PE) array dataflow differences. This work presents Tempus Core, a convolution core with highly scalable unary-based PE array comprising of tub (temporal-unary-binary) multipliers that seamlessly integrates with the NVDLA (NVIDIA's open-source DLA for accelerating CNNs) while maintaining dataflow compliance and boosting hardware efficiency. Analysis across various datapath granularities shows that for INT8 precision in 45nm CMOS, Tempus Core's PE cell unit (PCU) yields 59.3% and 15.3% reductions in area and power consumption, respectively, over NVDLA's CMAC unit. Considering a 16x16 PE array in Tempus Core, area and power improves by 75% and 62%, respectively, while delivering 5x and 4x iso-area throughput improvements for INT8 and INT4 precisions. Post-place and route analysis of Tempus Core's PCU shows that the 16x4 PE array for INT4 precision in 45nm CMOS requires only 0.017mm2die area and consumes only 6.2mW of total power. We demonstrate that area-power efficient unary-based hardware can be seamlessly integrated into conventional DLAs, paving the path for efficient unary hardware for edge AI inference.

Pseudo-Exhaustive Physically-Aware Region (PEPR) testing, in its most general application, rasterizes the layout of a logic circuit into overlapping three-dimensional regions of user-defined size. Faults that correspond to the exhaustive testing of each subcircuit within a region are defined and used for automatic test pattern generation (ATPG), fault simulation, and diagnosis. Evaluation of tens of thousands of chip failures demonstrated the effectiveness of PEPR in capturing the exact behavior of defects.However, deployment of PEPR is challenged by the large number of faults produced for exhaustively testing each region. Analysis revealed that there are a small percentage of regions that require a significant number of faults. For instance, a 14nm test chip contains regions that require more than 32M faults to test. While it is certainly possible to define a region size that produces large subcircuits, we found that large subcircuits predominantly result from including the entirety of a cell when a region simply intersects a small portion of the cell. To remedy this situation, we have developed IC-PEPR, a novel intra-cell extension to PEPR that significantly reduces the number of resulting faults. Specifically, by exploiting equivalence within a cell, intra-cell components within a region are controlled to all possible values without applying all cell-level input patterns. Applying IC-PEPR testing reduces the number of faults for a commercial benchmark circuit by more than 100X. This reduction in fault count results in a corresponding reduction in ATPG run time (almost 50X reduction) and test set size (>10X reduction).

Logic circuit diagnosis is an essential tool for improving manufacturing yield. However, there is a significant disparity between the behavior predicted by conventional fault models and the actual behavior observed in failing circuits. This undermines the performance of diagnosis methodologies that rely on conventional fault models to characterize defect behavior. Recently, a parameterizable test metric called PEPR has demonstrated the ability to precisely bound defect behavior, even when it deviates from conventional fault model assumptions. This paper describes a novel diagnosis methodology that uses the PEPR metric to determine (i) the physical location of a defect and (ii) the precise changes to the logic functionality of the affected circuit in the form of a custom fault model. The methodology, called CHEF, is applied to over 700 fail logs from a 22nm industrial test chip. Results demonstrate CHEF precisely characterizes defects that conventional diagnosis cannot, specifically when failure behavior does not align with a conventional fault model. Furthermore, CHEF achieves a significant increase in diagnostic resolution compared to conventional diagnosis, more than doubling the number of failures with a physical resolution better than 1µm2. Finally, diagnostic patterns generated by CHEF demonstrate the capability to further refine defect characterization.

Recently, companies such as Google, Meta (Facebook), and Microsoft reported in the mainstream press about seemingly random errors which, initially undetected ("silently"), had crept into their large cloud data centers. These reports mentioned that very specific instructions were intermittently incorrectly executed, propagated through the operating system, and would potentially manifest themselves as application-level errors. Are the root causes of these so-called silent data errors test escapes and/or reliability issues? Why are they only noticed now? Is that only the case because such large server farms bring together larger numbers of CPUs than ever seen before? And what counter measures can we take against them?

It is well-known that understanding the behavior of silicon failures is an essential step in yield learning. It is also becoming more important for producing high-quality silicon due to the increasing number of defects detected fortuitously. In order to meet this need, a new approach for extracting the precise faulty function from defective logic circuits is described. The approach is applied to nearly a 1,000 14nm failures and one use case of the results on improving ATPG is discussed.

General Matrix Multiply (GEMM) units, consisting of multiply-accumulate (MAC) arrays, perform bulk of the computation in deep learning (DL). Recent work has proposed a novel MAC design, Bit-Pragmatic (PRA), capable of dynamically exploiting bit sparsity. This work presents OzMAC (Omit-zero-MAC), a modified re-implementation of PRA, but extends beyond earlier works by performing rigorous post-synthesis evaluation against binary MAC design across multiple bitwidths and clock frequencies using TSMC N5 process node to assess commercial implementation potential. We demonstrate the existence of high bit sparsity in eight pretrained INT8 DL workloads and show that 8-bit OzMAC improves all three metrics of area, power, and energy significantly by 21%, 70%, and 28%, respectively. Similar improvements are achieved when scaling data precisions (4, 8, 16 bits) and clock frequencies (0.5 GHz, 1 GHz, 1.5 GHz). For the 8-bit OzMAC, scaling its frequency to normalize the throughput, it still achieves 30% improvement on both power and energy.

Debug of failing tests during new product introduction is a human-time-intensive task, requiring the focus of domain experts to develop and execute fact-finding experiments. In particular, complex failures in logic circuitry can be challenging to localize and characterize. The prior AAA (Automated, On-ATE AI) Debug Expert System operated on scan chain failures, using various debug methodologies to identify key information about the failure. This paper proposes Logic-AAA, an extension to AAA that uses the same framework to target failures in digital logic based on structural tests. Among the methods implemented in this system are failing flop identification for determining failure location, exhaustive backcone testing for determining failure behavior, and cross-voltage rail shmoo collection for determining test condition behavior. Logic-AAA can perform expert-like debug tasks in an automated fashion, which leads to significant resource savings and enables non-experts to perform complex debug.

A major task in chip design involves identifying the location and shape of each major design block/module in the layout footprint. This is commonly known as floorplanning. The first step of this task is known as global floorplanning and involves identifying a location for each module that minimizes wire length and leaves sufficient area for each module. Existing global floorplanning methods either have a non-convex problem formulation, or have trivial global solutions with no guarantee on the quality of the result. Here, we model the global floorplanning as a Semi-Definite Programming (SDP) problem with a rank constraint. We replace the rank constraint with a direction matrix and convexify the problem, whose solution is shown to be a global optimum if an appropriate direction matrix is chosen. To calculate the direction matrix, a convex iteration algorithm is used where the problem is decomposed into two SDP sub-problems. Furthermore, we introduce a series of techniques that enhance the flexibility, accuracy, and efficiency of our algorithm. Design experiments demonstrate that our proposed method reduces the average wirelength up to 20% for different benchmarks and outline aspect ratios.

Submitted to the Special Issue on Machine Learning for CAD (ML-CAD). Competitive strength in semiconductor field depends on yield. The challenges associated with designing and manufacturing of leading-edge integrated circuits (ICs) have increased that reduce yield. Test chips, especially full-flow logic test chips, are increasingly employed to investigate the complex interaction between layout features and the process that improves the total process quality before and during initial mass production. However, designing a high-quality full-flow logic test chip can be time-consuming due to the huge design space and complex process to search for optimal result. This work describes a new design flow that significantly accelerates the logic test chip design process. First, we deploy random forest classification technique to predict potential synthesis outcome for test chip design exploration. Next, a new method is described to efficiently solve the integer programming problem involved in the design process. Various experiments with industrial design have demonstrated that the proposed two methods greatly improve the design efficiency.

Recent reports indicate that existing fault models and test metrics result in substantial manufacturing test escapes that cause major system-level challenges such as silent data corruption resulting from incorrect computations. Such test escapes are often detected today after system deployment (e.g., in the field) using a variety of synthetic and application workloads. In this work, a new test metric is investigated for detecting defects that escape existing test approaches. PEPR (Pseudo-Exhaustive Physically-Aware Region) testing comprehensively analyzes both the physical layout and the logic netlist to identify single- or multi- output sub-circuits. The resulting sub-circuits are exhaustively tested to detect timing-independent combinational (TIC) defects. Analyses demonstrate that PEPR-based scan tests detect TIC defects perfectly (100%) when examining fail data from over 30,000 14nm failing chips. In contrast, existing fault models and test metrics might result in up to 95 % of TIC defects being detected fortuitously. Strategies for addressing increased test pattern count resulting from the pseudo-exhaustive nature of PEPR testing are also discussed.

The outsourcing of portions of the integrated circuit design chain, mainly fabrication, to untrusted parties has led to an increasing concern regarding the security of fabricated ICs. To mitigate these concerns a number of approaches have been developed, including logic locking. The development of different logic locking methods has influenced research looking at different security evaluations, typically aimed at uncovering a secret key. In this paper, we make the case that corruptibility for incorrect keys is an important metric of logic locking. To measure corruptibility for circuits too large to exhaustively simulate, we describe an ATPG-based method to measure the corruptibility of incorrect keys. Results from applying the method to various circuits demonstrate that this method is effective at measuring the corruptibility for different locks.

Debug of failing tests during new product introduction is a human-time-intensive task, requiring the focus of domain experts to develop and execute fact-finding experiments. With the increasing size and complexity of modern integrated circuit products, and the increasing size of company product portfolios, it is challenging and taxing for these few experts to support all required debug. To overcome this bottleneck of limited expertise, we propose AAA, a rule-based expert system to perform automated, on-the-tester debug of failing tests. The system is designed to replicate the typical procedure followed by an expert, including the dynamic creation and application of targeted debug tests, collection of on-tester silicon failure results, and analysis of the results to improve root-cause understanding. AAA performance is demonstrated on industrial chips with scan chain failures.

Logic diagnosis is a software-based methodology to identify the behavior and location of defects in failing integrated circuits, which is an essential step in yield learning. Conventionally, accurate diagnosis requires a sufficient amount of failing data, indicating a high test cost. Prior work that attempt to solve this problem either use a fixed pattern order, ignoring the characteristics of each chip, or require significant memory which leads to unacceptable increases in test cost. In this work, a new algorithm is described for dynamically selecting the test pattern order that leads to significant reduction in memory cost. Experiments using two industrial chips demonstrate the efficacy of the approach. Compared to prior work, the algorithm described in this work uses as little as 1/500 of tester space to store failing data.

Among various competing designs targeting similar functionality, the key differentiator typically consists of a small amount of custom Intellectual Property (IP). To protect this IP from reverse engineering, designers need effective solutions for hiding the unique aspects of their implementations. In this work, we introduce a general framework for partitioning the computation performed by a design into a part whose implementation is commonly known (and encountered across many designs), and a part which is unique to this design. The former can then be built using conventional techniques (including untrusted manufacturing facilities) while the latter needs to be protected using additional obfuscation techniques. The existence of several other known implementations of the (same or similar) target function serves as a decoy which deflects efforts seeking to reverse-engineer the unique implementation. We demonstrate our framework using a hardware accelerator case study where (a) partitioning is performed through High Level Synthesis (HLS), (b) the commonly known portion of the accelerator is implemented as an Application Specific Integrated Circuit (ASIC), and (c) the unique portion of the accelerator is implemented on an embedded Field-Programmable Gate Array (eFPGA).

Developing accurate and cost-effective classification techniques to facilitate virtual metrology is a critical task for modern manufacturing. In this paper, we consider the scenario in which labeling data is expensive, causing a shortage of labeled data. As a consequence, conventional classification methods suffer from a high risk of overfitting. To address this issue, we develop a novel semi-supervised classification method, namely Partial Cotraining with Logistic Regression (PCT-LR). PCT-LR finds a subset of the original features to generate a partial view, and uses this partial view to provide side information to support the complete view that includes all features. Both views are cooptimized in a Bayesian inference with a Gaussian process prior and a logistic regression classifier. The proposed method is validated with two industrial examples. Experiment results suggest that the amount of required labeled data can be reduced by up to 18% without loss in accuracy.

The current state of the integrated circuit (IC) ecosystem is that only a handful of foundries are at the forefront, continuously pushing the state of the art in transistor miniaturization. Establishing and maintaining a FinFET-capable foundry is a billion dollar endeavor. This scenario dictates that many companies and governments have to develop their systems and products by relying on 3rdparty IC fabrication. The major caveat within this practice is that the procured silicon cannot be blindly trusted: a malicious foundry can effectively modify the layout of the IC, reverse engineer its IPs, and overproduce the entire chip. The Hardware Security community has proposed many countermeasures to these threats. Notably, obfuscation has gained a lot of traction - here, the intent is to hide the functionality from the untrusted foundry such that the aforementioned threats are hindered or mitigated. In this paper, we summarize the research efforts of three independent research groups towards achieving trustworthy ICs, even when fabricated in untrusted offshore foundries. We extensively address the use of logic locking and its many variants, as well as the use of high-level synthesis (HLS) as an obfuscation approach of its own.

Logic diagnosis is a software-based methodology to identify the behavior and location of defects in failing integrated circuits, which is an essential step in yield learning. However, accurate diagnosis requires a sufficient amount of failing data, which is in contradiction to the requirement of reducing test time and cost. In this work, a dynamic test pattern reordering method is proposed to “recommend” which test patterns should be applied for a given failing chip, with the goal of maximizing failing data while minimizing test time. Unlike prior work that uses population statistics from already tested chips, this method uses a machine learning technique, namely k-Nearest Neighbors. Experiments using three industrial chips demonstrate the efficacy of the proposed methodology; specifically, the recommended test pattern order led to a 35% reduction, on average, while maximizing the amount of failure data collected.

Logic diagnosis aims to identify defects in falling integrated circuits (ICs) and thus plays an essential role in yield learning. Previous research has demonstrated that diagnosis outcome (defect number, resolution, etc.) can be accurately predicted using features derived from the data collected from failing ICs. This capability allows practitioners to better allocate resources during yield learning. However, a significant number of diagnosis must be conducted to obtain sufficient training data for building an accurate prediction model. To reduce the data collection cost, we utilize some prior knowledge through transfer learning. Specifically, a prior model is constructed from a correlated dataset and then adapted to very limited training samples from the current design of interest. Experiments performed using real industrial examples demonstrate that transfer learning can significantly improve prediction performance and save training data when a suitable prior knowledge exists.

Test vehicles of various types that aim to identify yield detractors are essential for maturing a new semiconductor process before high volume production. Due to large number of unpredictable geometries created by place-and-route, test vehicles that focus on random logic are of the utmost importance. Prior work that utilizes a two-dimensional regular array of logic blocks has demonstrated significant superiority over conventional approaches. In this work, a third dimension is added to ensure efficient diagnosis of multiple defects that frequently occur within a high defect-density environment. Experiments demonstrate a significant improvement in perfect diagnoses over the two-dimensional LCV.

IC diagnosis, as a key-step of yield learning, helps to uncover the root cause of chip failure. High quality diagnosis results, measured in terms of accuracy and resolution, are crucial for physical failure analysis during fast yield ramping. Despite various existing methods for enhancing diagnosis, there is still ample room for further improvement. In this paper, a new machine learning based diagnosis method is proposed for improving both accuracy and resolution. Based on features extracted from tester and simulation data, the goal is to predict whether a defect candidate actually corresponds to the real defect. Specifically, semi-supervised learning is deployed to use unlabeled data to augment model training. In addition, a defect-level learning procedure uses characteristics from similar defects to further improve resolution. Experiments involving virtual and silicon datasets demonstrate significant improvements that include: 6.4× increase in occurrences of perfect diagnosis, and a performance that consistently outperforms other state-of-the-art diagnosis techniques.

Logic diagnosis aims to identify defects in falling integrated circuits (ICs) and thus plays an essential role in yield learning. Previous research has demonstrated that diagnosis outcome (defect number, resolution, etc.) can be accurately predicted using features derived from the data collected from failing ICs. This capability allows practitioners to better allocate resources during yield learning. However, a significant number of diagnosis must be conducted to obtain sufficient training data for building an accurate prediction model. To reduce the data collection cost, we utilize some prior knowledge through transfer learning. Specifically, a prior model is constructed from a correlated dataset and then adapted to very limited training samples from the current design of interest. Experiments performed using real industrial examples demonstrate that transfer learning can significantly improve prediction performance and save training data when a suitable prior knowledge exists.

The outsourcing of the design and manufacturing of integrated circuits (IC) involves various untrusted entities, which can pose many security threats such as overproduction of ICs, sale of out-of-specification/rejected ICs, and piracy of Intellectual Properties (IPs). As a result, various design-for-trust techniques have been developed. Logic locking has recently gained significant interest from the research community due to its capability to provide defense against the threats from untrusted manufacturing. In logic locking, the original circuit is locked using a secret key to make it into a key-dependent circuit. However, various attacks on the extraction of secret keys associated with locking have undermined the security of logic locking techniques. Even after a decade of research, the security of logic locking is still under risk as none of the countermeasures can simultaneously provide resiliency against different attacks, such as tampering, probing, and oracle or oracle-less attacks. This paper presents an overview of novel attacks on logic locking apart from SAT-based analysis. We will present three different techniques to break a secure lock, and they are hardware Trojan based attacks, optical probing based attacks, and the ATPG oriented attacks.

Software diagnosis is the process of locating and characterizing a defect in a failing chip. It is the cornerstone of failure analysis that consequently enables yield learning and monitoring. However, multiple-defect diagnosis is challenging due to error masking and unmasking effects, and exponential complexity of the solution search process. This paper describes a three-phase, physically-aware diagnosis methodology called MDLearnX to effectively diagnose multiple defects, and in turn, aid in accelerating the design and process development. The first phase identifies a defect that resembles traditional fault models. The second and the third phases utilize the X-fault model and machine learning to identify correct candidates. Results from a thorough fault injection and simulation experiment demonstrate that MD-LearnX returns an ideal diagnosis 2X more often than commercial diagnosis. Its effectiveness is further evidenced through a silicon experiment, where, on average, MD-LearnX returns 5.3 fewer candidates per diagnosis as compared to state-of-the-art commercial diagnosis without losing accuracy.

Building accurate regression models using limited data is a challenging problem in manufacturing data analysis. In this paper, we study a particular semisupervised learning problem where labeled data are limited, while unlabeled data are plentiful. In these conditions, conventional single-view learning methods are prone to overfitting. To tackle this problem, we develop a novel co-training technique, namely partial Bayesian co-training (PBCT). PBCT scales down the original set of features to create a partial view, and then exploit side information from the partial view to enhance the complete model. The PBCT model also allows integrating domain knowledge to enhance model accuracy. The proposed method is validated with experiments on industrial manufacturing data. The experimental results show that under a reduction of labeled data by up to 50%, a robust estimation is still attainable. This suggests that the PBCT model is a promising solution to a broad spectrum of applications.

Given the inherent perturbations during the fabrication process of integrated circuits that lead to yield loss, diagnosis of failing chips is a mitigating method employed during both yield ramping and high-volume manufacturing for yield learning. However, various uncertainties in the fabrication process bring a number of challenges, resulting in diagnosis with undesirable outcomes or low efficiency, including, for example, diagnosis failure, bad resolution, and extremely long runtime. It would therefore be very beneficial to have a comprehensive preview of diagnostic outcomes beforehand, which allows fail logs to be prioritized in a more reasonable way for smarter allocation of diagnosis resources. In this work, we propose a learning-based previewer, which is able to predict five aspects of diagnostic outcomes for a failing IC, including diagnosis success, defect count, failure type, resolution, and runtime magnitude. The previewer consists of three classification models and one regression model, where Random Forest classification and regression are used. Experiments on a 28 nm test chip and a high-volume 90 nm part demonstrate that the predictors can provide accurate prediction results, and in a virtual application scenario the overall previewer can bring up to 9× speed-up for the test chip and 6× for the high-volume part.

To improve the throughput and energy efficiency of Deep Neural Networks (DNNs) on customized hardware, lightweight neural networks constrain the weights of DNNs to be a limited combination (denoted as k ϵ {1, 2}) of powers of 2. In such networks, the multiply-accumulate operation can be replaced with a single shift operation, or two shifts and an add operation. To provide even more design flexibility, the k for each convolutional filter can be optimally chosen instead of being fixed for every filter. In this paper, we formulate the selection of k to be differentiable, and describe model training for determining k-based weights on a per-filter basis. Over 46 FPGA-design experiments involving eight configurations and four data sets reveal that lightweight neural networks with a flexible k value (dubbed FLightNNs) fully utilize the hardware resources on Field Programmable Gate Arrays (FPGAs), our experimental results show that FLightNNs can achieve 2× speedup when compared to lightweight NNs with k = 2, with only 0.1% accuracy degradation. Compared to a 4-bit fixed-point quantization, FLightNNs achieve higher accuracy and up to 2× inference speedup, due to their lightweight shift operations. In addition, our experiments also demonstrate that FLightNNs can achieve higher computational energy efficiency for ASIC implementation.

Software-based diagnosis analyzes the observed response of a failing circuit to pinpoint potential defect locations and deduce their respective behaviors. It plays a crucial role in finding the root cause of failure, and subsequently facilitates yield analysis, learning and optimization. This paper describes a two-phase, physically-aware diagnosis methodology called LearnX to improve the quality of diagnosis, and in turn the quality of design, test and manufacturing. The first phase attempts to diagnose a defect that manifests as a well-established fault behavior (e.g., stuck or bridge fault models). The second phase uses machine learning to build a model (separate for each defect type) that learns the characteristics of defect candidates to distinguish correct candidates from incorrect ones. Results from 30,000 fault injection experiments indicate that LearnX returns an ideal diagnosis result (i.e., a single candidate correctly representing the injected fault) for 73.2% of faulty circuits, which is 86.6% higher than state-of-the-art commercial diagnosis. Silicon experiments further demonstrate the value of LearnX.

Logic test chips are a key component of the yield learning process, which aim to investigate the yield characteristics of actual products that will be fabricated at high volume. Mathematically, the design of a logic test chip with such an objective may involve solving a constrained under-determined equation for an integer vector solution, which is unfortunately, NP-hard. Existing solving methods are not applicable due to lack of accuracy or high computational complexity. We propose a method called IPSA (Integer Programming via Sparse Approximation) to solve this integer programming (IP) problem in an effective and efficient manner. By solving a transformed sparse-regression problem and a subsequent rounding process, a solution can be achieved with comparable error to the optimal solution of the original IP problem but using far less time and memory. Experiments with seven industrial examples demonstrate that with more than 100× speed-up, IPSA achieves a similar or even better solution compared to directly solving the original problem with a commercial IP solver.

Hardware security-related threats such as the insertion of malicious circuits, overproduction, and reverse engineering are of increasing concern in the IC industry. To mitigate these threats, various design-for-trust techniques have been developed, including sequential logic locking. Sequential logic locking protects a non-scanned design by employing a key-controlled entrance FSM, key-controlled transitions, or a combination of both techniques. Current methods for characterizing (attacking) the security of sequentially locked circuits do not have the scalability to be applicable to modern circuits. In addition, current methods often require the use of an oracle, which is a working, unlocked circuit that is assumed to be fully initializable and controllable. In this work, an oracle-free, ATPG-based approach is proposed for characterizing the security of a locked sequential circuit. This method is of several in a tool box called CLIC-A (Characterization of Locked ICs via ATPG). Experiments using CLIC-A demonstrate it is effective at recovering the key sequence from various sequentially locked circuits that have been locked using different locking methods.

Threats to integrated circuits exist due to the outsourcing of IC design and fabrication to third parties. As a result, various design-for-trust techniques have been developed including logic locking. Current methods of characterizing the security of logic locking require multiple tools and expertise for the various locking types now in existence. In this paper, we propose an ATPG-based toolbox called CLIC-A (Characterization of Locked Integrated Circuits via ATPG) that can be used to determine the level of security effectiveness for a given instance of a locked circuit. Experiments demonstrate that CLIC-A is effective across a multitude of locking methods.

Competitive position in the semiconductor field depends on yield which is becoming more challenging to achieve high levels due to the increasing complexity associated with the design and fabrication of leading-edge integrated circuits (ICs). Consequently, test chips, especially full-flow logic test chips, are increasingly employed to investigate the complex interaction between layout features and the process before and during product ramp. However, designing a high quality full-flow logic test chip can be time-consuming due to the huge design space. This work describes a design methodology that deploys a random forest classification technique to predict synthesis outcomes for test chip design exploration. Experiments on creating five full-flow logic test chips, which mimic five different designs, demonstrate the efficacy of the proposed methodology. To be specific, those design experiments demonstrate that the machine learning aided flow speeds up design by 11× with negligible performance degradation.

Logic diagnosis is a software-based methodology to identify the behavior and location of defects in failing integrated circuits, which is an essential step in yield learning. However, diagnosis can be time-consuming and produce unuseful information for further investigation of yield loss. It would therefore be desirable to have a preview of diagnosis outcomes beforehand, which helps engineers allocate diagnosis resources in a more efficient way. In this work, random forest classification and regression techniques are used to predict three aspects of potential diagnosis outcomes: existence of multiple defects, diagnosis resolution, and runtime magnitude. Experiments on a 28nm test chip and a 90nm high-volume manufactured chip prove the efficacy of the proposed methodology - high accuracy for multiple defect (up to 0.86 accuracy and 0.93 AUC) and resolution prediction (up to 0.84 accuracy and 0.87 AUC), and over 98% of the runtime magnitude prediction is within the error of one magnitude. These results prove that the method can provide helpful information to guide prudent allocation of diagnosis resources.

Previous work on the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) has achieved optimal testability for static fault models. This work explores enhancements to the CM- LCV that make delay faults optimally testable, with specific focus on the path delay fault model. Results from a design experiment indicate that the modified CM-LCV can achieve up to 100% robust path delay fault coverage, a significant improvement on the estimated 55.22% fault coverage for the reference benchmark design.

One approach for achieving a robust integrated system centers on first performing test during runtime, then identifying the locations of any faults (or potential faults), and finally repairing/replacing/avoiding the affected portion(s) of the system. Conventional fault dictionary approaches can be used to locate failures but are limited to simplistic fail behaviors due to the significant computational resources required for dictionary generation and memory storage. Several contributions are described to overcome these limitations, and include: 1) enhancement of an unspecified-transition fault model (called here the transition-X fault model, or TRAX) for capturing the misbehaviors expected from scaled technologies; 2) development of a hierarchical dictionary that only localizes to the level required; and 3) the design of a scalable architecture for retrieving and using the hierarchical dictionary for on-chip failure diagnosis. The OpenSPARC T2 processor and other circuits are used in experiments to demonstrate the low-overhead, accurate diagnosis of early life and wear-out failures, using TRAX dictionaries that are over five orders of magnitude smaller than full-response dictionaries.

Security is now becoming a well-established challenge for integrated circuits (ICs). Various types of IC attacks have been reported, including reverse engineering IPs, dumping on-chip data, and controlling/modifying IC operation. IEEE 1149.1, commonly known as Joint Test Action Group (JTAG), is a standard for providing test access to an IC. JTAG is primarily used for IC manufacturing test, but also for in-field debugging and failure analysis since it gives access to internal subsystems of the IC. Because the JTAG needs to be left intact and operational after fabrication, it inevitably provides a “backdoor” that can be exploited outside its intended use. This paper proposes machine learning-based approaches to detect illegitimate use of the JTAG. Specifically, JTAG operation is characterized using various features that are then classified as either legitimate or attack. Experiments using the OpenSPARC T2 platform demonstrate that the proposed approaches can classify legitimate JTAG operation and known attacks with significantly high accuracy. Experiments also demonstrate that unknown and disguised attacks can be detected with high accuracy as well (99% and 94%, respectively).

Deep Neural Networks (DNNs) have been adopted in many systems because of their higher classification accuracy, with custom hardware implementations great candidates for high-speed, accurate inference. While progress in achieving large scale, highly accurate DNNs has been made, significant energy and area are required due to massive memory accesses and computations. Such demands pose a challenge to any DNN implementation, yet it is more natural to handle in a custom hardware platform. To alleviate the increased demand in storage and energy, quantized DNNs constrain their weights (and activations) from floating-point numbers to only a few discrete levels. Therefore, storage is reduced, thereby leading to less memory accesses. In this paper, we provide an overview of different types of quantized DNNs, as well as the training approaches for them. Among the various quantized DNNs, our LightNN (Light Neural Network) approach can reduce both memory accesses and computation energy, by filling the gap between classic, full-precision and binarized DNNs. We provide a detailed comparison between LightNNs, conventional DNNs and Binarized Neural Networks (BNNs), with MNIST and CIFAR-10 datasets. In contrast to other quantized DNNs that trade-off significant amounts of accuracy for lower memory requirements, LightNNs can significantly reduce storage, energy and area while still maintaining a test error similar to a large DNN configuration. Thus, LightNNs provide more options for hardware designers to trade-off accuracy and energy.

Recent research has focused on Deep Neural Networks (DNNs) implemented directly in hardware. However, larger DNNs require significant energy and area, thereby limiting their wide adoption. We propose a novel DNN quantization technique and a corresponding hardware solution, CompactNet that optimizes the use of hardware resources even further, through dynamic allocation of memory for each parameter. Experimental results for the MNIST and CIFAR-10 datasets, show that CompactNet reduces the memory requirement by over 80%, the energy requirement by 12-fold, and the area requirement by 7-fold, when compared to the conventional DNN. This is achieved with minimal degradation to the classification accuracy. We demonstrate that, CompactNet provides pareto-optimal designs to make trade-offs between accuracy and resource requirement. The applications of CompactNet can be extended to datasets like ImageNet, and into models like MobileNet.

IEEE 1687 standard (IJTAG), as an extension to the IEEE 1149.1, facilitates efficient access to embedded instruments by supporting reconfigurable scan networks. Specifically, IJTAG allows each IP to be wrapped by a test data register (TDR) whose access is controlled by a segment insertion bit (SIB) or a scan-mux control bit (SCB). Because the TDRs and the SIB/SCB network are typically not public, but critical for accessing embedded instruments, they might be used for illegitimate purposes, such as dumping credential data and reverse engineering IP design. Machine learning has been proposed to detect such attacks, but the large number of instruments and parallel execution enabled by the IJTAG produce high-dimensional data, which poses a challenge to on-chip detection. In this paper, we propose to reduce the high-dimensional but sparse data using a low-density parity-check (LDPC) matrix. Experiments using a modified version of the OpenSPARC T2 to include IJTAG functionality demonstrate that the use of feature reduction eliminates 91% of the features, leading to 43% reduction in circuit size without affecting detection accuracy. Also, the on-chip detector adds moderate overhead (~ 8%) to the IJTAG.

At advanced technology nodes, complex interactions between layout features and the process can lead to manufacturability issues that reduce yield. Due to the huge number of layout geometries inherent to random logic, logic-only test chips are increasingly employed during yield ramp. This work describes a design methodology that incorporates complex layout geometries into an optimally testable full-flow logic test chip. Experiments comparing properties among test-chip, benchmark, and actual product designs demonstrate the efficacy of the methodology. Specifically, our test chips achieve 100% coverage for various fault models, and on average, incorporate the layout geometries of interest while being 96% less layout area and 63% less wire length compared to various benchmark and product designs.

Logic diagnosis, the process of identifying and locating possible defects in failing integrated circuits, is a key step in yield learning for both technology development and high-volume manufacturing. However, resources can be easily wasted if diagnosis results in no meaningful information, or if the type of diagnostic result is not actionable. It would therefore be very beneficial to have a comprehensive preview of diagnostic outcomes beforehand, which allows diagnosis resources to be prioritized in a more reasonable and effective way. In this work, a methodology is developed to predict whether a fail log for a given design will result in a diagnosis outcome that is meaningful for the purpose at hand. Specifically, the aim is to predict the time required for diagnosis, and whether diagnosis produces any defect candidates, and if so, are those candidates the result of logic failure or chain failure. Random Forest classification algorithm is used for prediction. Experiments on a 28nm test chip and a high-volume 90nm part illustrate that the methodology can provide accurate prediction results (0.95+ precision, 0.9+ recall and F1-score, and 0.96+ AUC on average) when two classes are balanced, and satisfactory results (0.95+ recall and 0.98+ AUC on average) when two classes are imbalanced.

The goal of diagnosis is to identify defect locations and subsequently, identify the root cause so as to minimize (and ideally eliminate) the need for physical failure analysis. With advanced technology nodes, there has been an increasing number of front-end (i.e., within a standard cell) defects. Conventional diagnosis approaches typically fail to localize such defects. In addition, circuit-level noise can change the tester response in an unexpected way, and can decrease the quality of diagnosis. This work describes a noise-resistant approach called NOIDA (NOise-resistant Intra-cell DiAgnosis) for effectively diagnosing cell-level defects based on the analysis of the intra-cell physical neighborhoods surrounding likely defect locations. Defect behavior is derived based on the neighborhood, instead of relying on a specific fault model. Experiments demonstrate the effectiveness of NOIDA using a library of standard cells. The results show that for over 16,000 static and sequence-dependent defects, the method achieves an average resolution improvement of 12.1% over prior work with a small accuracy loss (specifically, 1.6%). Additionally, NOIDA is found to be more robust to noise in the tester response. Specifically, in the presence of noisy tester response, NOIDA attains an accuracy of 97.6% with an average resolution improvement of 48.6% over prior work.

Diagnosis is the first analysis step for uncovering the root cause of failure for a defective integrated logic circuit. The conventional objective of identifying failure locations has been augmented with various physically-aware diagnosis techniques that are intended to improve both resolution and accuracy. Despite these advances, it is often the case, however, that resolution, i.e., the number of locations or candidates reported by diagnosis, exceeds the number of actual failing locations. To address this major challenge, a novel, machine-learning-based resolution improvement methodology named physically-aware diagnostic resolution enhancement (PADRE) is described. PADRE uses easily-available tester and simulation data to extract features that uniquely characterize each candidate. PADRE applies machine learning to the features to identify candidates that correspond to the actual failure locations. Through various experiments, PADRE is shown to significantly improve resolution with virtually no negative impact on accuracy. Additional experiments demonstrate that PADRE is robust against data set variation and feature-data availability.

Hardware implementations of deep neural networks (DNNs) have been adopted in many systems because of their higher classification speed. However, while they may be characterized by better accuracy, larger DNNs require significant energy and area, thereby limiting their wide adoption. The energy consumption of DNNs is driven by both memory accesses and computation. Binarized neural networks (BNNs), as a tradeoff between accuracy and energy consumption, can achieve great energy reduction and have good accuracy for large DNNs due to their regularization effect. However, BNNs show poor accuracy when a smaller DNN configuration is adopted. In this article, we propose a new DNN architecture, LightNN, which replaces the multiplications to one shift or a constrained number of shifts and adds. Our theoretical analysis for LightNNs shows that their accuracy is maintained while dramatically reducing storage and energy requirements. For a fixed DNN configuration, LightNNs have better accuracy at a slight energy increase than BNNs, yet are more energy efficient with only slightly less accuracy than conventional DNNs. Therefore, LightNNs provide more options for hardware designers to trade off accuracy and energy. Moreover, for large DNN configurations, LightNNs have a regularization effect, making them better in accuracy than conventional DNNs. These conclusions are verified by experiment using the MNIST and CIFAR-10 datasets for different DNN configurations. Our FPGA implementation for conventional DNNs and LightNNs confirms all theoretical and simulation results and shows that LightNNs reduce latency and use fewer FPGA resources compared to conventional DNN architectures.

Software-based diagnosis examines the failing-circuit design and test response to identify potential defect locations and if possible, pinpoint the root cause of failure. This paper describes a generalized physically-aware methodology called PADLOC (Physically-Aware Defect LOcalization and Characterization) to improve the quality of diagnosis. PADLOC consists of (a) identifying the subnets that are more likely to correspond to the actual defect, and (b) deriving the defect behavior based on the activity of the neighborhood (i.e., nets that are physically close and logically related). Results from 6,000 defect injection experiments reveal that 97.2% of the defects are accurately diagnosed with 92.6% of defects achieving a logical resolution of at most five and 27.6% of defects attaining perfect resolution. PADLOC has an average resolution of 2.6 and improves resolution for 24.8% of defects over prior work. In addition, the physical resolution (i.e., number of subnets) is improved for 61.3% of defects. Finally, PADLOC returns 33.9 fewer subnets per defect and reduces the number of subnets by 44.8%.

Virtual metrology is an important tool for industrial automation. To accurately build regression models for virtual metrology, we consider semi-supervised learning where labeled data are expensive to collect, but unlabeled data are abundant. In such a scenario, due to the scarcity of labeled data, traditional single-view learning methods face the risk of overfitting. To address the overfitting issue, we develop a Partial Co-training framework, which is an extension of the original co-training approach by means of an undirected probabilistic graphical model. Unlike other co-training techniques, this model creates a partial view by shrinking the original feature space, and makes use of this partial-view to provide guidance information for improving the complete-view model. Our approach is validated with data from two manufacturing applications. The results indicate that a consistent and robust estimation is achievable with very limited labeled data.

Previous work on the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) has emphasized the diagnosability properties of a specific class of regular circuits called functional unit block arrays (FUB arrays). This paper describes a multiple-defect, two-level diagnosis procedure that leverages these unique properties of the FUB array to significantly improve diagnosis. This custom diagnosis procedure is implemented and evaluated against commercial diagnosis using a simulated fault-injection experiment involving pairs of injected faults. Custom diagnosis is accurate in 98.2% of the simulations with resolution of at most five for 94.1% of the simulations, improving upon the commercial results of 70.7% accurate and 85.0% with the same level of resolution.

Application-specific integrated circuit (ASIC) implementations for Deep Neural Networks (DNNs) have been adopted in many systems because of their higher classification speed. However, although they may be characterized by better accuracy, larger DNNs require significant energy and area, thereby limiting their wide adoption. The energy consumption of DNNs is driven by both memory accesses and computation. Binarized Neural Networks (BNNs), as a trade-off between accuracy and energy consumption, can achieve great energy reduction, and have good accuracy for large DNNs due to its regularization effect. However, BNNs show poor accuracy when a smaller DNN configuration is adopted. In this paper, we propose a new DNN model, LightNN, which replaces the multiplications to one shift or a constrained number of shifts and adds. For a fixed DNN configuration, LightNNs have better accuracy at a slight energy increase than BNNs, yet are more energy efficient with only slightly less accuracy than conventional DNNs. Therefore, LightNNs provide more options for hardware designers to make trade-offs between accuracy and energy. Moreover, for large DNN configurations, LightNNs have a regularization effect, making them better in accuracy than conventional DNNs. These conclusions are verified by experiment using the MNIST and CIFAR-10 datasets for different DNN configurations.

A random forest is a widely used machine learning classifier. An FPGA is a good platform for performance acceleration of random forests due to their inherent concurrent memory accesses and computational parallelism. Amortizing the cost of an FPGA implementation among different applications is desirable, but the context switch time between applications significantly influences the forest architecture. Several architectures for random forests implemented within an FPGA are described, and the area-reconfiguration tradeoffs that determine the suitability of each for multiple applications are characterized. We show that each architecture can maximize the area utilization efficiency of an FPGA given a constraint on the context switch time.

This paper presents the design and implementation of a fault simulator for the TRAnsition-X fault model (TRAX for short) on a graphics processing unit (GPU). Fault dictionaries are an important aspect of on-chip fault detection and diagnosis. Generating a fault dictionary requires fault simulation with no fault dropping, requiring extensive computational resources. The inherent parallelism of the fault simulation problem maps well to the large number of concurrent threads supported by a modern GPU, and a GPU can be used to accelerate the construction of a fault dictionary. Our approach employs both pattern-parallel and fault-parallel algorithms in the GPU kernel implementations. Experiments involving various circuits, including the OpenSPARC T2 processor, demonstrate a speed-up of over 42x.

To ensure robustness of integrated systems, the TRAnsition-X (TRAX) fault model has been used with on-chip test and diagnosis hardware, utilizing fault dictionaries for diagnosis. Generating a fault dictionary requires fault simulation with no fault dropping, requiring extensive computational resources. This paper presents the design and implementation of an efficient fault simulator for the TRAX fault model, designed to run on a graphics processing unit (GPU). The inherent parallelism of the fault simulation problem maps well to the large number of concurrent threads supported by a modern GPU, and a GPU can be used to accelerate the construction of a fault dictionary. Our approach employs both pattern-parallel and fault-parallel algorithms in the GPU kernel implementations. Experiments involving various circuits, including the OpenSPARC T2 processor, demonstrate a mean speed-up of nearly 8x.

Fast yield ramping in a new technology to meet aggressive time-to-market deadlines requires a comprehensive design and fabrication methodology for silicon test structures that systematically explores and validates the technology. Prior work proposed a novel logic characterization vehicle (LCV), along with an implementation flow that produces a test chip that ensures logic demographics that resemble real products, and ensures near-optimal testability and diagnosability. This work describes a design flow that efficiently incorporates FEOL layout properties into an easily testable and diagnosable logic-based test chip. Experiments comparing testability, logic and layout properties between the test chip design and various benchmark circuits demonstrate the efficacy of this approach.

Precise and accurate logic diagnosis for integrated circuits enables fast analysis of defect locations and their corresponding behaviors that leads to valuable feedback for achieving fast yield ramp-up. However during large-volume production, limited tester time or memory restrict the amount of data that can be recorded for each failing chip, thus making diagnosis more difficult. To help mitigate this challenge, a test-reordering method is developed to improve diagnosability for chips that fail scan-based logic testing. Experiment results show that the number of failing chips with perfect diagnostic resolution is increased by 10.6% and 5.1%, respectively, for two industrial designs after tests are reordered using the method described in this work.

Design for manufacturability rule evaluation using manufactured silicon (DREAMS) is a comprehensive methodology for evaluating the yield-preserving capabilities of a set of design for manufacturability (DFM) rules using the results of logic diagnosis performed on failed ICs. DREAMS is an improvement over prior art in that the distribution of rule violations over the diagnosis candidates and the entire design are taken into account along with the nature of the failure (e.g., bridge versus open) to appropriately weight the rules. Silicon and simulation results demonstrate the efficacy of the DREAMS methodology. Specifically, virtual data is used to demonstrate that the DFM rule most responsible for failure can be reliably identified even in light of the ambiguity inherent to a nonideal diagnostic resolution, and a corresponding rule-violation distribution that is counter-intuitive. We also show that the combination of physically aware diagnosis and the nature of the violated DFM rule can be used together to improve rule evaluation even further. Application of DREAMS to the diagnostic results from an in-production chip provides valuable insight in how specific DFM rules improve yield (or not) for a given design manufactured in particular facility. Finally, we also demonstrate that a significant artifact of DREAMS is a dramatic improvement in diagnostic resolution. This means that in addition to identifying the most ineffective DFM rule(s), validation of that outcome via physical failure analysis of failed chips can be eased due to the corresponding improvement in diagnostic resolution.

Continued scaling of semiconductor fabrication processes has made achieving yield targets increasingly difficult. The design and fabrication of various types of test vehicles is one approach for enabling fast yield learning. Recent work introduced the Carnegie Mellon logic characterization vehicle (CM-LCV). The CM-LCV design methodology uses regularity and existing testability theory to produce logic-based designs that are both highly testable and diagnosable. For the CM-LCV to be effective for yield learning, it must reflect the design characteristics of actual product layouts. Previous work enables incorporation of a standard-cell distribution derived from product designs into an LCV while simultaneously ensuring optimal testability. In this work, a new method is proposed for constructing a CM-LCV that reflects the design characteristics of a product through rewiring either the entire layout or some portion thereof. Four different approaches for rewiring are examined, and the results of each approach are evaluated using a variety of metrics. Experiment results reveal that a product layout can be easily rewired to construct an LCV with reasonable wirelength with reasonable CPU time. Rewiring has many advantages including the transformation of an actual product front-end to a logic-based test chip that has significant transparency to failure. Consequently, this means that front-end masks from an actual product can be re-used to create an effective LCV that is both more reflective and inexpensive to fabricate.

An accurate and high-resolution diagnosis enables physical failure analysis (PFA) to identify and understand the root-cause of integrated-circuit failure. Despite many existing techniques for improving diagnosis, resolution is still far from ideal, which hinders PFA and other analyses. To address this challenge, we extend the capability of PADRE (physically-aware diagnostic resolution enhancement), a powerful machine learning based diagnosis resolution improvement technique, with a novel, active learning (AL) based PFA selection approach. An active-learning based PADRE (AL PADRE) selects the most useful defects for PFA in order to improve diagnostic resolution. AL PADRE provides an alternative to the normal PFA selection procedure, it improves the the accuracy of PADRE, and thus enables a more accurately improved resolution. AL PADRE is validated by both simulation-based experiment and silicon experiment. Simulation-based experiments show that by using AL PADRE, the number of PFAs required for increasing the accuracy to a stable level of 90% is reduced by more than 60% on average compared to baseline approach, and AL PADRE consistently outperforms the baseline approach for accuracy improvement in various scenarios. In the silicon experiment, by using AL PADRE, the number of chips needed to undergo PFA was reduced by more than 6x in order to increase diagnosis accuracy by more than 20%.

Rapid yield learning in a new manufacturing process via test chips is greatly enhanced with a “Design for Diagnosis” methodology. Prior work on logic-based test chip design demonstrated an implementation flow that ensures 100% intra-cell fault coverage using a minimal test set. However, testability alone does not guarantee good diagnosability. Since diagnosis is inherently a function of design, it is crucial that the design flow ensures defect-level diagnosis resolution and accuracy. This work describes an enhanced implementation methodology for the Carnegie-Mellon Logic Characterization Vehicle (CM-LCV) that ensures optimal cell-aware diagnosability by design. Experiments comparing intra-cell defect diagnosability of the CM-LCV and various benchmark circuits demonstrate the efficacy.

An ensemble of machine learning classifiers usually improves generalization performance and is useful for many applications. However, the extra memory storage and computational cost incurred from the combined models often limits their potential applications. In this article, we propose a new ensemble reduction method called CANOPY that significantly reduces memory storage and computations. CANOPY uses a technique from logic minimization for digital circuits to select and combine particular classification models from an initial pool in the form of a Boolean function, through which the reduced ensemble performs classification. Experiments on 20 UCI datasets demonstrate that CANOPY either outperforms or is very competitive with the initial ensemble and one state-of-the-art ensemble reduction method in terms of generalization error, and is superior to all existing reduction methods surveyed for identifying the smallest numbers of models in the reduced ensembles.

Despite best efforts, integrated systems are “born” (manufactured) with a unique `personality' that stems from our inability to precisely fabricate their underlying circuits, and create software a priori for controlling the resulting uncertainty. It is possible to use sophisticated test methods to identify the best-performing systems but this would result in unacceptable yields and correspondingly high costs. The system personality is further shaped by its environment (e.g., temperature, noise and supply voltage) and usage (i.e., the frequency and type of applications executed), and since both can fluctuate over time, so can the system's personality. Systems also “grow old” and degrade due to various wear-out mechanisms (e.g., negative-bias temperature instability), and unexpectedly due to various early-life failure sources. These “nature and nurture” influences make it extremely difficult to design a system that will operate optimally for all possible personalities. To address this challenge, we propose to develop statistical learning in-chip (SLIC). SLIC is a holistic approach to integrated system design based on continuously learning key personality traits on-line, for self-evolving a system to a state that optimizes performance hierarchically across the circuit, platform, and application levels. SLIC will not only optimize integrated-system performance but also reduce costs through yield enhancement since systems that would have before been deemed to have weak personalities (unreliable, faulty, etc.) can now be recovered through the use of SLIC.

Test selection aims at achieving high test quality with low test cost. By selecting only a subset of tests that most effectively detect defects, test time can be reduced while ensuring test escape is minimized. In this work, a new one-pass test-selection method is described that efficiently identifies tests that maximize either fault-model coverage or an N-detect test metric. The proposed method analyzes and selects each test one at a time in a streaming fashion to save both time and memory. The method is applied to two industrial designs, namely an IBM ASIC and an NVIDIA GPU. Experiment results demonstrate that the new method selects tests with coverage that virtually matches a greedy algorithm (less than 0.01% coverage difference), but uses less time (reduced by 2X) and memory (reduced by 20X to 200X). Additional experiments performed on two ISCAS circuits also demonstrates the new method typically achieves higher coverage but uses less time (reduced by 7X to 30X) and memory (reduced by 140X) as compared to selecting tests using a linear programming based approach.

A new type of logic characterization vehicle (LCV) that optimizes design, test, and diagnosis for yield learning has been recently described and is called the Carnegie-Mellon Logic Characterization Vehicle (CM-LCV). The CM-LCV is a product-like test chip that uses constant-testability theory and regularity to create a parameterized design that targets the physical characteristics of a product design or family of designs. The logic function of the CM-LCV is, by construction, designed to exhibit near-optimal test and diagnosis characteristics. The physical characteristics however should reflect those found in actual customer designs. In this work, we describe a unique and straight-forward methodology for measuring the physical characteristics of a design and more importantly how to impose or reflect those same characteristics into a CM-LCV. Experiments using both benchmark and industrial designs demonstrate the efficacy of this approach. Specifically, we develop a flow using available tools that can automatically synthesize a scalable CM-LCV in very little time with standard-cell characteristics that are nearly identical to product designs. For example, in the best case, we demonstrate the complete design of a scalable CM-LCV that matches the standard-cell usage of a family of benchmark designs with less than 0.25% error in about 2 hours of compute time.

The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.

Fast and efficient analysis of test chips is crucial for effective yield learning. Prior work proposed the Carnegie-Mellon logic characterization vehicle (CM-LCV) as an improved test chip for yield learning. The highly regular nature of the CM-LCV test chip is particularly appealing for BIST; the current work describes a BIST scheme that achieves 100% input-pattern fault coverage with an 86.9% reduction in test time for a reference design. Furthermore, all of these properties are achieved with a minimal hardware overhead.

On-chip test/diagnosis is proposed to be an effective method to ensure the lifetime reliability of integrated systems. In order to manage the complexity of such an approach, an integrated system is partitioned into multiple modules where each module can be periodically tested, diagnosed and repaired if necessary. The limitation of on-chip memory and computing capability, coupled with the inherent uncertainty in diagnosis, causes the occurrence of misdiagnoses. To address this challenge, a novel incremental-learning algorithm, namely dynamic k-nearest-neighbor (DKNN), is developed to improve the accuracy of on-chip diagnosis. Different from the conventional KNN, DKNN employs online diagnosis data to update the learned classifier so that the classifier can keep evolving as new diagnosis data becomes available. Incorporating online diagnosis data enables tracking of the fault distribution and thus improves diagnostic accuracy. Experiments using various benchmark circuits (e.g., the cache controller from the OpenSPARC T2 processor design) demonstrate that diagnostic accuracy can be more than doubled.

Systematic defects within integrated circuits (ICs) are a significant source of failures in nanoscale technologies. Identification of systematic defects is therefore very important for yield improvement. This paper discusses a diagnosis-driven systematic defect identification methodology that we call layout analysis for systematic IC-defect identification using clustering (LASIC). By clustering images of the layout locations that correspond to diagnosed sites for a statistically large number of IC failures, LASIC uncovers the common layout features. To reduce computation time, only the dominant coefficients of a discrete cosine transform analysis of the layout images are used for clustering. LASIC is applied to an industrial chip and it is found to be effective. In addition, detailed simulations reveal that LASIC is both accurate and effective.

Physical failure analysis (PFA) is crucial to improving yield during the production life of an integrated circuit (IC). PFA begins with software-based diagnosis, which reports a set of likely failing candidates. A large set, which can result from test-set equivalent (TSE) faults, makes PFA success unlikely because each candidate may potentially have to be examined. Reducing the cardinality of a TSE fault class can reduce the time required for PFA since it likely decreases the number of candidates that must be examined. Additional (diagnostic) test vectors can be generated however to reduce class size. In this work, several layout-based physical metrics are defined and investigated for assessing the layout characteristics of a TSE fault class, which serves as an estimate of the time/difficulty required to perform PFA. In short, these metrics are used to define a physically-aware diagnostic resolution (PAR for short) for a fault class. A TSE fault class with a bad PAR likely requires more PFA effort than one with good PAR. To demonstrate the utility of PAR, a test-selection algorithm that chooses tests from an N-detect test pool based on the improvement in PAR is compared to techniques that use conventional definitions of diagnostic resolution. Comprehensive experiments reveal that fewer additional tests are needed when using PAR.

Predicting defect level (DL) using fault coverage is an extremely difficult task but if can be accomplished ensures high quality while controlling test cost. Because IC testing now involves generating and combining tests from multiple fault models, it is important to understand how the coverage from each fault model relates to the overall DL. In this work, a new model is proposed which learns the effectiveness of fault models from the diagnostic results of defective chips, and predicts defect level using the derived measures of effectiveness and fault cover ages of multiple fault models. The model is verified using fail data from an IBM ASIC and virtual fail data created through simulation. Experiment results demonstrate that this new model can predict DL more reliably than conventional approaches.

A new type of logic characterization vehicle (LCV) that optimizes design, test, and diagnosis for yield learning is described. The Carnegie-Mellon LCV (CM-LCV) uses constant-testability theory and logic/layout regularity to create a parameterized design that exhibits both front- and back-end characteristics of a product-like, customer design. Design and test analysis of various CM-LCV designs (one of which has >4M gates) demonstrates that design time and density, test and diagnosis can all be simultaneously improved. For example, conventional ATPG produces test sets that are 2X larger, produce significantly poorer fault-detection and diagnostic characteristics for standard and advanced fault models, and require runtimes that are several orders of magnitude larger than the simple approach used to generate the constant test set for the CM-LCV. On the design side, a fully designed custom layout is 25% smaller than its synthesized, place-and-routed counterpart.

In this paper, a novel Bayesian model fusion (BMF) method is proposed for test cost reduction based on wafer-level spatial variation modeling. BMF relies on the assumption that a large number of wafers of the same circuit design (e.g., all wafers from the same lot) share a similar spatial pattern. Hence, the measurement data from one wafer can be borrowed to model the spatial variation of other wafers via Bayesian inference. By applying the Sherman-Morrison-Woodbury formula, a fast numerical algorithm is derived to reduce the computational cost of BMF for practical test applications. Furthermore, a new test methodology is developed based on BMF and it closely monitors the escape rate and yield loss. As is demonstrated by the wafer probe measurement data of an industrial RF transceiver, BMF achieves 1.125× reduction in test cost and 2.6× reduction in yield loss, compared to the conventional approach based on virtual probe (VP).

Design for manufacturability (DFM) is essential because of the formidable challenges encountered in nano-scale integrated circuit (IC) fabrication. Unfortunately, it is difficult for designers to understand the cost-benefit tradeoff when tuning their design through DFM to achieve better manufacturability. This paper attempts to assist the designer in meeting this challenge by providing a methodology, called rule assessment of defect-affected regions (RADAR), which uses failing-IC diagnosis results to systematically evaluate the effectiveness of DFM rules. RADAR is applied to the fail data from a 90 nm Nvidia graphics processing unit to demonstrate its viability. Specifically, evaluation of various DFM rules revealed that via-enclosure rules play a more important role than the density-related rules. The yield impact of resolving violations is also quantified. In addition, comprehensive simulation experiments have shown RADAR to be accurate and effective for performing DFM evaluation.

Stringent quality requirements for integrated, heterogeneous systems have led designers and test engineers to mandate large sets of tests to be applied to these systems, which, in turn, have resulted in increased test cost. However, many of these tests are unnecessary (i.e., redundant), since their outcomes can be reliably predicted using results from other applied tests. A methodology for identifying the redundant tests of an integrated, heterogeneous system that has only binary pass-fail test data is described. This methodology uses decision trees, Boolean minimization, and satisfiability as core components. Feasibility is empirically demonstrated using test data from two commercially fabricated systems, namely, a high-speed serializer/deserializer (HSS) and a phase-locked loop (PLL). Our analysis of test data from > 38,000 HSS and > 22,000 PLL circuits show that 14 out of 40 HSS tests and 11 out of 36 PLL tests are redundant.

DREAMS (DFM Rule EvAluation using Manufactured Silicon) is a comprehensive methodology for evaluating the yield-preserving capabilities of a set of DFM (design for manufacturability) rules using the results of logic diagnosis performed on failed ICs. DREAMS is an improvement over prior art in that the distribution of rule violations over the diagnosis candidates and the entire design are taken into account along with the nature of the failure (e.g., bridge versus open) to appropriately weight the rules. Silicon and simulation results demonstrate the efficacy of the DREAMS methodology. Specifically, virtual data is used to demonstrate that the DFM rule most responsible for failure can be reliably identified even in light of the ambiguity inherent to a nonideal diagnostic resolution, and a corresponding rule-violation distribution that is counter-intuitive. We also show that the combination of physically-aware diagnosis and the nature of the violated DFM rule can be used together to improve rule evaluation even further. Application of DREAMS to the diagnostic results from an in-production chip provides valuable insight in how specific DFM rules improve yield (or not) for a given design manufactured in particular facility. Finally, we also demonstrate that a significant artifact of DREAMS is a dramatic improvement in diagnostic resolution. This means that in addition to identifying the most ineffective DFM rule(s), validation of that outcome via physical failure analysis of failed chips can be eased due to the corresponding improvement in diagnostic resolution.

Physically Unclonable Functions (PUFs) are structures with many applications, including device authentication, identification, and cryptographic key generation. In this paper we propose a new PUF, called SCAN-PUF, based on scan-chain power-up states. We argue that scan chains have multiple characteristics that make them uniquely suited as a low-cost PUF. We present results from test chips fabricated in a 65nm bulk CMOS process in support of these claims. While approximately 20% of the total population of scan elements are unreliable across temperature variations, we find that simple unanimous selection schemes can result in mean error rates of less than 0.1% for the selected populations across all measurements collected.

Diagnosis is the first step of IC failure analysis. The conventional objective of identifying the failure locations has been augmented with various physically-aware techniques that are intended to improve both diagnostic resolution and accuracy. Despite these advances, it is often the case however that resolution, i.e., the number of locations or candidates reported by diagnosis, exceeds the number of actual failing locations. Imperfect resolution greatly hinders any follow-on, information-extraction analyses (e.g., physical failure analysis, volume diagnosis, etc.) due to the resulting ambiguity. To address this major challenge, a novel, unsupervised learning methodology that uses ordinarily-available tester and simulation data is described that significantly improves resolution with virtually no negative impact on accuracy. Simulation experiments using a variety of fault types (SSL, MSL, bridges, opens and cell-level input-pattern faults) reveal that the number of failed ICs that have perfect resolution can be more than doubled, and overall resolution is improved by 22%. Application to silicon data also demonstrates significant improvement in resolution (38% overall and the number of chips with ideal resolution is nearly tripled) and verification using PFA demonstrates that accuracy is maintained.

Start of the "Special session 4B: Elevator talks" section of the conference record.

Test data collection for a failing integrated circuit (IC) can be very expensive and time consuming. Many companies now collect a fix amount of test data regardless of the failure characteristics. As a result, limited data collection could lead to inaccurate diagnosis, while an excessive amount increases the cost not only in terms of unnecessary test data collection but also increased cost for test execution and data-storage. In this work, the objective is to develop a method for predicting the precise amount of test data necessary to produce an accurate diagnosis. By analyzing the failing outputs of an IC during its actual test, the developed method dynamically determines which failing test pattern to terminate testing, producing an amount of test data that is sufficient for an accurate diagnosis analysis. The method leverages several statistical learning techniques, and is evaluated using actual data from a population of failing chips and five standard benchmarks. Experiments demonstrate that test-data collection can be reduced by > 30% (as compared to collecting the full-failure response) while at the same time ensuring >90% diagnosis accuracy. Prematurely terminating test-data collection at fixed levels (e.g., 100 failing bits) is also shown to negatively impact diagnosis accuracy.

One approach for achieving integrated-system robustness centers on performing test during runtime, identifying the location of any faults (or potential faults), and repairing or avoiding the affected portion of the system. Fault dictionaries can be used to locate faults but conventional approaches require significant memory storage and are therefore limited to simplistic fault types. To overcome these limitations, three contributions are made that include: (i) enhancement of an unspecified transition fault model (called here the transition-X fault model, or TRAX for short) for capturing the misbehaviors expected from scaled technologies, (ii) development of a new type of hierarchical dictionary that only localizes to the level of repair or fault avoidance, and (iii) the design of a scalable architecture for retrieving and using the hierarchical dictionary for performing on-chip diagnosis. Experiments involving various circuits, including the OpenSPARC T2 processor, demonstrate that early-life and wear-out failures can be accurately diagnosed with minimum overhead using TRAX dictionaries that are up to 2600x smaller than full-response dictionaries.

Physically-aware$N$-detect ($PAN$-detect) test improves defect coverage by exploiting defect locality. This paper presents physically-aware test selection (PATS) to efficiently generate$PAN$-detect tests for large industrial designs. Compared to traditional$N$-detect test, the quality resulting from$PAN$-detect is enhanced without any increase in test execution cost. Experiment results from an IBM in-production application-specific integrated circuit demonstrate the effectiveness of PATS in improving defect coverage. Moreover, utilizing novel test-metric evaluation, we compare the effectiveness of traditional$N$-detect and$PAN$-detect, and demonstrate the impact of automatic test pattern generation parameters on the effectiveness of$PAN$-detect.

Logic-level simulation has been the de facto method for simulating defect/faulty behavior for various testing tasks since it offers a good tradeoff between accuracy and speed. Unfortunately, by abstracting defect behavior to the logic level (i.e., a fault model), it also discards important information that inevitably results in inaccuracies. This paper describes a fast and accurate defect simulation framework called SLIDER (simulation of layout-injected defects for electrical responses). SLIDER uses well-developed mixed-signal simulation technology that is conventionally used for design verification. There are three innovative aspects that distinguish SLIDER from prior work in this area: 1) accuracy resulting from defect injection taking place at the layout level; 2) speedup resulting from careful and automatic partitioning of the circuit into maximal digital and minimal analog domains for mixed-signal simulation; and 3) complete automation that includes defect generation, defect injection, design partitioning, netlist extraction, mixed-signal simulation, and test-data extraction. The virtual failure data created by SLIDER is useful in a variety of settings that include diagnosis resolution improvement, defect localization, fault model evaluation, and evaluation of yield/test learning techniques that are based on failure data analysis.

This paper describes a method for improving the test quality of digital circuits on a per-design basis by: 1) monitoring the defect behaviors that occur through volume diagnosis; and 2) changing the test patterns to match the identified behaviors. To characterize the behavior of a defect (i.e., the conditions when a defect is activated), physically-aware diagnosis is employed to extract the set of signal lines relevant to defect activation. Then, based on the set of signal lines derived, the defect is attributed to one of several behavior categories. Our defect level model uses the behavior-attribution results of the current failing population to guide test-set customization to minimize defect level for a given constraint on test costs, or alternatively, ensure that defect level does not exceed some predetermined threshold. Circuit-level simulation involving various types of defects shows that defect level can be reduced by 30% using this method. Simulation experiment on actual chips also demonstrates quality improvement.

Logic diagnosis analyzes the observed failing circuit responses to derive the potential defect sites. This paper describes a method for improving diagnosis through failing behavior identification (FBI). FBI captures defect behavior (i.e., activation conditions of the defect) by identifying the signal lines related to defect activation. This additional information allows the root cause to be estimated in order to improve yield, design quality, and test quality, as well as guide PFA to perform faster defect localization. FBI is accomplished by: 1) deriving the neighborhood states of the defect site, i.e., the actual values on the signal lines within logical or physical proximity to the defect site, and 2) identifying the signal lines that are most relevant to defect activation. The efficacy of FBI is validated using circuit-level and logic-level simulation experiments. The results show that FBI achieves an average accuracy of 94% in identifying signal lines that are relevant to defect activation, a 28% improvement over an existing approach. Moreover, by analyzing the neighborhood states of each defect site reported by logic diagnosis, sites that are not likely to be defective can be eliminated, which leads to improvement in diagnosis resolution. Experiment results show that with little influence on diagnosis accuracy, the number of incorrect defective sites reported by logic diagnosis can be reduced by 64%, on average.

Design for manufacturability (DFM) is inevitable because of the formidable challenges encountered in nano-scale integrated circuit (IC) manufacturing. Unfortunately, it is difficult for designers to understand the cost-benefit tradeoff when tuning their design through DFM to achieve better manufacturability. This work attempts to assist the designer in this aspect by providing a methodology (called RADAR --- Rule Assessment of Defect-Affected Regions) which uses failing-IC diagnosis results to systematically evaluate the effectiveness of DFM rules. RADAR is applied to the fail data from a 90nm Nvidia graphics processing unit (GPU) to demonstrate its viability. Specifically, evaluation of the via-enclosure rules revealed that they are much more needed in metal layers 3--6 than the remaining layers.

At substantial cost, conventional methods for evaluating test quality apply a specially-generated test set to a large population of manufactured chips. In contrast, a new time-efficient framework for evaluating test quality (FETQ) that uses tester data from normal production has been developed and validated. FETQ estimates the quality of both static and adaptive test metrics, where the latter guides test using the results of statistical data analysis. FETQ is innovative since instead of evaluating a single measure of effectiveness (e.g., number of unique defects detected), it provides a confidence interval of effectiveness based on the analysis of a collection of test sets. FETQ is demonstrated by measuring the chip-detection capability of several static and adaptive test metrics using tester data from actual ICs.

Systematic defects due to design-process interactions are a significant component of integrated circuit (IC) yield loss in nano-scale technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that will affect a product over its manufacturing lifetime. This paper describes a comprehensive methodology that addresses the prevention and identification of systematic defects. For prevention, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of design-for-manufacturability (DFM) rules in preventing systematic defects that is based on volume diagnosis data. A second method called LASIC (Layout Analysis for Systematic Identification using Clustering), also based on volume diagnosis data, has been developed for identifying systematic defects that escape DFM. To validate RADAR and LASIC, a fast and accurate defect simulation framework called SLIDER (Simulation of Layout-Injected Defects for Electrical Responses) has been developed. SLIDER generates virtual failure data with known defect characteristics. Experiments involving two industrial chips and virtual failure data from SLIDER demonstrate the effectiveness of RADAR and LASIC.

As integrated circuit (IC) manufacturing entered the nano-scale era, defect observability has greatly diminished. As a result, test-fail data diagnosis and mining are playing an indispensable role in providing feedback for yield learning. Accurate simulation of defect behavior is vital to this process but, unfortunately, cannot be achieved with simulation at the logic-level alone. This work proposes a framework to enable fast and accurate defect simulation, by making use of existing and well-developed mixed-signal simulation technology (traditionally used for design verification). While previous work has considered this topic before, the innovation here centers on two aspects: (i) accuracy resulting from defect injection taking place at the layout level, (ii) speedup resulting from careful and automatic partitioning of the circuit into digital and analog domains for mixed-signal simulation, and (iii) complete automation that involves defect injection, design partitioning, netlist extraction, mixed-signal simulation, and test-data extraction. The mixed-signal framework developed can be applied in a variety of settings that include diagnosis resolution improvement, defect localization, fault model evaluation, and virtual failure data creation. Experiments demonstrate that the proposed framework is scalable to handle large designs efficiently. A second set of experiments demonstrates how defect localization can be dramatically improved (>; 53%) by more accurate defect simulation.

Integrated, heterogeneous systems are comprehensively tested to verify whether their performance specifications fall within some acceptable ranges. However, explicitly testing every manufactured instance against all of its specifications can be expensive due to the complex requirements for test setup, stimulus application, and response measurement. To reduce manufacturing test cost, we have developed a methodology that uses binary decision forests and several test-specific enhancements for identifying redundant tests of an integrated system. Feasibility is empirically demonstrated using test data from over 70 000 manufactured instances of an in-production microelectromechanical system accelerometer, and over 4 500 manufactured instances of an RF transceiver. Through our analysis, we have shown that the expensive cold-mechanical test of the accelerometer and nine out of the 22 RF tests of the transceiver are likely redundant.

Researchers from both academia and industry continually propose new fault models and test metrics for coping with the ever-changing failure mechanisms exhibited by scaling fabrication processes. Understanding the relative effectiveness of current and proposed metrics and models is vitally important for selecting the best mix of methods for achieving a desired level of quality at reasonable cost. Evaluating metrics and models traditionally relies on actual test experiments, which is time-consuming and expensive. To reduce the cost of evaluating new test metrics, fault models, design-for-test techniques, and others, this paper proposes a new approach, MEeasuring Test Effectiveness Regionally (METER). METER exploits the readily available test-measurement data that is generated from chip failures. The approach does not require the generation and application of new patterns but uses analysis results from existing tests, which we show to be more than sufficient for performing a thorough evaluation of any model or metric of interest. METER is demonstrated by comparing several metrics and models that include: 1) stuck-at; 2)N-detect; 3)PAN-detect (physically-awareN-detect); 4) bridge fault models; and 5) the input pattern fault model (also more recently referred to as the gate-exhaustive metric). We also provide in-depth discussion on the advantages and disadvantages of METER, and contrast its effectiveness with those from the traditional approaches involving the test of actual integrated circuits.

In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize, and monitor spatially-correlated inter-die and/or intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs in compressed sensing to accurately predict spatial variations from an exceptionally small set of measurement data, thereby reducing the cost of silicon characterization. By exploring the underlying sparse pattern in spatial frequency domain, VP achieves substantially lower sampling frequency than the well-known Nyquist rate. In addition, VP is formulated as a linear programming problem and, therefore, can be solved both robustly and efficiently. Our industrial measurement data demonstrate the superior accuracy of VP over several traditional methods, including 2-D interpolation, Kriging prediction, and k-LSE estimation.

A technique is proposed to automatically predict whether a failing chip has a bridge defect. Logic diagnosis is performed using scan test results to identify candidate nets. Several relevant features of the test data are measured for net pairs that consist of the diagnosis candidates and other nets in close physical proximity. Based on these features, rules are constructed to identify defects that fully exhibit classic bridge behaviors, while the remaining chips are classified using a forest of decision trees. Results indicate that a population of chips failing due to bridges can indeed be extracted with very high accuracy. Finally, the method correctly classifies 41 commercially-fabricated chips that underwent PFA.

Systematic defects due to design-process interactions are a dominant component of integrated circuit (IC) yield loss in nano-scaled technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that affect the product. This paper describes a method that uses diagnosis to identify layout features that do not yield as expected. Specifically, clustering techniques are applied to layout snippets of diagnosis-implicated regions from (ideally) a statistically-significant number of IC failures for identifying feature commonalties. Experiments involving an industrial chip demonstrate the identification of possible systematic yield loss due to lithographic hotspots.

We propose a methodology that effectively estimates the defect-type distribution that affects a design fabricated in a given manufacturing process. Understanding the distribution can improve design quality, test quality, and the manufacturing process itself. The methodology is composed of i) an improved approach for identifying the signal lines relevant to defect activation at each site reported by diagnosis, ii) a new behavior attribution method, and iii) a novel approach to estimate the defect-type distribution. The efficacy of this methodology is validated using circuit-level simulation experiments. The results show that the method achieves an average accuracy of 94% in identifying signal lines that are relevant to the activation of a defect. When estimating defect-type distribution for a population affected by a variety of defects, the average estimation accuracy is 92% with ideal diagnosis. With a realistic diagnosis (i.e., the inherent ambiguity of diagnosis is accounted for), the estimated defect-type distribution is 85% accurate, on average.

Sub-wavelength lithography uses light waves that have a longer wavelength than the feature size that is being printed. Image distortions are an inevitable consequence of this situation, even after resolution enhancement techniques have been applied. This paper studies in detail how the image distortion in a fabricated IC can impact test and critical-area yield loss. Particularly, lithography simulation is performed on the desired pattern to predict the printed (distorted) pattern. The impact on critical-area yield loss is studied using both the desired pattern and the printed pattern. Similarly, the impact on test is studied using inductive fault analysis on both the desired pattern and the printed pattern. Even under the assumption of the best process conditions, experiment results indicate that the difference in misdirected test effort can be as large as 8.0% and the difference in the critical-area yield calculations is about 3.4% for a large design. The more accurate analysis requires a runtime increase of 5X on average.

In this paper, we present a vision for the cointegration of deeply scaled complementary metal-oxide-semiconductor (CMOS) and emerging nanoelectronic devices into CMOS-hybrid systems. These hybrid systems will create new functionality, modality and add value to existing CMOS integrated circuits. We describe several new nanoelectronic devices which may enable new dimensions to traditional CMOS circuits and systems that build on CMOS compatible, parallel nanoscale fabrication methods. In addition, we show that the integration of multimodal sensors and nonvolatile memory enables a platform of self-evolving hardware that is able to adapt to fabrication variation, environmental changes, and applications changes on-the-fly.

This paper describes a multiple-defect diagnosis methodology that is flexible in handling various defect behaviors and arbitrary failing pattern characteristics. Unlike some other approaches, the search space of the diagnosis method does not grow exponentially with the number of defects. Results from extensive simulation experiments and real failing integrated circuits show that this method can effectively diagnose circuits that are affected by a large (>20) or small number of defects of various types. Moreover, this method is capable of accurately estimating the number of defective sites in the failing circuit.

Integrated circuit (IC) diagnosis typically analyzes failed chips by reasoning about their responses to test patterns to deduce what has gone wrong. Current trends use diagnosis as the first step in extracting valuable information from a large population of failing ICs that include, for example, design-feature failure rates and defect-occurrence statistics. However, it is difficult to examine the accuracy of these techniques because of the unavailability of sufficient fail data where such information is known. This paper describes an approach for benchmarking and verifying diagnosis techniques through failure population creation that builds on prior work in this area. Specifically, we describe how a population of realistic IC failures is created through circuit-level simulation of extracted layouts. The most novel feature of the work is that the virtual test responses produced are both a precise function of defect type and the three-dimensional location within the layout. The extended approach is demonstrated using twelve placed-and-routed circuits. An example application of the developed framework is given to illustrate the utility of having a failure population where the location and type of defect are known a priori.

In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs in compressed sensing [15]-[17] to accurately predict spatial variations from an exceptionally small set of measurement data, thereby reducing the cost of silicon characterization. By exploring the underlying sparse structure in (spatial) frequency domain, VP achieves substantially lower sampling frequency than the well-known (spatial) Nyquist rate. In addition, VP is formulated as a linear programming problem and, therefore, can be solved both robustly and efficiently. Our industrial measurement data demonstrate that by testing the delay of just 50 chips on a wafer, VP accurately predicts the delay of the other 219 chips on the same wafer. In this example, VP reduces the estimation error by up to 10× compared to other traditional methods. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids — Verification General Terms Algorithms

Test metrics and fault models continue to evolve to keep up with defect characteristics associated with ever-changing fabrication processes. Understanding the relative effectiveness of current and proposed metrics and models is therefore important for selecting the best mix of methods for achieving a desired level of quality at reasonable cost. Test-metric and fault model evaluation traditionally relies on large, time-consuming silicon-based test experiments. Specifically, tests generated for some specific metric/model are applied to real chips, and unique chip-fail detections are used as relative measures of effectiveness. To reduce the cost of evaluating new test metrics, fault models, DFT techniques, etc., this work proposes a new approach that exploits the readily-available test-measurement data in chip-failure log files. The new approach does not require the generation and application of new patterns but uses analysis results from existing tests. We demonstrate the method by comparing several metrics and models that include: (i) stuck-at, (ii) N-detect, (iii) PAN-detect (physically-aware N-detect), (iv) bridge fault models, and (v) the input pattern fault model (also more recently referred to as the gate-exhaustive metric).

In test compaction, the objective is to reduce cost of testing an integrated system by applying a subset of its specification-based tests. One approach for accomplishing this objective is to statistically learn a correlation function for the tests eliminated from a collection of systems that are fully tested (i.e., training data). Accuracy of this correlation function may degrade over the life span of an integrated system however. We describe an adaptive scheme that (1) uses stratified sampling to check the accuracy of a correlation function at various time instances and (2) re-learns a function when its accuracy dips below some tolerable threshold. This methodology is applied to test data from two in-production integrated systems, namely, an accelerometer and a phase-locked loop. Experiments that use over 200,000 real chips demonstrate that the difference between actual function accuracy and its estimate using stratified sampling is smaller than 2%. Moreover, our adaptive re-learning is able to improve the accuracy for one out of three accelerometer and one out of three PLL sampling instances where the function accuracy was unacceptable.

Physically-aware N-detect (PAN-detect) test has been demonstrated to improve defect detection for modern designs. One existing approach for PAN-detect test generation that is applicable for industrial designs generates fully-specified test sets. This work presents a PAN-detect test relaxation methodology that can be applied to both physically-aware test sets as well as arbitrary test sets. The methodology enhances PAN-detect test applicability by allowing test-input values to be unspecified as don’t cares, which can be utilized for test compression, scan-power reduction, and test enrichment. The test quality of the relaxed test set is maintained by preserving the PAN-detect coverage of the original test set. Experiment results demonstrate that the physically-aware N-detect test relaxation approach relaxes, on average, 42% of the test-input values while preserving PAN-detect coverage.

We propose to achieve and maintain ultra-high quality of digital circuits on a per-design basis by (i) monitoring the type of failures that occur through volume diagnosis, and (ii) changing the test patterns to match the current failure population characteristics. Opposed to the current approach that assumes sufficient quality levels are maintained using the tests developed during the time of design, the methodology described here presupposes that fallout characteristics can change over time but with a time constant that is sufficiently slow, thereby allowing test content to be altered so as to maximize coverage of the failure types actually occurring. Even if this assumption proves to be false, the test content can be tuned to match the characteristics of the fallout population if the fallout characteristics are unchanging. Under either scenario, it should be then possible to minimize DPPM for a given constraint on test costs, or alternatively ensure that DPPM does not exceed some pre-determined threshold. Our approach does not have to cope with situations where fallout characteristics change rapidly (e.g. excursion), since there are existing methods to deal with them. Our methodology uses a diagnosis technique that can extract defect activation conditions, a new model for estimating DPPM, and an efficient test selection method for reducing DPPM based on volume diagnosis results. Circuit-level simulation involving various types of defects shows that DPPM could be reduced by 30% using our methodology. In addition, experiments on a real silicon chip failures show that DPPM can be significantly reduced, without additional test execution cost, by altering the content (but not the size) of the applied test set.

Traditional software-based diagnosis of failing chips typically identifies several lines where the failure is believed to reside. However, these lines can span across multiple layers and can be very long in length. This makes physical failure analysis difficult. In contrast, there are emerging diagnosis techniques that identify both the faulty lines as well as the neighboring conditions for which an affected line becomes faulty. In this paper, an approach is presented to improve failure localization by automatically analyzing the information associated with the outcome of diagnosis. Experimental results show a significant improvement in failure localization when this method is applied to 106 real IC failures.

We propose an effective multiple defect diagnosis methodology that does not depend on failing pattern characteristics. The methodology consists of a conservative defect site identification and elimination algorithm, and an innovative path-based defect site elimination technique. The search space of the diagnosis method does not grow exponentially with the number of defects in the circuit under diagnosis. Simulation experiments show that this method can effectively diagnose circuits that are affected by 10 or more faults that include multiple stuck-at, bridge and transistor stuck-open faults.

Circuit fabrics composed of highly regular structures, called logic bricks, have been described recently for improving yield. An automated logic brick design flow based on a SAT formulation of the brick routing has been developed to minimize wire length and the number of vias while maintaining several design-for-manufacturability constraints. In this work, testability enhancements are imposed into a logic brick to reduce the likelihood of (i) feedback bridges to improve test and (ii) equivalent faults to improve diagnosis. This is accomplished by adding constraints to the SAT formulation of the logic brick routing that restricts certain wires from being routed in close proximity, thus making bridges between them unlikely. Application to several brick designs resulted in critical-area reductions for targeted bridges with little degradation in terms of additional wire length and via count.

N-detect test has been shown to have a higher likelihood for detecting defects. However, traditional definitions of N-detect test do not necessarily exploit the localized characteristics of defects. In physically-aware N-detect test, the objective is to ensure that the N tests establish N different logical states on the signal lines that are in the physical neighborhood surrounding the targeted fault site. We present a test selection procedure for creating a physically- aware N-detect test set that satisfies a user-provided constraint on test-set size. Results produced for an industrial test chip demonstrate the effectiveness and practicability of our pattern selection approach. Specifically, we show that we can virtually detect the same number of faults 10 or more times as a traditional 10-detect test set and increase the number of neighborhood states and the number of faults with 10 or more states by 18.0 and 4.7%, respectively, without increasing the number of tests over a traditional 10-detect test set.

To mitigate fluctuations in the accuracy of test compaction, we propose to periodically verify this accuracy using stratified samples and adaptively update the models when it degrades below some acceptable limit. Application to an in-production accelerometer demonstrates the feasibility of this methodology.

Physically-aware N-detect attempts to improve the detection characteristics of traditional N-detect by exploiting the localized characteristics of defects. Specifically, in addition to detecting each fault N times, we also require that the physical neighborhood surrounding the target change state as well. In this work, the effectiveness of the physically-aware metric is examined using two approaches. First, tester responses from an in-production IBM chip are analyzed to compare the physically-aware N-detect test with other traditional tests that include stuck-at, IDDQ, logic BIST, and delay tests. Second, diagnostic results from LSI chip failures are utilized to directly compare the traditional and physically-aware N-detect metrics. Results from both experiments demonstrate the effectiveness of physically-aware N-detect test in detecting defects in modern industrial designs.

A multiple defect diagnosis methodology consisting of a defect site identification and elimination method, a path-based defect site elimination method, and a defect site selection and ranking method is described. The flexibility of the diagnosis method in handling various defect behaviors and arbitrary failing pattern characteristics is demonstrated through extensive simulations. Unlike some competing approaches, the search space of the diagnosis method does not grow exponentially with the number of defects. Results from over 1700 simulated and 131 failing ICs show that this method can effectively diagnose circuits that are affected by a large (>20) or small number of defects of various types. Specifically, when diagnosing circuits with more than 20 defects, our method identifies 65% of them, and the number of sites reported per actual defective site is, on average, 1.17. For circuits affected by two defects, these numbers change to 86% and 1.85, respectively. Finally, 84% of our top-ranked sites are actual defect sites.

We propose a methodology that employs boolean minimization and optimized test covering to identify redundant tests of a mixed-signal circuit from its pass-fail (binary) test data. This methodology is applied to two in-production circuits, a high-speed serializer/deserializer (HSS) and a phase-locked loop (PLL). Application of the methodology to over 38, 000 failing HSS circuits demonstrate that only 0.016% of them are mispredicted when three of nine high- voltage HSS tests are eliminated. Similarly, analysis of 22, 000 failing PLL circuits results in an error of 0.032% when 11 out of the 36 PLL tests are eliminated. Assuming 90% yield, these misprediction levels for the HSS and the PLL designs are equivalent to 16 and 32 DPM, respectively. The cost savings from eliminating the redundant tests in the HSS and the PLL designs at 90% yield are however estimated to be 21.9% and 30.9%, respectively.

An objective of delay fault diagnosis is to enable characterization of the source and nature of timing failure in an integrated circuit. However, the most commonly studied defect models (the gate-delay and path-delay fault models) do not adequately capture the complex timing characteristics that a delay fault can exhibit. In this work, we present a novel diagnostic technique that is used to extract an accurate delay fault model we call a segment network fault without the need for any timing information. In our simulation-based experiments, we successfully diagnose delay faults of varying complexity demonstrating the usefulness of the new delay fault model for the purposes of delay defect characterization.

Multiple-detect test sets detect single stuck line faults multiple times, and thus have a higher probability of detecting complex defects. But current definitions of what constitutes a new test for a single stuck line fault do not leverage defect locality. Recent work has proposed a new metric to capture quality of a multiple-detect test set based on the number of unique states on lines in the physical neighborhood of a targeted line. This paper presents a new ATPG strategy that uses this metric to generate higher quality multiple-detect test sets.

Defect density and defect size distributions (DDSDs) are key parameters used in IC yield loss predictions. Traditionally, memories and specialized test structures have been used to estimate these distributions. In this paper, we propose a strategy to accurately estimate DDSDs for shorts in metal layers using production IC test results

It is now generally accepted that the stuck-at fault model is no longer sufficient for many manufacturing test activities. Consequently, diagnostic test pattern generation based solely on distinguishing stuck-at faults is unlikely to achieve the resolution required for emerging fault types. In this work we describe a new diagnostic ATPG implementation that uses a generalized fault model. It can be easily used in any diagnosis framework to refine diagnostic resolution for complex defects. For various types of faults that include, for example, bridge, transition, and transistor stuck-open, we show that diagnostic resolution can be significantly enhanced over a traditional diagnostic test set aimed only at stuck-at faults. Finally, we illustrate the use of our diagnostic ATPG to distinguish faults derived from a state-of-the-art diagnosis flow based on layout

DIAGNOSIX is a comprehensive fault diagnosis methodology for characterizing failures in digital ICs. Using limited layout information, DIAGNOSIX automatically extracts a fault model for a failing IC by analyzing the behavior of the physical neighborhood surrounding suspect lines. Results from several simulated and over 800 failing ICs reveal a significant improvement in localization. More importantly, the output of DIAGNOSIX is an accurate model of the logic-level defect behavior that provides useful insight into the actual defect mechanism. Experiment results for the failing chips with successful physical failure analysis reveal that the extracted faults accurately describe the actual defects

Inductive fault analysis is the process of determining which defects are likely to occur in an integrated circuit for a given manufacturing process. Although IFA provides a more accurate defect list for test than standard fault models, it typically retires a significant amount of computation time. We propose, a methodology that exploits the physical regularity of a design to reduce the computation time, required for IFA. This methodology was applied to several designs implemented in a via-programmable gate array (an example of a regular circuit fabric) and shown to provide an average speedup of 46times

Fault tuples represent a defect modeling mechanism capable of capturing the logical misbehavior of arbitrary defects in digital circuits. To justify this claim, this paper describes two types of logic faults (state transition and signal line faults) and formally shows how fault tuples can be used to precisely represent any number of faults of this kind. The capability of fault tuples to capture misbehaviors beyond logic faults is then illustrated using many examples of varying degree of complexity. In particular, the ability of fault tuples to modulate fault controllability and observability is examined. Finally, it is described how fault tuples can and have been used to enhance testing tasks such as fault simulation, test generation, and diagnosis, and enable new capabilities such as interfault collapsing and application-based quality metrics

The defects and the corresponding behavior caused by particle contaminants introduced into the fabrication of a combdrive surface-micromachined microresonator are investigated. The microresonator is chosen as a research vehicle since it possesses all the primitive elements used in many types of capacitive-based microelectromechanical systems (MEMS). Fabrication process simulation is used to predict all the possible defective structures caused by contaminants. The resulting defects are then classified based on their geometrical properties. Mechanical and electrical simulations are also used to determine the impact of defect classes on key mechanical and electrical characteristics of the microresonator. This analysis reveals that particles can cause various mechanical defects that include anchors, broken beams, and bridged comb fingers, all of which can have a significant impact on mechanical behavior. On the other hand, there are mechanical defects (e.g., a broken comb finger) that virtually have no effect on mechanical properties but can lead to catastrophic changes in electrical capability

Testing a non-digital integrated system against all of its specifications can be quite expensive due to the elaborate test application and measurement setup required. We propose to eliminate redundant tests by employing /spl epsi/-SVM based statistical learning. The application of the proposed methodology to an operational amplifier and a MEMS accelerometer reveal that redundant tests can be statistically identified from a complete set of specification-based tests, with negligible error. Specifically, after eliminating five of eleven specification-based tests for an operational amplifier, the defect escape and yield loss is small at 0.6% and 0.9%, respectively. For the accelerometer, defect escape of 0.2% and yield loss of 0.1% occurs when the hot and cold tests are eliminated. For the accelerometer, this level of compaction would reduce test cost by more than half.

We present a methodology for diagnosing arbitrary defects in digital integrated circuits (ICs). Rather than using one or a set of fault models in a cause-effect or effect-cause approach, our methodology derives defect behavior from, the test set, the circuit and its response, and the physical neighbors that surround a potential defect location. The defect locations themselves are identified using a model-independent stage. The methodology enables accurate identification of defect location and behavior through validation via simulation using passing and additional diagnostic test patterns. A byproduct of our methodology is the distinction that can be made among stuck-fault equivalencies which results in improved diagnostic resolution. Several types of shorts and opens are used to demonstrate the applicability of our approach to the diagnosis of arbitrary defects.

A built-in self-test algorithm is developed for chemically-assembled electronic nanotechnology (CAEN) that exploits reconfigurability to achieve 100% fault coverage and nearly 100% diagnostic accuracy. This algorithm is particularly suited for regular architectures with high defect densities.

Diagnosis algorithms for integrated circuits (ICs) are typically developed and evaluated using a limited number of logic-level models of defect behaviors. However, it is well-known that real IC defects exhibit behavior well outside these models. Consequently, the utility of IC diagnosis methodologies may be uncertain. A simulation-based benchmarking strategy is developed that uses circuit-level models to describe the complex nature of real defects. Specifically, we have proposed a simple yet powerful strategy using a small circuit and a set of bounded deformations (i.e., defects) for measuring the effectiveness of diagnosis techniques. Evaluation of several simple and commercial diagnosis algorithms indicates that this form of diagnosis benchmarking is viable.

Fault tuples have introduced a fault model independent methodology for digital circuit test analysis. However, the {0, 1, X} algebra currently used with fault tuples allows only one form of path sensitization. The sensitization options for fault tuples is enhanced based on a 5-value algebra. The 5-value algebra enables a more detailed test analysis through the selection of one of three types of sensitization. Simulation experiments performed using the ITC'99 benchmark circuits for transition and path delay faults reveal that faults can be simultaneously analyzed under different types of sensitization criteria with little increase in memory and CPU time.

A mathematical model analyzing the efficacy of a built-in self-test technique, applicable to any symmetrical MEMS microstructure, is developed. The model predicts that the BIST technique can also be used to characterize a wide range of local manufacturing variations affecting different regions of the device. Model predictions have been validated by simulation. Specifically, it has been shown that by using a suitable modulation scheme, sensitivity to linear etch variation along a particular direction is improved by nearly 30%.

Multiple-detect test sets have been shown to be effective in lowering defect level. Other researchers have noted that observing the effects of a defect can be controlled by sensitizing affected sites to circuit outputs but defect excitation is inherently probabilistic given a defect’s inherent, unknown nature. As a result, test sets that sensitize every signal line multiple times with varying circuit state has a greater probability of detecting a defect. In past work, the entire circuit is considered when varying circuit state from one vector to another for a given signal line. However, it may be possible to improve defect excitation by exploiting the localized nature of many defect types. Spec$cally, by varying circuit state in the physical region or neighborhood surrounding a line affected by a defect, the defect excitation and therefore detection can be improved. In this paper, we present a method for extracting a physical region surrounding a signal line but more importantly, techniques for analyzing the excitation characteristics of the region. Analysis of 4-detect test sets reveals that 30% to 60% of signal line regions do not achieve at least four unique states, indicating opportunity to further reduce defect level.

A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of a domino gate in the presence of crosstalk is developed and exploited by a new efJicient timing analysis algorithm. The algorithm uses a single, breadth-jirst traversal to compute delays in the presence of crosstalk. Thus, it avoids the iterative methods commonly employed for static CMOS circuits. The timing analysis technique is used to generate test input vectors that exercise the worst-case delays of a multiplier circuit implemented using domino logic. Hspice simulation results demonstrate that the technique identiJes test vectors that produce circuit delay that satisfy the targeted value in the presence of crosstalk.

Abstract This paper argues that the existing approaches to modelingand characterization of IC malfunctions are inadequate fortest and yield learning of Deep Sub-Micron (DSM) products.Traditional notions of a spot defect and local and global pro-cess variations are analyzed and their shortcomings areexposed. A detailed taxonomy of process-induced deforma-tions of DSM IC structures, enabling modeling and charac-terization of IC malfunctions, is proposed. The blueprint of aroadmap enabling such a characterization is suggested. Keywords : yield learning, fault modeling, defects, diagno-sis, defect characterization. 1 Introduction The motivation, purpose and overall structure of this paperhave already been explained in the abstract above. The dis-cussion of the prior and relevant publications should be thenext natural component of this paper. But it is skipped aswell, even if there exists substantial body of relevant publi-cations in the related domain (some of them are listed as ref-erences in [1,2].) It is skipped to avoid unnecessarydiscussion of the weaknesses of related results presented inthe past. Simply, majority of published papers with the ICtechnology-oriented flavour (and prime examples are the fol-lowing papers co-written by the first author of this paper [3,4, 5, 6, 7, 8]) do not offer sufficient insight into failure mech-anisms to address challenges posed by the DSM era prod-ucts. A substantial portion of this paper attempts to justify theabove, somewhat provocative claim. Then the remainingportion of the paper is used to suggest directions of theresearch, which we should undertake to truly assist test andyield learning of modern era ICs.

We present an efficient algorithm for identification of two-line bridges in combinational CMOS logic that narrows down the two-line bridge candidates based on tester responses for voltage tests. Due to the implicit enumeration of bridge sites, no layout extraction or precomputed stuck-at fault dictionaries are required. The bridge identification is easily refined using additional test pattern results when necessary. We present results for benchmark circuits and four common fault models (wired-AND, wired-OR, dominant, and composite), evaluate the diagnosis against other possible fault types, and summarize the quality of our results. 1.

A review of traditional IC failure analysis techniques strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard single stuck-line- (SSL-) based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting nontargeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

Diagnosis of malfunctioning deep-submicron (DSM) ICs is becoming more difficult due to the increasing sophistication of the manufacturing process and the structural complexity of the IC itself. At the same time, key diagnostic tasks that include defect localization are still solved using primitive models of the IC's defects. This paper explores the use of "fault tuples" in diagnosis. Fault tuples can accurately mimic the complex misbehavior of DSM ICs at the logic level, enabling practical diagnosis of large circuits. Initial assessment of the use of fault tuples in diagnosis is performed based on a case study involving one specific category of polysilicon spot defects. Obtained results indicate that fault tuples may enhance diagnosis significantly.

A built-in self-test technique for MEMS that is applicable to symmetrical microstructures is described. A combination of existing layout features and additional circuitry is used to make measurements from symmetrically-located points. In addition to the normal sense output, self-test outputs are used to detect the presence of layout asymmetry that are caused by local, hard-to-detect defects. Simulation results for an accelerometer reveal that our self-test approach is able to distinguish misbehavior resulting from local defects and manufacturing process variations.

Local dominance and equivalence relationships for a single fault type have been exploited to reduce test set size and test generation time. However, these relationships have not been explored for multiple fault types. Using fault tuples, we describe how local dominance and equivalence relationships across various fault types can be derived. We also describe how the derived relationships can be used to order the faults efficiently for test generation in order to reduce test set size. Initial results using our ordered fault lists for ISCAS85 and ITC99 benchmark circuits reveals that test set size can be reduced by as much as 19%.

As technology scales into the deep submicron regime, capacitive coupling between signal lines becomes a dominant problem. Capacitive coupling is more acute for domino logic circuits since an irreversible, unwanted gate output transition can result. We present a timed test generation methodology for CMOS domino circuits that assigns the circuit inputs so that capacitively-coupled aggressors of a victim line transition in time proximity which creates a noise effect that is propagated within the clock-cycle constraint. Experiments for a multiplier reveal that a high level of accuracy is achieved without significant test generation time, resulting in a nearly 50% reduction in the number of sites earlier believed to be susceptible to crosstalk failure.

Recent developments in the field of MEMS indicate a clear move toward systems, rather than just individual components. Design and fabrication of these components include new methods and techniques. Does testing require new methodologies and tools ? Will we be able to include MEMS in the SoCs flow ?

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. The authors address the charge-sharing noise issue. Specifically, they develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice simulations. The model is used to generate test vectors using a generalized ATPG tool. The charge-sharing model and the corresponding tests are validated using Hspice simulations on industrial circuits and it is also demonstrated that test vectors that establish high amounts of charge sharing could be generated for most domino gates.

Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs. In order to avoid excessive conservatism in static timing analysis, it is important to determine if aggressor lines can potentially switch simultaneously with the victim. In this paper, we present a comprehensive ATPG-based approach that uses functional information to identify valid interactions between coupled lines. Our algorithm accounts for glitches on aggressors that can be caused by static and dynamic hazards in the circuit. We present results on several benchmark circuits that show the value of considering functional information to reduce the conservatism associated with worst-case coupled line switching assumptions during static timing analysis.

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. In this paper, we address the charge sharing noise issue. Specifically, we develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice simulations. The model is used to generate test vectors using a generalized ATPG tool. The charge-sharing model and the corresponding tests were validated using Hspice simulations on industrial circuits and it was also demonstrated that test vectors that establish high amounts of charge sharing could be generated for most domino gates.

We introduce a new fault representation mechanism for digital circuits based on fault tuples. A fault tuple is a simple 3-element condition for a signal line, its value, and clock cycle constrain t. AND-OR expressions of fault tuples are used to represent arbitrary misbehaviors. A fault simulator based on fault tuples was used to conduct experiments on benc hmark circuits. Simulation results show that a 17% reduction of average CPU time is achiev ed when performing sim ulation on all fault types simultaneously, as opposed to individually. We expect further improvements in speedup when the shared characteristics of the various fault types are better exploited.

The effect of vertical stiction, foreign particles, and etch variation on the resonant frequency of a surface-micromachined resonator and accelerometer are presented. For each device, it is shown that misbehaviors resulting from different failure sources can overlap, exhibit dominance and combine to create behavior masking and construction. Such an analysis is essential for developing test and diagnosis methodologies for surface-micromachined MEMS.

A test generation tool for combinational circuits called FATGEN has been developed based on the notion of fault tuples. FATGEN can be used to simultaneously generate tests for many types of misbehavior that occur in digital systems. Individual experiments involving SSL, transistor stuck-open, path delay and bridging faults for the ISCAS85 benchmark circuits reveal an average speedup of nearly 32% and test set compaction of 60% when faults of all types are analyzed simultaneously. In addition, there is an average reduction of approximately 34% in the number of aborted faults.

Capacitative coupling will become a dominant problem due to increased parasitic capacitance between adjacent wires and faster signal switching rates. The coupling problem is more acute for domino logic circuits since an irreversible gate output transition can result. We present a method to analyze domino circuits for susceptibility to crosstalk failures from a layout-extracted netlist. Specifically, sites in the circuit that may fail due to crosstalk are identified. In addition, failure sites are partitioned into two categories (faults or design errors) based on their likelihood of occurrence in the context of manufacturing variations. The method has been implemented and applied to a dual-rail domino Wallace tree circuit with little loss in accuracy, resulting in a 37X speedup over a full analysis using Hspice.

A design methodology for implementing fast, easily testable arithmetic-logic units (ALUs) is presented. Here, we describe a set of fast adder designs, which are testable with a test set that has either /spl theta/(N) complexity (Lin-testable) or /spl theta/(1) complexity (C-testable), where N is the input operand size of the ALU. The various levels of testability are achieved by exploiting some inherent properties of carry-lookahead addition. The Lintestable and C-testable ALU designs require only one extra input, regardless of the size of the ALU. The area overhead for a high-speed 64-bit Lintestable ALU is only 0.5%.

We investigate the failure modes of a comb-drive surface-micromachined microresonator that are caused by particulate contaminations. The microresonator structure is chosen as our research vehicle because it possesses all the primitive components found in many capacitive-based MEMS sensors and actuators. Process simulation is used to create the full-spectrum of defective structures caused by foreign particles. The generated defective structures are then classified based on their geometrical properties. Finite element analysis is used to understand the impact of these defects on the mechanical frequency response of the microresonator while HSPICE simulations are performed to determine the corresponding electrical misbehaviors within an acceleration measuring application. Simulation results show that particles can cause unwanted anchors, broken beams and welded comb fingers. However, the most interesting defects are broken comb fingers and lateral finger protrusions that only affect sensing capacitance. These defects lead to a very small increase or decrease in the shuttle mass. The mass change is so small that the mechanical frequency response of the resonator is virtually unchanged. However, the HSPICE simulations show that the change in output sensing voltage can be catastrophic.

Genetic algorithms have proven to be a viable solution to the NP-complete problem of test vector generation. However the parameters used to control GA-based ATPG can greatly affect test set size, fault coverage and CPU execution time. Knowing how a given set of parameters will affect each of these factors a priori allows for more efficient testing procedures. Over 1 million ATPG experiments were conducted on the ISCAS85 benchmark set exploring a wide range of parameter options. Although sequential circuit testing looms as the larger problem, investigating combinational circuits should provide direction as to where efforts should be focused. From our experiments, we derive regression-based equations utilizing circuit characteristics and various controllable parameters. Using these equations, the ATPG tool determines parameter values that maximize fault coverage while meeting constraints on CPU run times and test set size. For many circuits tested, fault coverage improved with a tolerable increase in CPU time.

Wafer-level testing of surface-micromachined sensors provides new challenges to the test community. Currently, there is no method available for performing direct measurements to assess faulty micromechanical structures. Most commercial methods use electrical measurements to deduce the physical source of failures in the micromechanical structure. As a result, the process of identifying various failure modes (electrical measurements) and accurately mapping them to the underlying physical failure mechanisms of the mechanical sensor becomes highly complex. Several sources of failures that include particulates and stiction complicate the situation even more. Here, we provide a case study of the Analog Devices ADXL75 Accelerometer. One failure category called stuck/tipped beams is investigated and a methodology is developed to uniquely distinguish failures either caused by stuck or tipped beams. The proposed method is easy to implement and the information obtained can be critical for yield improvement.

We have enhanced the process simulator CODEF (1996) into a tool called CARAMEL (Contamination And Reliability Analysis of MicroElectromechanical Layout) for analyzing the impact of contamination particles on the geometrical and material properties of microelectromechanical systems (MEMS). CARAMEL accepts as input a microelectromechanical layout, a particulate description, and a process recipe. CARAMEL produces a mesh description of the defective layout that is completely compatible with the electromechanical simulator ABAQUS (1995). Analysis of CARAMEL's output indicates that a wide range of defective structures are possible due to the presence of contaminations. Moreover, electromechanical simulations of CARAMEL's mesh representations of defective layout has revealed that a wide variety of faulty behaviors are associated with these defects. In this paper, we describe CARAMEL and its application to the development of realistic fault models for MEMS.

Recent work in IC failure analysis strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting non-targeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

Microelectromechanical systems (MEMS) are miniature electromechanical sensor and actuator systems developed from the mature batch-fabricated processes of VLSI technologies. Projected growth in the MEMS market requires significant advances in CAD and manufacturing for MEMS. These advances must be accompanied with testing methodologies that ensure both high quality and reliability. We describe our approach for developing a comprehensive testing methodology for a class of MEMS known as surface micromachined sensors. Our first step involving manufacturing process and low-level mechanical simulations is illustrated by studying the effects of realistic contaminations on the folded-flexure comb-drive resonator. The simulation results obtained indicate that realistic contaminations can create a variety of defective structures that result in a wide spectrum of faulty behaviors.

Despite a substantial amount of prior work in design-for-testability (DFT) cost modeling, the decision whether or not and how to use DFT is still not an easy one. The problem is that the relationship between DFT benefits and costs are still far from being well understood. The objective of this paper is to study the DFT decision-making process and to identify its missing or weak links. The first step of this study involved development of a new DFT cost/benefit trade-off modeling procedure. Next, the developed cost model (which we call the CMU Test Cost model) was used, with a range of parameters representing typical industrial conditions, to answer the question: to DFT or not to DFT. The obtained results indicate that in the DFT application space there exist regions in which one can provide a clear answer to this question. There also exist regions of uncertainty. One of the objectives of our study has been to identify ways of minimizing this uncertain region.

Current approaches to self test consist of adding hardware to the already synthesized circuits to transform them into autonomous finite state machines. If the circuit's own function is used for test generation and or data compression, then the fault coverage and aliasing properties have to be obtained by simulation. In this paper, we give a function-level specification for the self-test problem. In the self-test mode, all primary inputs and outputs are latched. The circuit behaves as an autonomous finite-state machine, which executes an Euler walk of all states. Thus, each state is visited exactly once, with all states forming a closed path in the state transition graph of the test machine. This function is embedded in the high-level description of the given finite state machine. The self-test hardware thus undergoes the same optimization process as the machine hardware, with a chance of better area/timing optimization. Up to 100% fault coverage against all single/multiple faults can be achieved if the appropriate synthesis/optimization tools are used. On completion of self-test the signature, consisting of the states of all flip-flops, is shown to have an aliasing probability 2/sup -m/ when the circuit has m flip-flops and the fault corrupts a single state-transition.

The design and implementation of a fast, easily testable arithmetic-logic unit (ALU) is described. It is built around an adder design which is level-testable (L-testable), implying that the number of test patterns required to detect all functional faults in modules grows logarithmically with the size of the ALU. L-testability is achieved by exploiting some inherent properties of carry-lookahead addition. The resulting ALU design requires only two extra inputs, regardless of the size of the ALU. For an 8-bit implementation that has little impact on performance, the area overhead is shown to be less than 9%.

The testing properties of a class of regular circuits called convergent trees are investigated. Convergent trees include such practical circuits as comparators, multiplexers, and carry-lookahead adders. The conditions for the testability of these tree circuits are derived for a functional fault model. The notion of L-testability is introduced, where the number of tests for a p-level tree is directly proportional to p, rather than exponential in p. Convergent trees that are C-testable (testable with a fixed number of tests, regardless of the tree's size) are also characterized. Two design techniques are also introduced that modify arbitrary tree modules in order to achieve Land C-testability. Finally, we apply these techniques to the design of a large carry-lookahead adder.