This live demonstration shows a frame-based CMOS vision sensor with high dynamic range for event generation. Our CMOS vision sensor features 64 × 64 processing elements that comprise one 4T-APS and local circuitry to provide events and high dynamic range extension. The event generation is performed synchronously through the threshold of the frame difference between consecutive frames. The dynamic range extension is carried out per-pixel with the overflow capacitance method. The sensor can reach up to thousands of event frames per second. Electrical simulations indicate a dynamic range of 85 dB, which narrows the gap with dynamic vision sensors.

This paper shows a FeFET-based analog multi-level unit cell for computing-in-memory applications for Deep Neural Networks (DNN). The FeFET-based unit cell performs input-weight multiplication with a Back-End-Of-Line (BEOL) ferro-electric HZO FeFET device on top of standard 180 nm CMOS circuits. The unit cell works with a feedback mechanism which combines an in-house FeFET device to store weights and CMOS transistors underneath to provide outputs in current mode to be integrated over time on a capacitor. Said feedback mechanism compensates for device-to-device variability, and would permit to calibrate a system against time variations, something not usually included in cross-bar solutions. Joint electrical simulations of the FeFET-CMOS circuit are performed with a compact Verilog-A model extracted from the experimental characterization of the FeFET devices. Electrical simulations show that our feedback approach leads to a multi-bit cell with 5-bits of resolution, superior to that of state-of-the-art solutions.

This paper describes a new Fine-Tuning approach for Few-Shot object detection in Videos that exploits spatio-temporal information to boost detection precision. Despite the progress made in the single image domain in recent years, the few-shot video object detection problem remains almost unexplored. A few-shot detector must quickly adapt to a new domain with a limited number of annotations per category. Therefore, it is not possible to include videos in the training set, hindering the spatio-temporal learning process. We propose augmenting each training image with synthetic frames to train the spatio-temporal module of our method. This module employs attention mechanisms to mine relationships between proposals across frames, effectively leveraging spatio-temporal information. A spatio-temporal double head then localizes objects in the current frame while classifying them using both context from nearby frames and information from the current frame. Finally, the predicted scores are fed into a long-term object-linking method that generates object tubes across the video. By optimizing the classification score based on these tubes, our approach ensures spatio-temporal consistency. Classification is the primary challenge in few-shot object detection. Our results show that spatio-temporal information helps to mitigate this issue, paving the way for future research in this direction. FTFSVid achieves 41.9 AP50 on the Few-Shot Video Object Detection (FSVOD-500) and 42.9 AP50 on the Few-Shot YouTube Video (FSYTV-40) dataset, surpassing our spatial baseline by 4.3 and 2.5 points. Additionally, FTFSVid outperforms previous few-shot video object detectors by 3.2 points on FSVOD-500 and 14.5 points on FSYTV-40, setting a new state-of-the-art.

This live demonstration shows a mixed-signal design in 180 nm CMOS technology that runs hyperdimensional computing (HDC) on binary hypervectors with up to 8,192 components. The chip comprises 64 × 128 processing elements (PE) arranged in a 2D mesh with direct connection to their first neighbors. PEs include a 1-bit ALU with a 16 6T-SRAM bank to execute HDC primitives. Hypervector classification is performed through the Hamming distance with current sources in every PE globally connected to an analog computing unit laid down outside the PE array. The overall approach results in tens of nJ of power consumption in inference, which is competitive with state-of-the-art solutions.

This live demonstration shows a mixed-signal Computer In Memory (CIM) macro deep neural network (DNN) integrated circuit in 180 nm CMOS technology for image recognition. Images are coded as pulse width modulation (PWM) signals. DNN weights are stored as voltages in 6T-SRAM memories which drive current sources inside every multiplier. Multipliers are arranged within processing elements laid down in a 2D mesh suitable for image processing. The power consumption per multiplier of the CIM macro is of 0.22 µW, below state-of-the-art competitors following the same multiply and accumulate (MAC) principle.

Abstract This paper addresses the problem of exploiting spatiotemporal information to improve small object detection precision in video. We propose a two-stage object detector called FANet based on short-term spatiotemporal feature aggregation and long-term object linking to refine object detections. First, we generate a set of short tubelet proposals. Then, we aggregate RoI pooled deep features throughout the tubelet using a new temporal pooling operator that summarizes the information with a fixed output size independent of the tubelet length. In addition, we define a double head implementation that we feed with spatiotemporal information for spatiotemporal classification and with spatial information for object localization and spatial classification. Finally, a long-term linking method builds long tubes with the previously calculated short tubelets to overcome detection errors. The association strategy addresses the generally low overlap between instances of small objects in consecutive frames by reducing the influence of the overlap in the final linking score. We evaluated our model in three different datasets with small objects, outperforming previous state-of-the-art spatiotemporal object detectors and our spatial baseline.

Object detection accuracy on small objects, i.e., objects under 32 × 32 pixels, lags behind that of large ones. To address this issue, innovative architectures have been designed and new datasets have been released. Still, the number of small objects in many datasets does not suffice for training. The advent of the generative adversarial networks (GANs) opens up a new data augmentation possibility for training architectures without the costly task of annotating huge datasets for small objects. In this paper, we propose a full pipeline for data augmentation for small object detection which combines a GAN-based object generator with techniques of object segmentation, image inpainting, and image blending to achieve high-quality synthetic data. The main component of our pipeline is DS-GAN, a novel GAN-based architecture that generates realistic small objects from larger ones. Experimental results show that our overall data augmentation method improves the performance of state-of-the-art models up to 11.9% [email protected] on UAVDT and by 4.7% [email protected] on iSAID, both for the small objects subset and for a scenario where the number of training instances is limited.

Maintaining the identity of multiple objects in real-time video is a challenging task, as it is not always feasible to run a detector on every frame. Thus, motion estimation systems are often employed, which either do not scale well with the number of targets or produce features with limited semantic information. To solve the aforementioned problems and allow the tracking of dozens of arbitrary objects in real-time, we propose SiamMOTION. SiamMOTION includes a novel proposal engine that produces quality features through an attention mechanism and a region-of-interest extractor fed by an inertia module and powered by a feature pyramid network. Finally, the extracted tensors enter a comparison head that efficiently matches pairs of exemplars and search areas, generating quality predictions via a pairwise depthwise region proposal network and a multi-object penalization module. SiamMOTION has been validated on five public benchmarks, achieving leading performance against current state-of-the-art trackers. Code available at: https://www.github.com/lorenzovaquero/SiamMOTION

Depth estimation and all-in-focus image restoration from defocused RGB images are related problems, although most of the existing methods address them separately. The few approaches that solve both problems use a pipeline processing to derive a depth or defocus map as an intermediary product that serves as a support for image deblurring, which remains the primary goal. In this paper, we propose a new Deep Neural Network (DNN) architecture that performs in parallel the tasks of depth estimation and image deblurring, by attaching them the same importance. Our Two-headed Depth Estimation and Deblurring Network (2HDED:NET) is an encoder-decoder network for Depth from Defocus (DFD) that is extended with a deblurring branch, sharing the same encoder. The network is tested on NYU-Depth V2 dataset and compared with several state-of-the-art methods for depth estimation and image deblurring.

Many computer vision applications require real-time processing speeds, which prevents them from running an object detector on all frames of the sequence. In such circumstances, it is necessary to resort to motion estimation techniques in order to maintain the identity of the targets. This can be carried out by instantiating multiple single object trackers, if there are few targets, or through methods that globally extract the frame features, in order to share computations. The problem with the latter is that they yield features with limited semantic information and detect changes in the scene by performing multi-scale tests, which is inefficient and prone to errors. To solve these problems and provide accurate tracking for multiple objects in real-time, we propose SiamFAST. SiamFAST includes: a feature-pyramid-based region-of-interest extractor that produces quality features for both object exemplars and search areas; a pairwise depthwise region proposal network to compute fast similarities for several dozens of objects; and a multi-object penalization module in order to suppress the effect of distractors. SiamFAST has been validated on three public benchmarks, achieving leading performance against current state-of-the-art trackers.

This paper addresses a mixed-mode CMOS circuit for Hyperdimensional Computing (HDC). HDC is based on the use of binary vectors with thousands dimensions to represent data in a holistic way. During the last years HDC has shown to be a powerful approach to solve classification problems. The proposed circuit architecture in this paper is made up of an array of 128 × 64 (8192) processing units (PUs) with a 1-bit ALU, local memory and connectivity to their 4 nearest neighbors to run the basic operations of HDC, i.e, binding, bundling and permutation. The architecture also includes a module to calculate Hamming distance to address classification. Post-layout simulations of the complete system working on various basic operations in 0.18 μ m CMOS technology are shown.

Neural network mixed-mode hardware accelerators for deep convolutional neural networks (CNN) strive to cope with a high number of input feature maps and increasing bit depths for both weights and inputs. As an example of this need, the ResNet model for image classification comprises 512 3× 3 feature filters in its conv5 layer. This would lead to 4068 multipliers driving a summing node for actual concurrent processing of all the input feature maps, which makes up a challenge in mixed-mode. This paper addresses the design of a 5-bit signed SRAM-based in-memory computing cell in 180 nm 3.3 V CMOS technology, dealing with the impact of increasing the number of input feature maps. The data presented in the paper are based on electrical and post layout simulations.

Indirect time of flight (IToF) allows for accurately retrieving 3D geometry without the need for exorbitant time resolution. Nevertheless, the use of continuous-wave (CW) periodic modulation brings the need for multiple frequency measurements to solve depth ambiguities or cope with multi-path interference. Sequential acquisition of multiple frames reduces the frame rate, while harmonic distortion of the modulation waveforms produces wiggling in the depth estimation. This paper presents and verifies the operation of an IToF CMOS image sensor designed to provide single-shot multi-frequency measurements. A macro-pixel structure allows acquiring multi-frame data in one shot, while resonant demodulation annihilates the harmonic content. The novel architecture consists of 10 $\mu m \times 10 \mu m$ 2 -tap pixels with a 20% fill factor (FF). Post-layout simulations show promising 3D reconstruction for up to 16 different simultaneous frequencies.

Most video analytics applications rely on object detectors to localize objects in frames. However, when real-time is a requirement, running the detector at all the frames is usually not possible. This is somewhat circumvented by instantiating visual object trackers between detector calls, but this does not scale with the number of objects. To tackle this problem, we present SiamMT, a new deep learning multiple visual object tracking solution that applies single-object tracking principles to multiple arbitrary objects in real-time. To achieve this, SiamMT reuses feature computations, implements a novel crop-and-resize operator, and defines a new and efficient pairwise similarity operator. SiamMT naturally scales up to several dozens of targets, reaching 25 fps with 122 simultaneous objects for VGA videos, or up to 100 simultaneous objects in HD720 video. SiamMT has been validated on five large real-time benchmarks, achieving leading performance against current state-of-the-art trackers.

Real-time visual object tracking provides every object of interest with a unique identity and a trajectory across video frames. This is a fundamental task of many video analytics applications, such as traffic monitoring or video surveillance in general. The development of real-time multiple object tracking systems on low-power edge devices as IoT nodes, without compromising accuracy, is a challenge due to the limited computing capacity of said devices. This might rule out the best in-class computer vision solutions, which, nowadays, are based on deep learning, and thus, they are very hardware demanding. This article meets this challenge with a multiple object detection and tracking system that employs cutting-edge deep learning architectures on an embedded GPU while operating in real time. For this purpose, a system has been designed that extends a joint architecture of tracking and detection by adding a module comprised of appearance-based and movement-based trackers that allow to maintain the identity of the objects of interest for longer periods of time while alleviating the burden of the detector. Our system is mapped onto an embedded GPU platform, cutting down power consumption significantly with respect to a server GPU. Tracking performance metrics show a 51.1% in multiple object tracking accuracy (MOTA) on the MOT16 data set. This, in conjunction with a real-time processing speed of 25.2 FPS for up to 45 simultaneous objects and low-power consumption of 15 W, make our system an ideal solution for a wide range of video analytics applications.

We present a new network architecture able to take advantage of spatio-temporal information available in videos to boost object detection precision. First, box features are associated and aggregated by linking proposals that come from the same anchor box in the nearby frames. Then, we design a new attention module that aggregates short-term enhanced box features to exploit long-term spatio-temporal information. This module takes advantage of geometrical features in the long-term for the first time in the video object detection domain. Finally, a spatio-temporal double head is fed with both spatial information from the reference frame and the aggregated information that takes into account the short- and long-term temporal context. We have tested our proposal in five video object detection datasets with very different characteristics, in order to prove its robustness in a wide number of scenarios. Non-parametric statistical tests show that our approach outperforms the state-of-the-art. Our code is available at https://github.com/daniel-cores/SLTnet.

Object detection through convolutional neural networks is reaching unprecedented levels of precision. However, a detailed analysis of the results shows that the accuracy in the detection of small objects is still far from being satisfactory. A recent trend that will likely improve the overall object detection success is to use the spatial information operating alongside temporal video information. This paper introduces STDnet-ST, an end-to-end spatio-temporal convolutional neural network for small object detection in video. We define small as those objects under 16×16 px, where the features become less distinctive. STDnet-ST is an architecture that detects small objects over time and correlates pairs of the top-ranked regions with the highest likelihood of containing those small objects. This permits to link the small objects across the time as tubelets. Furthermore, we propose a procedure to dismiss unprofitable object links in order to provide high quality tubelets, increasing the accuracy. STDnet-ST is evaluated on the publicly accessible USC-GRAD-STDdb, UAVDT and VisDrone2019-VID video datasets, where it achieves state-of-the-art results for small objects.

The detection of small objects is of particular interest in many real applications. In this paper, we propose STDnet-ST, a novel approach to small object detection in video using spatial information operating alongside temporal video information. STDnet-ST is an end-to-end spatio-temporal convolutional neural network that detects small objects over time and correlates pairs of the top-ranked regions with the highest likelihood of containing small objects. This architecture links the small objects across the time as tubelets, being able to dismiss unprofitable object links in order to provide high-quality tubelets. STDnet-ST achieves state-of-the-art results for small objects on the publicly available USC-GRAD-STDdb and UAVDT video datasets.

Visual object tracking is of great interest in many applications, as it preserves the identity of an object throughout a video. However, while real applications demand systems capable of real-time-tracking multiple objects, multi-object tracking solutions usually follow the tracking-by-detection paradigm, thus they depend on running a costly detector in each frame, and they do not allow the tracking of arbitrary objects, i.e., they require training for specific classes. In response to this need, this work presents the architecture of SiamMT, a system capable of efficiently applying individual visual tracking techniques to multiple objects in real-time. This makes it the first deep-learning-based arbitrary multi-object tracker. To achieve this, we propose global frame features extraction by using a fully-convolutional neural network, followed by the cropping and resizing of the different object search areas. The final similarity operation between these search areas and the target exemplars is carried out with an optimized pairwise cross-correlation. These novelties allow the system to track multiple targets in a scalable manner, achieving 25 fps with 60 simultaneous objects for VGA videos and 40 objects for HD720 videos, all with a tracking quality similar to SiamFC.

Background subtraction is one of the first steps in many video processing algorithms. Thus, a real-time processing with low power consumption is convenient for different applications where power hungry devices with high computational capabilities can not be deployed. This work presents the design of a 24×56 pixel proof-of-concept 0.18 μm standard CMOS vision sensor chip implementing the foreground detection algorithm Hardware Oriented Pixel Based Adaptive Segmenter (HO-PBAS) on the focal plane. Simulation results show a maximum processing speed of 2000 fps with a figure of merit of 1.3 μW/pixel at 60 fps and a pixel pitch of 47 μm in a four pixels per processing element configuration.

An ultra-low power LDO regulator with an adaptive biasing error amplifier is presented in this paper. An absolute difference voltage meter circuit section based on super source followers is used to achieve the adaptive biasing scheme. The experimental total quiescent current consumption is as low as 1.88 nA with a measured line sensitivity of 0.13 mV/V in a circuit occupying 1473 μm2of silicon area.

Multiple object visual tracking of real time detected objects using a low-power embedded solution is shown. The proposal is implemented on a NVIDIA Jetson TX2 development kit demonstrating the feasibility of deep learning techniques for IoT and mobile edge computing applications.

This paper presents a 1 mm2solar cell and a Power Management Unit (PMU) on the same substrate to rise up the harvested voltage above 1.1 V to power wearable or implantable devices. The on-chip solar cell and the PMU are fabricated in standard 0.18 μm CMOS technology achieving a form factor of 1.575 mm2. Experimental results show that the PMU is able to start-up from a harvested power of 2.38 nW without any external kick off or control signal and can handle a harvested power up to μW with a continuous and two-dimensional Maximum Power Point Tracking (MPPT) that works in open-loop mode to set the frequency, the gain and the capacitor sizes of a charge pump.

This paper presents an indirect Time-of-Flight sensor for standard CMOS technologies with an alternative demodulation scheme based on homodyne techniques. This avoids control signals shorter than the period of the emitted light signal, which prevents synchronization issues and minimizes switching effects like charge injection and clock feedthrough. The feasibility of the pixel and the demodulation scheme is demonstrated through simulations.

Compute and memory demands of state-of-the-art deep learning methods are still a shortcoming that must be addressed to make them useful at Internet of Things (IoT) end-nodes. In particular, recent results depict a hopeful prospect for image processing using convolutional neural networks, CNNs, but the gap between software and hardware implementations is already considerable for IoT and mobile edge computing applications due to their high power consumption. This proposal performs low-power and real time deep learning-based multiple object visual tracking implemented on an NVIDIA Jetson TX2 development kit. It includes a camera and wireless connection capability and it is battery powered for mobile and outdoor applications. A collection of representative sequences captured with the on-board camera, dETRUSC video dataset, is used to exemplify the performance of the proposed algorithm and to facilitate benchmarking. The results in terms of power consumption and frame rate demonstrate the feasibility of deep learning algorithms on embedded platforms although more effort in the joint algorithm and hardware design of CNNs is needed.

This live demonstration is related to ISCAS track “4.5: Circuits & Systems for Energy Harvesting”. This live demo shows a micro-energy harvesting system which includes a 1 mm2solar cell as the unique power source and a Power Management Unit (PMU) on the same substrate in standard 0.18 μm CMOS technology. The PMU has cold start-up from nW and it also performs a continuous and two-dimensional maximum power point tracking using analog strategies to meet very low power consumption, managing a high input power range. The system is used to power an off-chip NAND gate.

Foreground segmentation algorithms are sometimes provided with feedback mechanisms to deal with complex scenarios such as dynamic backgrounds. This is accomplished with background dynamic estimators in the case of foreground detectors based on non-parametric models with a historical record of the background. This work introduces the Shannon entropy as a new background dynamics estimator. The paper shows that this approach leads to better figures of merit than those provided by the original background dynamics estimators in state-of-the-art algorithms such as PBAS and SuBSENSE for complex scenarios as dynamic backgrounds or camera jitter in the database ChangeDetection. Also, the Shannon entropy permits to decrease the number of samples in the background model, cutting memory usage, and thus making implementations on embedded devices easier.

The high number of memory accesses in background subtraction algorithms constraints the choice of the memory topology of an analog implementation of a hardware-oriented version of the well-known PBAS algorithm (HO-PBAS). As the first step towards the implementation of a CMOS vision chip with per-pixel processing to run the HO-PBAS, this work assesses the impact of the circuit non-idealities of the three main analog memory topologies into the segmentation result on the CDNET database.

This paper presents a dynamic model for on-chip inverting capacitive charge pumps driven by two non-overlapping clock signals. The model implements the charge reusing technique to mitigate the efficiency loss due to the charge and discharge process of the parasitic capacitances. Validation with both circuit-level simulations and experimental results is shown, demonstrating high accuracy. An application example in micro energy harvesting is given.

This live demonstration is related to ISCAS track “Sensory Systems: Sensor Networks”. This live demo shows a wireless sensor network of custom-made differential capacitive sensors with the ZigBee protocol for snail pest detection. The wireless sensor network provides the snail occupation level of a given plantation area. Validation of the wireless sensor network in both controlled mini plots in a greenhouse and outdoor small areas has been made.

This paper introduces a Time-of-Flight sensor of 50 × 60 pixels in standard CMOS 0.18 μm technology with in-pixel adaptive number of accumulations and background suppression. Background suppression is carried out through two mechanisms, namely, the increase of signal to background ratio, and background subtraction. The pixel features a fill factor of 77% with an nwell over p-substrate diode of 50 × 50 μm2. The pixel senses the photocurrent through a transimpedance amplifier. Adaptive accumulations are performed with an in-pixel comparator that is also used for per-column A/D conversion as part of an 8-bit single-slope ADC. The sensor works with 4 square pulses of 50 ns. Simulations show that the chip could measure distances up to 7.5 m without optical filters for background levels up to 20 klux at video frame rate.

Computer vision applications have a large disparity in operations, data representation and memory access patterns from the early vision stages to the final classification and recognition stages. A hardware system for computer vision has to provide high flexibility without compromising performance, exploiting massively spatial-parallel operations but also keeping a high throughput on data-dependent and complex program flows. Furthermore, the architecture must be modular, scalable and easy to adapt to the needs of different applications. Keeping this in mind, a hybrid SIMD/MIMD architecture for embedded computer vision is proposed. It consists of a coprocessor designed to provide fast and flexible computation of demanding image processing tasks of vision applications. A 32-bit 128-unit device was prototyped on a Virtex-6 FPGA which delivers a peak performance of 19.6 GOP/s and 7.2 W of power dissipation.

This paper studies the dark current (DC) of the photodiode (PD), the transmission gate (TG), and the floating diffusion (FD) in 4-Transistor (4T) pixels in standard CMOS technologies for Time-of-Flight (ToF) sensors through device simulations. The paper addresses the layout optimization in terms of DC for an nwell/psub and two custom pinned-photodiodes (PPD), stating their pros and cons.

This live demonstration is related to ISCAS track “Imagers and Vision Processing”. It showcases the Gaussian pyramid with a CMOS vision sensor with a 176 × 120 pixel array in standard 0.18 μm CMOS technology. The sensing elements are 3T-APS with in-pixel ADC and CDS. The Gaussian pyramid is extracted concurrently with a double-Euler switched-capacitor network on the same substrate, giving RMSE errors below 1.2% of FSO. The chip provides a Gaussian pyramid of 3 octaves with 6 scales each with an energy cost of 26.5 nJ/px at 2.64 Mpx/s.

This paper proposes a hardware implementation to speed up the calculation of the feature descriptor vector in the Scale-Invariant Feature Transform (SIFT) algorithm. The proposed architecture, which improves conventional solutions based on embedded processors or other hardware/software co-designs, computes a feature descriptor vector of 27 elements from a keypoint neighborhood of 15×15 pixels. This process comprises several steps, including complex operations such as vector normalization operations. The paper compares two different implementations: one being time-optimized and the other memory-optimized. Both approaches require 649 and 874 clock cycles respectively for a single feature vector calculation (6.49 μs and 8.74 μs for a 100 MHz FPGA).

Image and video processing algorithms are becoming more and more sophisticated. An efficient hardware architecture is a requirement in order to address effectively the increasing computational workload. In a context of high performance, low cost and rapid prototyping, a hybrid SIMD/MIMD architecture for image processing is proposed in this work. By reusing functional units and including a dynamically reconfigurable datapath, this architecture enables high performance devices for general image processing tasks with high application development productivity when using as part of a System-on-Chip. A 32-bit 128-unit coprocessor was prototyped on a Virtex-6 FPGA and results show a peak performance of 19.6 GOP/s.

This paper assesses the implementation of scale-and rotation-invariant feature detectors on Cellular Processor Arrays (CPA). Scale- and rotation-invariant feature detectors are complex image processing algorithms with a high computational burden in the low-level image processing stage due to large-neighborhood convolution-type operations. Such operations are used to generate the so-called scale-space. This paper outlines different options to provide the scale space in the Scale Invariant Feature Transform (SIFT) and the Speeded-Up Robust Features (SURF) algorithms on CPAs with pixel-per-processor assignment. The paper shows that it is feasible to do this even with a reduced set of inter-processor communications within acceptable time limits on existing CPAs.

This paper introduces an architecture of a switched-capacitor network for Gaussian pyramid generation. Gaussian pyramids are used in modern scale- and rotation-invariant feature detectors or in visual attention. Our switched-capacitor architecture is conceived within the framework of a CMOS-3D-based vision system. As such, it is also used during the acquisition phase to perform analog storage and Correlated Double Sampling (CDS). The paper addresses mismatch, and switching errors like feedthrough and charge injection. The paper also gives an estimate of the area occupied by each pixel on the 130nm CMOS-3D technology by Tezzaron. The validity of our proposal is assessed through object detection in a scale- and rotation-invariant feature detector.

This work introduces an FPGA implementation for vesseltree extraction on retinal images. The retinal vessel-tree can be used in disease diagnoses, e.g. diabetes, or in person authentication. In such cases, a portable device with a high performance may be a need. The FPGA implementation discussed here, although application-oriented, features a fully programmable SIMD architecture, allowing for an efficient realization of low-level image processing algorithms. It is mapped onto a Spartan 3, amounting to 90 processing elements. The on-chip memory utilized was 1.4MB and stores 8 gray images of 144 × 160px. The working frequency is 53MHz, allowing for a 3 × 3 convolution in less than 110μs.

The use of a reduced set of multipliers or coefficient circuits on cellular processor arrays leads to time and area efficient solutions. The reduced set of multipliers is achievable with the so-called split&shift (S&S) methodology. Data resultant from applying such a methodology to implementations with cellular non-linear networks (CNN) reported in the literature are presented. Also, pixel-level snakes (PLS) are used as benchmark for a more in-depth analysis of our methodology.

Electronic speckle pattern interferometry (ESPI) is a well-known technique in the realm of optoelectronics by which a fringe pattern is formed when two coherent light beams (typically lasers) interfere after, at least one of them, is reflected off a rough surface. The resultant image is acquired by electronic means, with either a CCD camera or CMOS imagers. Observation of the fringe pattern gives information about a measurement. Examples of such measurements are displacement of an object, surface deformation, vibration, velocity, etc. Image analysis is required to read and interpret the underlying information conveyed in the fringe pattern. This paper merges ESPI with cellular non-linear networks (CNN). The final goal is to run ESPI image processing on CMOS CNN-based chips to cover applications with hard time requirements. The current work addresses the first stage which is noise removal through spin filters with CNN operators.

In this paper we analyze the reliability of computation of binary-programmable cellular nonlinear networks for processing binary data. We describe the probability of a cell producing an error with given inputs and the error probability when processing random data. Furthermore, we show how the error probability could be defined in case the cell needs to work correctly with all possible input combinations. This error probability is found by performing Monte Carlo simulations

An alternative to classical image segmentation based on active contour techniques is discussed. The approach is based on deformable contours which evolve until reaching a final desired location. The contour shift is guided by external information from the image under consideration which attracts them towards the target characteristics (intensity, extremes, edges,...) and by internal forces which try to maintain the smoothness of the contour curve. These forces act on each pixel of the contours, resulting in a high degree of freedom for the contour evolution and provide a high flexibility for the evolution dynamics of the snakes which allows the solution of complex tasks as is the case for topologic transformations. This, along with the use of only local information will allow the algorithm implementation into an array of processors leading towards "pixel-level" contour processing.