We propose a novel image acquisition scheme HCAS (Hardware based Compressed Acquisition Scheme) using hardware-based binning (downsampling), bit truncation and JPEG compression and develop a deep learning based reconstruction network DRCAS (Deep Restoration network for hardware based Compressed Acquisition Scheme) for images acquired using HCAS. DRCAS to our best knowledge is the first work proposed in the literature for the restoration of images acquired using acquisition scheme like HCAS. It is also superior in performance than state-of-the-art super resolution networks while being much smaller. We show that HCAS and DRCAS techniques will enable us to design much simpler and power efficient image acquisition pipelines.

Networks-on-chips (NoCs) are gaining in popularity as replacement for shared medium interconnects in chip-multiprocessors (CMPs) and multiprocessor systems-on-chips, and their performance becoming essential to system performance. There have been emerging studies to achieve better power/energy efficiency without performance degradation on NoCs. However, there are still non-negligible latency issues caused by the mechanism of power efficient approaches. To alleviate the latency problem and to transfer data efficiently with the high utilization of interconnect resources, we propose an on-chip network architecture that improves latency and bandwidth. Increasing the data/link widths across the network may considerably resolve this problem but is a costly proposition both in terms of device area and of power. Alternatively, we propose a dual-path router architecture that efficiently exploits path diversity to attain low latency without significant hardware overhead. By: 1) doubling the number of injection and ejection ports; 2) splitting packets into two halves; 3) recomposing routing policy to support path diversity; and 4) provisioning the network hardware design, we can considerably enhance network resource utilization to achieve much higher performance in latency. The proposed simultaneous dual-path routing (SDPR) scheme outperformed the conventional dimension order routing (DOR) technique across synthetic workloads by 31%-40% in average latency and up to a 100% improvement in throughput performance running on a 49-core CMP. Our synthesizable model for the SDPR router and network provides accurate power and area reports. According to the synthesis reports, SDPR incurs insignificant overhead compared to the baseline XY DOR router.

This paper presents a hardware architecture of fast simplified successive cancellation (fast-SSC) algorithm for polar codes, which significantly reduces the decoding latency and dramatically increases the throughput. Algorithmically, fast-SSC algorithm suffers from the fact that its decoder scheduling and the consequent architecture depends on the code rate; this is a challenge for rate-compatible system. However, by exploiting the homogeneousness between the decoding processes of fast constituent polar codes and regular polar codes, the presented design is compatible with any rate. The scheduling plan and the intendedly designed processing core are also described. Results show that, compared with the state-of-art decoder, our design can achieve at least 60% latency reduction for the codes with length N = 1024. By using Nangate FreePDK 45nm process, proposed design can reach throughput up to 5.81 Gbps and 2.01 Gbps for (1024,870) and (1024, 512) polar code, respectively.

This paper presents an efficient hardware design approach for list successive cancellation (LSC) decoding of polar codes. By applying path-overlapping scheme, for LSC with list size l (l > 1), the l instances of successive cancellation (SC) decoder can be cut down to only one. This results in a dramatic reduction of the hardware complexity without any decoding performance loss. We also develop novel approaches to reduce the latency associated with the pipeline scheme. Simulation results show that with proposed design approach the hardware efficiency is increased significantly over the recently proposed LSC decoders.

This paper presents a novel belief propagation (BP) based decoding algorithm for polar codes. The proposed algorithm facilitates belief propagation by utilizing the specific constituent codes that exist in the factor graph, which results in an express journey (XJ) for belief information to propagate in each decoding iteration. In addition, this XJ-BP decoder employs a novel round-trip message passing scheduling method for the increased efficiency. The proposed method simplifies min-sum (MS) BP decoder by 40.6%. Along with the round-trip scheduling, the XJ-BP algorithm reduces the computational complexity of MS BP decoding by 90.4%; this enables an energy-efficient hardware implementation of BP decoding in practice.

This paper presents a very-large-scale integration (VLSI) design to reconstruct compressively sensed data. The proposed digital design recovers signal compressed by specific analog-to-digital converter (ADC). Our design is based on a modified iterative hard threshold (IHT) reconstruction algorithm to adapt unknown and varying degree of sparsity of the signal. The algorithm is composed empirically and implemented in a hardware-friendly fashion. The reconstruction fidelity using fixed-point hardware model is analyzed. The design is synthesized using Synopsys Design Compiler with TSMC 45nm standard cell library. The post-synthesis implementation consumes 165 mW and is able to reconstruct data with information sparsity of 4%, at equivalent sampling rate of 1 gigasample-per-second (GSPS).

WaveSync is a network-on-chip architecture for a globally asynchronous locally-synchronous (GALS) design. The WaveSync design facilitates low-latency communication leveraging the source-synchronous clock sent along with the data to time components in the datapath of a downstream router, reducing the number of synchronizations needed. WaveSync accomplishes this by partitioning the router components at each node into different clock domains, each synchronized with one of the orthogonal incoming source-synchronous clocks in a GALS 2D mesh network. The data and clock subsequently propagate through each node/router synchronously until the destination is reached, regardless of the number of hops this may take. As long as the data travels in the path of clock propagation and no congestion is encountered, it will be propagated without latching as if in a long combinatorial path, with both the clock and the data accruing delay at the same rate. The result is that the need for synchronization between the mesochronous nodes and/or the asynchronous control associated with the typical GALS network is completely eliminated. To further reduce the latency overhead of synchronization, for those occasions when synchronization is still required (when a flit takes a turn or arrives at the destination), we propose a novel less-than-one-cycle synchronizer. The proposed WaveSync network outperforms conventional GALS networks by 87--90% in average latency, synthesized using a 45nm CMOS library.

WaveSync is a low-latency focused, network-on-chip architecture for globally-asynchronous locally-synchronous (GALS) designs. WaveSync facilitates low-latency communication leveraging the source-synchronous clock sent with the data, to time components in the downstream routers data-path to reduce the number of synchronizations needed. WaveSync accomplishes this by partitioning the router components at each node into different clock-domains, each synchronized with one of the the orthogonal incoming source synchronous clocks in a GALS 2D mesh network. The data and clock subsequently propagate through each node/router, synchronously, until the destination is reached, regardless of the number of hops it may take. As long as the data travel in the path of clock propagation, and no congestion is encountered, it will be propagated without latching, as if in a long-combinatorial path, with both the clock and the data accruing delay at the same rate. The result is that the need for synchronization between the mesochronous nodes and/or the asynchronous control associated with typical GALS network is completely eliminated. The proposed WaveSync network outperforms conventional GALS networks by 87-90% in average nanosecond latency with 1.8-6.5 times more throughput across synthetic traffic patterns and SPLASH-2 benchmark suite.

Networks-on-Chips are gaining in popularity as replacement for shared medium interconnects in chip-multiprocessors (CMPs) and multiprocessor systems-on-chips (MPSoCs), and their performance becoming essential to system performance. We propose a dual-path router architecture that efficiently exploits path diversity to attain low latency and high throughput without significant hardware overhead. By 1) doubling the number of injection and ejection ports, 2) splitting packets into two halves, 3) recomposing routing policy to support path diversity, and 4) provisioning the network hardware design, we can significantly improve network resource utilization to achieve much higher throughput and lower latencies. Results show that the proposed dual-path router improves saturation bandwidth by 29% on uniform random synthetic traffic, while achieving a reduction in average packet latency of 31% and 17% for uniform random synthetic traffic and video benchmarks respectively.

This article presents a low-power decoder design for joint source-channel decoding (JSCD) based on a novel unequal error protection (UEP) scheme over additive white gaussian noise (AWGN) channels. Conventional JSCD schemes, adopting low-density parity check (LDPC) codes for multimedia devices, typically operate at a fixed-time decoding loop, regardless of the quality of data received. We present a JSCD scheme that achieves reduction in power through minimum energy decoding and dynamic voltage and frequency scaling (DVFS). Consequently, up to 39% power reduction is achieved in Foreman, Akiyo, and Mobile video streams without performance degradation in reconstructed video quality.

This paper presents a low-power multiple-input multiple-output (MIMO) and H.264 video joint detector/decoder design that minimizes energy for portable, wireless embedded systems. The design combines an unequal error protection (UEP) scheme with a variable fidelity of MIMO detection, making performance and energy consumption tradeoffs as required by the importance of each coded video frame. Using search space reduction/truncation strategies in MIMO detection along with H.264 data partitioning (DP) method, we determine the decoding configurations that yield minimum energy consumption for pre-specified image qualities at the receiver. The synthesis result of this scalable MIMO detector using a 45nm technology library yields 52%, 57%, and 58% energy reductions at 24dB SNR in Foreman, Akiyo, and Mobile test streams respectively. The tradeoff is negligible 0.3dB degradation in peak signal to noise ratio (PSNR) typically used in an image quality estimation.

Network-on-chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communication. As with all current very large scale integration designs, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power consumption is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) clocking scheme. In both DVFS and GALS designs, the chip as a whole is multi-synchronous. As the NoCs interconnecting those nodes must communicate across these clock domain boundaries, they tend to have high latencies as packets must be synchronized at the intermediate nodes. In this paper, we propose a novel router microarchitecture which offers superior performance with respect to typical synchronizing router designs for multi-synchronous networks. Our approach features asynchronous bypass channels which allow flit traversal of intermediate nodes within the network without the latching or synchronization overheads of typical designs. We also propose a new network topology and routing algorithm that leverage the advantages of the bypass channel offered by our router design. We present a detailed analysis of design decisions which affect the performance of the asynchronous bypass channel network. Our experiments show that our design improves the performance of a conventional synchronizing design with similar resources by up to 26% at low loads and increases saturation throughput by up to 50% for a uniform random traffic.

Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI design, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach to reduce power consumption is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) clocking scheme. NoCs implemented with either of these schemes, however, tend to have high latencies as packets must be synchronized at intermediate nodes between source and destination. In this paper, we propose a novel router microarchitecture which offers superior performance versus typical synchronizing router designs. Our approach features Asynchronous Bypass Channels (ABCs) at intermediate nodes thus avoiding synchronization delay. We also propose several new network topology and routing algorithm that leverage the advantages of the bypass channel offered by our router design. Our experiments show that our design improves the performance of a conventional synchronizing design with similar resources by up to 26% at low loads and increases saturation throughput by up to 50%.

Future high speed wireless standards such as 802.11n involve multiple input multiple output (MIMO) antenna systems as a key technology component. Efficient design of the MIMO detector is a challenging task. This is further compounded by the fact that 802.11n standard requires support for runtime switching between different modulation schemes (or modes). While searching for an appropriate architecture attention must be paid to application requirements such as required throughput, limits on latency, and reconfiguration between various modes of operations. Important hardware design metrics such as area/power should be optimized over all the operating modes of the detector. In this paper we carry out extensive architectural space exploration to address the issues of power consumption, area, and reconfigurability between different modes of operation while meeting the standards throughput requirement. Ultimately, we come up with two designs that target low area and low power respectively. We also maintain close to optimum bit error rate(BER), which is vital for any wireless system. The design estimates are based on 45 nm technology library.

MIMO systems (with multiple transmit and receive antennas) are becoming increasingly popular, and many next-generation systems such as WiMAX, 3-GPP LTE and IEEE802.11n wireless LANs relay on the increased throughput of MIMO systems with up to four antennas at receiver and transmitter. High throughput implementation of the detection unit for MIMO systems is a significant challenge especially for higher order modulation schemes. To achieve superior Bit Error Rate (BER) or Frame Error Rate (FER) performance, the detector has to provide soft values to advanced Forward Error Correction (FEC) schemes like Turbo Codes. This paper presents a systolic soft detector architecture for high dimensional (eg. 4times4, 64-QAM) MIMO systems. A Single detector core achieves, throughput of 215 Mbps and power consumption of 23.6 mW, whiles using only 33.1 K gate equivalent (for l2norm). Impressive SNR gains of almost 2 dB are observed with respect to the hard detection counterpart over a block fading channel (at an FER of 1%). Additionally, the architecture can be stacked to give linear increase in throughput with linear increase in hardware resources.

In this paper, we present a novel circuit design approach for radiation hardened digital electronics. Our approach is based on the use of shadow gates, whose task it is to protect the primary gate in case it is struck by a heavy cosmic ion. We locally duplicate the gate to be protected, and connect a pair of diode-connected transistors (or diodes) between the outputs of the original and shadow gates. These transistors turn on when the voltages of the two gates deviate during a radiation strike. Our experiments show that at the level of a single gate, our circuit structure has a delay overhead about 1.76% on average, and an area overhead of 277%. At the circuit level, however, we do not need to protect all gates. We present a methodology to selectively protect specific gates of the circuit in a manner that guarantees radiation tolerance for the entire circuit. With this methodology, we demonstrate that at the circuit level, the average delay overhead is about 3% and the average placed-and-routed area overhead is 28%, compared to an unprotected circuit (for delay mapped designs). We also propose an improved circuit protection algorithm to reduce the area overhead associated with our approach. With this approach for circuit protection, the area and delay overheads are further lowered.

MIMO systems (with multiple transmit and receive antennas) are becoming increasingly popular, and many next-generation systems such as WiMAX, 3-GPP LTE and IEEE802.11 n wireless LANs rely on the increased throughput of MIMO systems with up to four antennas at receiver and transmitter. High throughput implementation of the detection unit for MIMO systems is a significant challenge. This challenge becomes still harder, because the above mentioned standards demand support for multiple modulation and coding schemes. This implies that the MIMO detector must be dynamically reconfigurable. Also, to achieve required bit error rate (BER) or frame error rate (FER) performance, the detector has to provide soft values to advanced forward error correction (FEC) schemes like turbo Codes. This paper presents an ASIC implementation of a novel MIMO detector architecture that is able to reconfigure on the fly and provides soft values as output. The design is implemented in 45 nm predictive technology library, and has a parallelism factor of four. The detector has many qualities of a systolic architecture and achieves a continuous throughput of 1 Gbps for QPSK, 500 Mbps for 16-QAM, and 187.5 Mbps for 64-QAM. The total area is estimated to be approximately 70 KGates equivalent, and power consumption is estimated to be 114 mW.

With shrinking feature size and growing integration density in the deep sub-micrometer (DSM) technologies, the global buses are fast becoming the ldquoweakest-linksrdquo in VLSI design. They have large delays and are error-prone. Especially, in system-on-chip (SoC) designs, where parallel interconnects run over large distances, they pose difficult research and design problems. This paper presents a two-fold approach for evaluating the signal and data carrying capacity of on-chip interconnects. In the first approach, the wire is modeled as a linear time invariant (LTI) system and a frequency response is studied. The second approach addresses delay and reliability in interconnects from an information theoretic perspective. Simulation results for an 8-bit-wide bus in 0.1-mum technology are presented for both approaches. The results closely match to a similar optimal bus clock frequency that will result in the maximumdatatransferrate. Moreover, this optimal frequency is higher than that achieved by present day designs which accommodate the worst case delays. The first approach achieves this higher transmission rate using ideal signal shapes, instead of square pulses, while the second approach uses coding techniques to eliminate high delay cases to generate a higher transmission rate. It is seen that the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication theory, these ldquogoodrdquo signals arriving early can be used to predict/correct the ldquofewrdquo signals that arrive late.

This paper presents a low-power real-time decoder that provides constant-time processing of each frame using dynamic voltage and frequency scaling. The design uses known capacity-approaching low-density parity-check (LDPC) code to contain data over fading channels. Real-time applications require guaranteed data rates. While conventional fixed-number of decoding-iteration schemes are not energy efficient for mobile devices, the proposed heuristic scheme pre-analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The results are then used to dynamically adjust decoder frequency. Energy use is then reduced appropriately by adjusting power supply voltage to minimum necessary for the given frequency. The resulting design provides a judicious trade-off between power consumption and error level

Dirty paper code (DPC) can be used in a number of communication network applications; broadcast channels, multiuser interference channels and ISI channels to name a few. We study various implementation bottlenecks and issues with implementing a DPC pre-coder based on nested trellis technique. The aim is to achieve a practical hardware realization of the precoder for wireless LAN/DSL applications. We describe the architectural development process and realization of the precoder on a Xilinx Virtex 2V8000 FPGA. To the best of our knowledge this is the first reported DPC pre-coder hardware implementation.

We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. The decoder has the following advantages: 55% savings in memory, reduction of routers by 50%, and increase of throughput by 2times when compared to the recent state-of-the-art decoder architectures.

We present a new multi-rate architecture for decoding block LDPC codes in IEEE 802.11n standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. Techniques of data-forwarding and out-of-order processing are used to deal with the irregularity of the codes. The decoder has the following advantages when compared to recent state-of-the-art architectures: 55% savings in memory, reduction of routers by 50% and increase of throughput by 2times.

sunilkhatri at tamu.edu In this paper, we present a novel circuit design approach for radiation hardened digital electronics. Our approach is based on the use of shadow gates, whose task it is to protect the primary gate in case it is struck by a heavy cosmic ion. We locally duplicate the gate to be protected, and connect a pair of transistors (or diodes) between the outputs of the original and shadow gates. These transistors turn on when the voltages of the two gates deviate during a radiation strike. Our experiments show that at the level of a single gate, our circuit structure has a delay overhead of about 4% on average, and an area overhead of over 100%. At the circuit level, however, we do not need to protect all gates. We present a methodology to selectively protect specific gates of the circuit in a manner that guarantees radiation tolerance for the entire circuit. With this methodology, we demonstrate that at the circuit level, the delay overhead is about 4 % and the placed-and-routed area overhead is 30%, compared to an unprotected circuit (for delay mapped designs)

This paper presents a VLSI implementation of a Low-Density Parity Check (LDPC) decoder that achieves 2.4 Gbps throughput yet permits real-time configuration of (1) rate, (2) code length, and (3) the parity equations. This decoder can be programmed in the field, much like an FPGA. We describe the architectural, circuit-level and layout-level details of our implementation. Our design can handle variable rate codes of length up to 1024, and is implemented in a 0.1 μm VLSI fabrication process. Our design has a die size of 12mm by 8mm and a power consumption of 7W. This implementation can extended to handle longer codes in a partially parallel manner, and allow for on-the-fly modification of the code.

With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the "weakest-links" in VLSI design. They have large delays and are error-prone. Especially, in system-on-chip (SoC) designs, where parallel interconnects run over large distances, the effects of crosstalk are detrimental to the overall system performance due to the large delays and un-reliability involved. This paper presents an information theoretic approach to address delay and reliability in long interconnects. A framework to calculate the capacity of a physical wire is laid out herein. The results for 8-bit wide buses of varying lengths in 0.1μm technology are also presented. The wires are modeled based on their calculated parasitic (R, L, C) values and the coupling (C, L) parameters. Using this model, results are obtained for the data transfer capacity of long interconnects. It is seen that for wide buses, the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication-theory, these "good" signals arriving early can be used to predict/correct the "few" signals arriving late. Further, results show that for every bus configuration, there exists an optimal frequency of transmission that will result in the maximum data transfer rate. Also, this optimal frequency is higher than the pessimistic worst case delay based clock design.

Low density parity check (LDPC) codes have received much attention for their excellent performance, and the inherent parallelism involved in decoding them. We consider a type of structured binary LDPC codes, known as array LDPC codes, which have low encoding complexity and good performance, for implementation on a Xilinx field programmable gate array (FPGA) device.

Recent research efforts based on a joint code-decoder design methodology have shown that it is possible to construct structured LDPC (low density parity check) codes without any performance degradation. An interesting new data independence property between the two classes of messages viz. check to bit and bit to check, involved in decoding, is observed. This property is a result of the specific structuring of the parity check matrix. By exploiting this property, we propose an architecture in which the computation of messages is synchronized such that each class of message is consumed immediately by the computational unit for another class of message. The internal memory of the check to bit units is increased in tune with the storage requirement of the check to bit messages. The separate memories for check to bit and bit to check messages are eliminated. This approach has memory savings of 75% and reduces the overall memory accesses by 66%.

A requirement-specific decoder design for forward error-correction in 2 Gbps optical fiber communication system is presented. Low-density parity-check codes are used to achieve high bit error rate performance. Several novel error-decoding architectures are proposed and their design configurations explored to identify optimal cost/performance design. Serial, parallel and scalable architectures are studied. The result is a scaleable architecture that consists of 1.3 million CMOS gates running at 295 MHz and it achieves a throughput of 2.51 Gbps.

An important issue in register-transfer-level (RTL) hardware verification is the ability to check specified functions and to determine the presence of an error. Code-level coverage is often used to measure the success in verification at this level. However existing code-level coverage inaccurately estimates the verification result by considering only the excitations of functional blocks. While it may be impossible to achieve 100% correctness with code-coverage measure, checking excitation of functions and monitoring the effects at output ports can improve reliability of functional verification. This paper presents an RTL functional verification approach that evaluates the excitation-states of conditional expressions and propagates the excited information to output ports. The proposed approach with Verilog PLI-based implementation provide more meaningful coverage value that can measure the extent of functional verification in a very effective way during logic simulation.

A system-level verification framework is presented that combines the speed of hard-wired (FPGA-based) emulation and the observability of gate-level simulation. A checkpoint approach is developed for (1) periodic capturing of the machine state from an emulation, (2) sampling of the emulation output for error detection, and (3) constructing a piece-wise simulation run, necessary to debug the design in an event of an error detection from the emulation. The checkpoint frequency is optimized to reduce the cost of downloading the state data during a hardware emulation. A sampling of the emulation output also minimizes the network-bandwidth and storage-space requirements associated with instrumenting for error detection.

Mixed analog and digital mode simulators have been available for accurate /spl alpha/-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for /spl alpha/-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.

The paper presents a methodology for the simulation of massive number of device-level transient faults. Fault injection locations and the gate around those locations are extracted and evaluated with SPICE. The extracted sub-circuits are exercised exhaustively while fault-injections are performed. Faulty behavior at the outputs of each sub-circuit is recorded in a dictionary, along with the associated input vector, fault-injection time, and location. The recorded logical errors are injected concurrent transient simulator is developed to allow simultaneous evaluation of a massive number of fault-injections, in a single simulation pass. The methodology is illustrated by a case study of MC68000 microprocessor.

FOCUS, a simulation environment for conducting fault-sensitivity analysis of chip-level designs, is described. The environment can be used to evaluate alternative design tactics at an early design stage. A range of user specified faults is automatically injected at runtime, and their propagation to the chip I/O pins is measured through the gate and higher levels. A number of techniques for fault-sensitivity analysis are proposed and implemented in the FOCUS environment. These include transient impact assessment on latch, pin and functional errors, external pin error distribution due to in-chip transients, charge-level sensitivity analysis, and error propagation models to depict the dynamic behavior of latch errors. A case study of the impact of transient faults on microprocessor-based jet-engine controller is used to identify the critical fault propagation paths, the module most sensitive to fault propagation, and the module with the highest potential for causing external errors.>

A simulation environment that allows the run-time injection of transient and permanent faults and the assessment of their impact in complex systems is described. The error data from the simulation are automatically fed into the analysis software in order to quantify the fault-tolerance of the system under test. The features of the environment are illustrated with case study of a fault-tolerant, dual-configuration real-time jet engine controller. The entire controller, described at the logic and functional levels, is simulated, and transient fault injections are performed. In the controller, fault detection and reconfiguration are performed by transactions over the communication links. The simulation consists of the instructions specifically designed to exercise this cross-channel communication. The level of effectiveness of the dual configuration of the system to single and multiple transient errors is measured. The results are used to identify critical design aspects from a fault-tolerance viewpoint.>