Open-source libraries save developers time and effort by providing them access to pre-written functions, objects, and methods. The adoption of such libraries follows the current trend of more widespread use of open-source software and components. However, like proprietary software, open-source software can also suffer from defects that can be exploited by attackers. Many of these vulnerabilities have been identified and documented and are stored in Common Vulnerabilities and Exposures (CVE) databases maintained by entities such as NIST. Developers of these open-source components have a responsibility to inform their users of the vulnerabilities that exist in their releases and of the patches that fix these vulnerabilities. Consistent documentation of CVEs is a prerequisite for mitigating these vulnerabilities, especially if an automated approach is taken. This study investigates how well-documented are the patches both in the CVE database, and within the Github commits of C language open-source libraries. The results show that a significant number of CVEs in the NIST database do not mention the existence of patches and that only a small subset of the libraries looked at document CVEs in their commits. This paper comes to the conclusion that mutually agreed upon standards when it comes to CVE documentation should be adopted by both developers of open-source software and the entities that update and maintain CVE databases.

A locality sensitive hash (LSH) is a function to identify similar items in data sets. However, traditional LSH based algorithms are rarely implemented on hardware due to the high demand of computation, which limits its usage. In this paper, we propose a novel LSH design and hardware implementation called FPGA locality-aware sensitive hash (FLASH). With the unique hardware delay generated during the fabrication process, a FLASH can reduce the dimensionality of coordinate distance calculation and improve the efficiency of nearest neighbor search (NNS). It is also applied to 2-D image clustering. The experimental results show the practical value of our FLASH applications.

FPGA designs are typically optimized for speed and accuracy, with the amount of available hardware considered after the fact. Balancing speed, accuracy, and hardware utilization is a difficult proposition. In this paper, we demonstrate the Hardware Optimization Tool for Memory Table and Logic Conversion (HOTMeTaL) which helps with this tradeoff by modifying part or the majority of an existing FPGA design to use additional logic resources when memory is at a premium, or force the use of memory when logic is highly utilized; without significantly changing the overall functionality of the design. Using established minimization methods, traditionally used for programmable logic devices (PLDs), we also allow the conversion of groups or individual output bits into minimal logic circuits, which then allows the creation of several functionally identical designs, but allowing more control over the resources used in a design. After introducing the basics of the algorithm, we demonstrate the utility of this process with direct comparisons to examples from previous works. It is demonstrated that in some cases, our system will reduce the amount of logic (slices) while simultaneously removing the

A ring oscillator physical unclonable function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Unfortunately, RO PUFs are known to be unstable especially when implemented on an Field Programmable Gate Array (FPGA). In this work, we comprehensively evaluate the RO PUF's stability on FPGAs, and we propose a phase calibration process to improve the stability of RO PUFs. The results show that the bit errors in our PUFs are reduced to less than 1%.

Physical Unclonable Functions are promising candidates for lightweight authentication applications as they are hard to predict and clone. PUFs are dependent on process variations that occurs during silicon chip fabrication. As the CMOS technology scales down towards nanoscale dimensions, there are increasing transistor reliability challenges which impact the lifetime of integrated circuits. These issues are known as aging effects, which result in degradation of the performance of circuits. In this paper, we analyze the effects of aging on the reliability of intrinsic DRAM PUFs. We present accelerated aging experimental results over 18 months (from Sep. 2014 to Feb. 2016) on 3 DRAM PUFs. Based on our observations, DRAM PUFs maintain their reliability over time, and thus, validate the use of DRAM PUFs in a number of applications such as system authentications.

Counterfeit integrated circuits (IC) can be very harmful to the security and reliability of critical applications. Physical unclonable functions (PUFs) have been proposed as a mechanism for uniquely identifying ICs and thus reducing the prevalence of counterfeits. However, maintaining large databases of PUF challenge response pairs (CRPs) and dealing with PUF errors make it difficult to use PUFs reliably. This paper presents an innovative approach to authenticate CRPs on PUF-based ICs. The proposed method can tolerate considerable bit errors from responses of PUFs without the use of error correcting codes. Different types of optimization methods are applied to improve the overall performance. The simulation shows that it is successful in authenticating 99.96% authorized chips and filtering out 99.92% cloned chips by tolerating 12 errors in 128 bits. The results are verified with ring oscillator PUF and arbiter PUF implementations on Kintex-7 FPGA. The approach saves hardware and software resources significantly, compared to those of other authentication solutions.

A physically unclonable function (PUF) is an irreversible probabilistic function that produces a random bit string. It is simple to implement but hard to predict and emulate. PUFs have been widely proposed as security primitives to provide device identification and authentication. In this paper, we propose a novel dynamic-memory-based PUF [dynamic RAM PUF (DRAM PUF)] for the authentication of electronic hardware systems. The DRAM PUF relies on the fact that the capacitor in the DRAM initializes to random values at startup time. Most PUF designs require custom circuits to convert unique analog characteristics into digital bits, but using our method, no extra circuitry is required to achieve a reliable 128-bit PUF. The results show that the proposed DRAM PUF provides a large number of input patterns (challenges) compared with other memory-based PUF circuits such as static RAM PUFs. Our DRAM PUFs provide highly unique PUFs with a 0.4937 average interdie Hamming distance. We also propose an enrollment algorithm to achieve highly reliable results to generate PUF identifications for system-level security. This algorithm has been validated on real DRAMs with an experimental setup to test different operating conditions.

The reverse engineering (RE) of electronic chips and systems can be used with honest and dishonest intentions. To inhibit RE for those with dishonest intentions (e.g., piracy and counterfeiting), it is important that the community is aware of the state-of-the-art capabilities available to attackers today. In this article, we will be presenting a survey of RE and anti-RE techniques on the chip, board, and system levels. We also highlight the current challenges and limitations of anti-RE and the research needed to overcome them. This survey should be of interest to both governmental and industrial bodies whose critical systems and intellectual property (IP) require protection from foreign enemies and counterfeiters who possess advanced RE capabilities.

Physical Unclonable Functions (PUF) are the result of random uncontrollable variables in the manufacturing process. A PUF can be used as a source of random but reliable data for applications such as generating chip identification and encryption keys. Among various types of PUFs, an intrinsic PUF is the result of a preexisting manufacturing process, does not require any additional circuitry, and is cost effective. In this paper, we introduce an intrinsic PUF based on dynamic random access memories (DRAM). DRAM PUFs can be used in low cost identification applications and also have several advantages over other PUFs such as large input patterns. The DRAM PUF relies on the fact that the capacitor in the DRAM initializes to random values at startup. We demonstrate real DRAM PUFs and describe an experimental setup to test different operating conditions on three DRAMs to achieve the highest reliable results. Finally, we select the most stable bits to use as chip ID using our enrollment algorithm.

Counterfeit Integrated Circuits (IC) can be very harmful to the security and reliability of critical applications. Physical Unclonable Functions (PUF) have been proposed as a mechanism for uniquely identifying ICs and thus reducing the prevalence of counterfeits. However, maintaining large databases of PUF challenge response pairs and dealing with PUF errors makes it difficult to use PUFs reliably. This paper presents an innovative approach to authenticate PUF challenge response pairs on IC chips. The proposed method can tolerate considerable bit errors from responses of PUFs without the use of error correcting codes. It is successful in authenticating 99.96% authorized chips and filtering out 99.92% cloned chips. The overhead is reduced by 65.62% compared to that of other authenticating solutions.

The spatial wave-function switched field-effect transistor (SWSFET) has two or three low bandgap quantum well channels that can conduct carrier flow from source to drain of the SWSFET. Because of this property, SWSFETs are useful to implement different multivalued logic with reduced device count. In this paper, we introduce the circuit model of a SWSFET and the design of a unipolar inverter where only one kind of charge carrier contributes to the current flow. We also simulate two input unipolar logic gates such as NAND and NOR and demonstrate their universal property to implement other unipolar logic gates. We also simulate NOR gate and full adder circuits based on unipolar logic gates.

Object-Based Storage Devices (OSDs) offer an object-based data layout instead of using the traditional block-based design. Object storage ideas are increasingly being used in parallel file systems and cloud storage. Previous work has implemented the Parallel Virtual File System (PVFS) on OSDs by moving the metadata and data operations to the OSDs. In this paper, we present two new methods to further improve the performance of the existing PVFS-OSD implementation. These methods are using object collections to represent traditional directories on OSDs and delaying the creation of an OSD object until it is accessed by a write operation. The optimization methods are not particular to PVFS-OSD implementation and could be used with other parallel file systems-object storage implementations too. Experimental evaluations show that using collections yields up to 29 times of improvement in throughput; whereas delaying the creation of OSD objects provides 25% throughput improvement.

In order to sustain scalability, clustered file systems distribute files across multiple I/O nodes in the cluster. The basis of many of these file systems is an object storage architecture where data is represented by variable sized containers called objects. The I/O nodes, however, use a POSIX file and directory interface which do not map well to the object interface. As a result, object storage nodes still have to resolve file paths and perform expensive lookup operations to find inodes and open objects stored as files. In this paper, we propose an alternative object based data interface where I/O node data can be accessed directly using object IDs instead of character strings. We modified an existing Linux file system to provide the object based interface which allows for faster data access times compared to the traditional directory-based interface. In addition, we modified a Object Storage Device (OSD) to use our object based interface to gain improvements in object creation and access. We believe this object based interface provides a useful alternative to the existing interface to provide better performance for cluster storage systems.

In this paper, we discuss logic circuit designs using the circuit model of three-state quantum dot gate field effect transistors (QDGFETs). QDGFETs produce one intermediate state between the two normal stable ON and OFF states due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Interesting logic can be implemented using QDGFETs. In this paper, we discuss the designs of various two-input three-state QDGFET gates, including NAND- and NOR-like operations and their application in different combinational circuits like decoder, multiplier, adder, and so on. Increased number of states in three-state QDGFETs will increase the number of bit-handling capability of this device and will help us to handle more number of bits at a time with less circuit elements.

In this paper, we present the design and implementation of an active storage framework for object storage devices. The framework is based on the use of virtual machines/execution engines to execute function code downloaded from client applications. We investigate the issues involved in supporting multiple execution engines. Allowing user-downloadable code fragments introduces potential safety and security considerations, and we study the effect of these considerations on these engines. In particular, we look at various remote procedure execution mechanisms and the efficiency and safety of these mechanisms. Finally, we present performance results of the active storage framework on a variety of applications.

The flattened butterfly is known to be a cost efficient topology for high-radix networks. Because of its inherent path diversity, it is able to provide comparable cost/performance with the Clos network in adversarial traffic conditions. However, the flattened butterfly is a blocking network and this blocking behavior can degrade the performance of the network when all the I/O devices are transmitting and receiving data with full bandwidth. In this paper, we show that a 2-dilated flattened butterfly shows the nonblocking behavior which is a critical factor in deciding the quality of any high performance computing system network. We demonstrate the procedure to find static decentralized conflict-free routing schedule for this structure. We also compare the performance of a 2-dilated flattened butterfly with other switching networks. We also show that the 2-dilated flattened butterfly topology can be used to build high speed switching systems with reduced cost.

Public resource computing depends on the availability of computing resources that have been contributed by individuals. The amount of resources can be increased by incentivizing resource providers through payment for resources. However, there are costs associated with providing resources for public grid computing. Without an understanding of these costs, it is impossible for a provider to judge if the payment is sufficient to overcome those costs. In this paper, we present a provider cost model that considers all resource provider costs including opportunity costs, future-value costs, penalties, utility costs, and fixed costs. This model helps set a cost structure that a resource provider can use to determine whether it is profitable to participate in a public resource computing market.

The increasing performance and decreasing cost of processors and memory are causing system intelligence to move from the CPU to peripherals such as disk drives. Storage system designers are using this trend toward excessive computation capability to perform more complex processing and optimizations directly inside the storage devices. Such kind of optimizations have been performed only at low levels of the storage protocol. Another factor to consider is the current trends in storage density, mechanics, and electronics, which are eliminating the bottleneck encountered while moving data off the media, and putting pressure on interconnects and host processors to move data more efficiently. Previous work on active storage has taken advantage of the extra processing power on individual disk drives to run application-level code. This idea of moving portions of an applicationpsilas processing to run directly at disk drives can dramatically reduce data traffic and take advantage of the parallel storage already present in large systems today. This paper aims at demonstrating active storage on an iSCSI OSD standards-based object oriented framework.

Peer-to-peer systems provide the opportunity to pool large amounts of distributed resources to enable Internet-scale applications. However, the participant nodes are highly dynamic and unreliable. Thus, any shared resource such as file objects must incorporate redundancy to be useful. While many studies have proposed heuristics to determine redundancy levels based on object popularity, there has been little work in determining optimal or near-optimal resource allocation based on node reliability. In this paper, we present a strategy for the allocation of objects in the presence of dynamic and unreliable peers. We have built an availability model of peer-to-peer storage systems based on the bimodal and time-dependent availability characteristics of a P2P node. Using this model, we can select the size of a candidate node set for storage allocation and assign storage objects to maximize availability while still maintaining a balanced distribution of objects

In this paper, we introduce a novel architecture for constructing caches for lookup operations that are used in a variety of network processing applications. The distinguishing feature of the cache is the ability to match on keys that of arbitrary lengths. We show through an FPGA implementation, that the proposed design can speed up lookup operations significantly compared to a software implementation. In conjunction with a network processor, the use of such a cache can greatly improve the response time of lookup intensive applications such as DNS resolution, directory lookup in network storage, and LDAP queries.

In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). NIDSs are becoming critical components of the network infrastructure as they serve as a key line of defense in network protection. However, current methods are much too compute intensive and cannot begin to meet the bandwidth requirements of a moderate sized corporate network. Thus, hardware techniques are desired to speed up network processing. This paper introduces a FPGA based signature match processor that can serve as the core of a hardware based NIDS. The signature match processor's key feature is a CAM-based cellular processor architecture that can match strings in an area efficient manner. Using a unique binary tree structure, we are also able to generate priority encoded addresses corresponding to multiple signature matches.

In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). Current software-based NIDS are too compute intensive and cannot meet the bandwidth requirements of a modern network. Thus, hardware techniques are desired to speed up network processing. This paper introduces a FPGA based keyword match processor that can serve as the core of a hardware based NIDS. The keyword match processor's key feature is a cellular processor architecture that allows content addressable memory (CAM) to process variable sized keys. These CAMs allow us to perform intrusion detection signature lookup at line speed at rates well past 2 Gbps.

This paper demonstrates a keyword match processor capable of performing fast dictionary search with approximate match capability. Using a content addressable memory with processor element cells, the processor can process arbitrary sized keywords and match input text streams in a single clock cycle. The processor is capable of determining approximate match and providing distance information as well. A 64-word design has been developed using 19000 transistors and it could be expanded to larger sizes easily. Using a modest 0.5 micron process, we are achieving cycle times of 8 ns and the design will scale to smaller feature sizes.

We present a novel framework of a Web-based automated parallel CAD environment. The goal of this project is to make available to the CAD community a growing number of design and test applications that support standard interfaces and execute efficiently in a parallel environment. The design files of a user working on a remote machine are transparently shipped to the local Compute Center, the relevant computation is performed in a parallel environment and then the results are returned back to the user. A job submission and scheduling tool ensures proper load balance and maximal usage of the various parallel machines. The whole process is done efficiently and transparently without the user having to bother about any low-level details. At present, a number of parallel CAD tools including a placement tool, a fault simulator and a VHDL simulator are supported. Results from a preliminary implementation are impressive and show the feasibility of the approach.

Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing based placement has minimized area, but with deep submicron design, minimizing wirelength delay is also needed. The algorithm discussed in this paper is the first parallel algorithm for timing driven placement. We have used a very accurate Elmore delay model which is more complete intensive and hence the need for parallel placement is more apparent. Parallel placement is also needed for very large circuits that may not fit in the memory of a single processor. Therefore, our algorithm is circuit partitioned and can handle arbitrary large circuits on distributed memory multiprocessors. The algorithm, called mpi PLACE, has been tested on several large benchmarks on a variety of parallel architectures.

This paper presents a detailed evaluation of parallel mesaagedriven pmgmms on both message-passing and shared memory pamllel architectures.Four large pomllel appiications from the domain of VLSI computer aided design are evaluated, namely: parallel test pattern genemtion, pamllel cell placement, logic qnthesis, and event dn'ven VHDL kmulalion.The parallelism structure, the communication characterktics, locality chamcterirrtics, gmin sizes of wmputationa, and detailed measurement8 of system time, idle time, and uaer time are meaaunzd for theae applicationa.Resulta are presented for an Intel Pamgon distributed-memory measagepassing multicomputer and compared to a Sun SPARCcenter 1 OOOE symmetric multiprocessor.

Simulated annealing, a methodology for solving combinatorial optimization problems, is a very computationally expensive algorithm and, as such, numerous researchers have undertaken efforts to parallelize it. In this paper, we investigate three of these parallel simulated annealing strategies when applied to standard cell placement, specifically the TimberWolfSC placement tool. We have examined a parallel moves strategy, as well as two new approaches to parallel cell placement-multiple Markov chains and speculative computation. These algorithms have been implemented in ProperPLACE, our parallel cell placement application, as part of the ProperCAD II project. We have constructed ProperPLACE so that it is portable across a wide range of parallel architectures. Our parallel moves algorithm uses novel approaches to dynamic message sizing, message prioritization, and error control. We show that parallel moves and multiple Markov chains are effective approaches to parallel simulated annealing when applied to TimberWolfSC, yet speculative computation is wholly inadequate.

The PARADIGM (PARAllelizing compiler for DIstributed-memory General-purpose Multicomputers) project at the University of Illinois provides a fully automated means to parallelize programs, written in a serial programming model, for execution on distributed-memory multicomputers. To provide efficient execution, PARADIGM automatically performs various optimizations to reduce the overhead and idle time caused by interprocessor communication. Optimizations studied in this paper include message coalescing, message vectorization, message aggregation, and coarse gram pipelining. To separate the optimization algorithms from machine-specific details, parameterized models are used to estimate communication and computation costs for a given machine. The models are also used in coarse gram pipelining to automatically select a task granularity that balances the available parallelism with the costs of communication. To determine the applicability of the optimizations on different machines, we analyzed their performance on an Intel iPSC/860, an Intel iPSC/2, and a Thinking Machines CM-5.

The use of parallel platforms, despite their increasing availability, remains largely restricted to well-structured, numeric applications. We address the issue of facilitating the use of parallel platforms on unstructured problems through object-oriented design techniques and the actor model of concurrent computation. We present a multi-level approach to expressing parallelism for unstructured applications: a high-level interface based on the actor model of concurrent object-oriented programming and a low-level interface which provides an object-oriented interface to system services across a wide range of parallel architectures. The high- and low-level interfaces are implemented as part of the ProperCAD II C++ class library which supports shared memory, message-passing, and and hybrid architectures. We demonstrate our approach through a detailed examination of the parallelization process for an existing unstructured serial application, viz. a state-of-the-art VLSI computer-aided design application. We compare and contrast the library-based actor approach to other method for expressing parallelism in C++ on a number of applications and kernels.>

The authors present an evaluation of some of the disk array organizations proposed in the literature. They evaluate three alternatives for sparing, hot sparing, distributed sparing, and parity sparing, and two options for data layout, regular RAID5 and block designs, and systems based on combinations of these data layout and sparing alternatives. The performance of these organizations is evaluated with different reconstruction strategies. It is shown that parity sparing and distributed sparing have better performance and shorter reconstruction times than hot sparing. It is shown that both block designs as a data layout policy and distributed sparing as a sparing policy reduce the reconstruction time after a failure. The impact of reconstruction strategies is studied, and it is shown that, at higher workloads, choice of reconstruction strategy has a significant impact on the performance of the systems.>

Numerous redundant disk organizations have been proposed and used to provide increased performance and reliability from the I/O subsystems architecture, and once a disk fails in such a system, different forms of spar ing and reconstruction have also been proposed. In this paper, we offer a comprehensive evaluation of the relation ship between various disk array architectures, various disk reconstruction strategies, and their reliability under various failure rate and repair rate distributions. Specifically, we perform the evaluations of the reliabilities (through a mea sure of system mean time to failure) of different redundant disk organizations with variations in each of the following orthogonal directions. We also consider the effect of the reconstruction strategy on the reliability. A third and im portant dimension to our study involves the use of realistic failure rates and repair rates of disks that are dependent on the workload and the organization of the disks. Finally, we perform our study of scalability of the results to varying sys tem sizes, by specifically addressing disk organizations with 16 to 10&4 disks. The paper's contribution is in presenting a uniform framework for evaluation of these multidimen sional studies, as well as offering an improved model for predicting disk array reliability taking into account system load as well as disk organization.