Network-on-Chip (NoC) has emerged as a key architecture component that determines the overall performance, power, and area (PPA) of a contemporary System-on-Chip (SoC) device. The PPA characteristics of NoC are influenced by a wide range of issues, including semi-conductor technology (process node and corner, 2D/3D integration), circuit technology (synchronous, asynchronous), SoC architecture and use-case (number of IP blocks, general purpose or domain specific workload, frequency requirements, voltage, and clock domains), network topology (homogeneous, heterogeneous), routing strategy (deterministic, adaptive), router architecture and features (arity, virtual channels, Quality-of-Service, or QoS), and test architecture. Consequently, research in NoC design covers a wide gamut of topics. This special issue presents the latest advancements in NoC design and optimization.

In this article, we propose a heuristic algorithm for scheduling synchronous data flow (SDF) models on scratch pad memory (SPM) enhanced processors with the objective of minimizing its steady-state execution time. The task involves partitioning the limited on-chip SPM for actor code and data buffer, and executing actors in such a manner that the physical SPM is time shared with different actors and buffers (formally defined as code overlay and data overlay, respectively). In our setup, a traditional minimum buffer schedule could result in very high code overlay overhead and therefore may not be optimal. To reduce the number of direct memory access (DMA) transfers, actors need to be grouped into segments. Prefetching of code and data overlay that overlaps DMA transfers with actor executions also need to be exploited. The efficiency of the our heuristic was evaluated by compiling ten stream applications onto one synergistic processing engine (SPE) of an IBM Cell Broadband Engine. We compare the performance results of our heuristic approach with a minimum buffer scheduling approach and a 3-stage ILP approach, and show that our heuristic is able to generate high quality solutions with fast algorithm run time.

In recent years, we have observed the prevalence of stream applications in many embedded domains. Stream applications distinguish themselves from traditional sequential programming languages through well defined independent actors, explicit data communication, and stable code/data access patterns. In order to achieve high performance and low power, scratch pad memory (SPM) has been introduced in today's embedded multicore processors. Programing on SPM based architecture is both challenging and time consuming. In this paper we address the problem of automatic compilation of stream applications onto SPM based embedded multicore processors through unrolling and retiming. In our technique, code overlay and data overlay are implemented to overcome the limited SPM capacity. Smart double buffering and code prefetching are introduced to amortize memory access delays. We evaluated the efficiency of our technique through compiling several stream applications onto the IBM Cell processor and compared their performance with existing approaches.

Many embedded processor chips aimed at high performance and low power application domains are implemented as multiprocessor System-on-Chip (MPSoC) devices. The multimedia and communication sub-systems of an MPSoC perform some of the most computation intensive and performance critical tasks, and are key determinants of the system-level performance and power consumption. This paper presents an automated technique for synthesizing the system-level memory architecture (both code and data) for the streaming sub-systems of an embedded processor. The experimental results evaluate effectiveness of the proposed technique by synthesizing the system-level memory architecture for benchmark stream processing applications and comparisons against an existing approach.

The prevalence of stream applications in signal processing, multi-media, and network processing domains has resulted in a new trend of programming and architecture design. Several languages and multicore architectures have been developed to support streaming applications. In many of these multicore architectures scratchpad memories (SPM) have substituted caches due to their lower power consumption. Performance optimization on SPM based architectures requires the programmer/compiler to efficiently manage the limited local memory. Our paper addresses the problem of compilation of stream programs onto multicore architectures that incorporate SPMs. We propose a retiming technique that maximizes the throughput under a memory constraint with a user-specified number of software pipeline stages. Trade-offs between double buffering and code overlay are explored intensively in our technique to achieve the best performance. The efficiency of our technique was evaluated by compiling several stream applications for the IBM Cell BE and comparing their results against existing approaches.

Extracting high performance from multi-core processors requires increased use of thermal management techniques. In contrast to offline thermal management techniques, online techniques are capable of sensing changes in the workload distribution and setting the processor controls accordingly. Hence, online solutions are more accurate and are able to extract higher performance than the offline techniques. This paper presents performance optimal online thermal management techniques for multicore processors. The techniques include dynamic voltage and frequency scaling and task-to-core allocation or task migration. The problem formulation includes accurate power and thermal models, as well as leakage dependence on temperature. This paper provides a theoretical basis for deriving the optimal policies and computationally efficient implementations. The effectiveness of our DVFS and task-to-core allocation techniques are demonstrated by numerical simulations. The proposed task-to-core allocation method showed a 20.2% improvement in performance over a power-based thread migration approach. The techniques have been incorporated in a thermal-aware architectural-level simulator called MAGMA that allows for design space exploration, offline, and online dynamic thermal management. The simulator is capable of handling simulations of hundreds of cores within reasonable time.

The paper presents the design of an Automatic Target Recognition (ATR) algorithm on the IBM Cell Broadband Engine (Cell BE). The implementation utilizes several optimizations that exploit both the specific algorithm constructs of the ATR and the architectural features of the Cell processor. We discuss a total of 8 optimizations and present performance improvements achieved by their application. The latency of the Cell BE implementation of the ATR algorithm is 0.070 seconds on the Sony PlayStation3 (PS3) platform. The achieved performance is more than 25 times faster than the fully optimized PowerPC implementation and almost 20 times faster than our best efforts on a Pentium4 CPU.

We seek to maximize the throughput of a periodic application by obtaining an optimized task sequence and dynamic voltage/freque--cy scaling schedules subject to a peak temperature constraint. We first derive an optimal initial temperature that can generate opti-mum solutions. We next present optimal solutions for several sub-problems. Finally, we propose novel algorithms for the general instances of the problem. Experimental results show that our tech-niques out perform existing approaches in both design quality and solution times.

The stream processing characteristics of many embedded system applications in multimedia and networking domains have led to the advent of stream based programming formats. Several multicore processors aimed at embedded domains incorporate scratchpad memories (SPM) due to their superior power consumption characteristics. The paper addresses the problem of compiling stream programs on to multi-core processors that incorporate SPM. Performance optimization on SPM based processors requires effective schemes for software based management of code and/or data overlay. In the context of our problem instance the code overlay scheme impacts both the stream element to core mapping and memory available for inter-processor communication. The paper presents an integer linear programming (ILP) formulation and heuristic approach that effectively exploit the SPM to maximize the throughput of stream programs when mapped to multicore processors. The experimental results demonstrate the effectiveness of the proposed techniques by compiling StreamIt based benchmark applications on the IBM Cell processor and comparing against existing approach.

Many embedded processors incorporate scratchpad memories (SPM) due to their lower power consumption characteristics. SPMs are utilized to host both code and data, often on the same physical unit. Synchronous dataflow (SDF) is a popular format for specifying many embedded system applications particularly in multimedia and network processing domains. Execution of SDF specifications on SPM based processors involves division of memory between actor code and buffers, and scheduling of actor executions and code overlays such that latency is minimized subject to the memory constraints. In our problem instance a traditional minimum buffer SDF schedule could require a larger code overlay overhead and therefore may not be optimal. The paper presents a three stage integer linear programming (ILP) formulation to solve the problem. Further, the paper also introduces modifications to the three stage ILP for incorporating code prefetching optimization to further reduce the code overlay overhead. The effectiveness of the proposed approaches is evaluated by comparisons with minimum buffer SDF schedules for several benchmark applications.

Stream programming models promise dramatic improvements in developers' ability to express parallelism in their applications while enabling extremely efficient implementations on modern many-core processors. Unfortunately, the wide variation in the architectural features of available multi-core processors implies that a single compiler may be incapable of generating general solutions which can run on many target systems, or even on different configurations of the same system. In particular, off-line approaches for finding optimal mappings and schedules for a stream program on a specific processor are limited by their lack of portability across different processors, and by a lack of flexibility for run time variations in resource availability in typical multi-tasking environments. The paper presents a scheme that includes a lightweight compile-time sequencer, and a dynamic scheduler capable of mapping stream programs onto available cores in a multi-core processor at run-time. Unlike previous implementations, our scheme requires limited knowledge of the target architecture's resources at compile time. The off-line portion of the scheme generates canonical scheduling information about the stream program. This information is utilized by the lightweight run-time scheduling algorithm to generate application mappings in linear time based on available resources giving near optimal throughput. Evaluations of schedules generated for twelve streaming benchmarks gives an average of 96% and 93% of the theoretical optimum throughput for schedules with up to 4 and 128 cores, respectively.

It is known that temperature gradients and thermal hotspots affect the reliability of microprocessors. Temperature is also an important constraint when maximizing the performance of processors. Although DVFS and DFS can be used to extract higher performance from temperature and power constrained single core processors, the full potential of multi-core performance cannot be exploited without the use of thread migration or task-to-core allocation schemes. In this paper, we formulate the problem of throughput-optimal task allocation on thermally constrained multi-core processors, and present a novel solution that includes optimal speed throttling. We show that the algorithms are implementable in real time and can be implemented in operating system's dynamic scheduling policy. The method presented here can result in a significant improvement in throughput over existing methods (5X over a naive scheme).

Advances in chip-multiprocessor processing capabilities has led to an increased power consumption and temperature hotspots. Maintaining the on-chip temperature is important from the power reduction and reliability considerations. Achieving highest performance while maintaining the temperature constraint is a challenge. We develop analytical solutions for the optimal control of frequencies for each core in a chip-multiprocessor. The objective is to reduce the makespan or the latest task completion time of all tasks. We show that the optimal frequency policy is bang-bang when the temperature constraint is not active and is exponential when the temperature constraint is active. We show that there is a significant improvement in overall throughput with our proposed solution and yet all cores operate under the thermal maximum.

In this paper a precise formulation of the problem of minimizing the maximum completion time of tasks on a multi-core processor, subject to thermal constraints is presented. The power model used in this work, accounts for the leakage dependence on temperature, while the thermal model is based on the HotSpot model. The general problem is shown to be a non-linear optimization problem that includes cyclic constraints between temperature and power. The derived policy of dynamic frequency and voltage control results in a performance improvement of 19.6% over an optimal policy which performs speed-only control.

The paper addresses the problem of battery lifetime maximization for a job sequence executing on a processor with discrete voltage/frequency states under a deadline constraint. We consider a nonlinear electrochemical discharging model of the battery, and present a pseudo-polynomial time optimal algorithm and a fully polynomial time approximation algorithm as solutions. This is the first work that proposes both optimal and approximation algorithms for battery aware energy management based on voltage/frequency scaling techniques. Our experimental results show that the approximation algorithms widely outperform an existing technique. Further, for a number of realistic and synthetic benchmarks, the qualities of the solutions produced by our approximation techniques are much better than the required quality bounds imposed by the designer.

The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. The technique operates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimentation with benchmark applications and comparisons with existing approaches.

We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency operating states for each core. We prove that the problem is strongly NP-hard. We propose polynomial time 2-approximation algorithms for homogeneous and heterogeneous CMPs. To the best of our knowledge, our techniques offer the tightest bounds for energy constrained design on CMP architectures. Experimental results demonstrate that our techniques are effective and efficient under various workloads on several CMP architectures.

The paper introduces the problem of system-level thermal aware design of applications with uncertain run time on an embedded processor equipped with dynamic voltage/frequency scaling features. The problem takes as inputs a task sequence, cycle time distribution of each task, and processor thermal model. The solution specifies a voltage/frequency assignment to the tasks such that the expected latency is minimized subject to the probability that the peak temperature constraint is not violated is no less than a designer specified value. We prove that the problem is at least NP-hard, and present optimal and (1 + ∈) fully polynomial time approximation scheme as solutions. To the best of our knowledge, this paper is the first work that addresses the stochastic version of the system-level thermal-aware design problem. We evaluate the effectiveness of our techniques by experimenting with realistic and synthetic benchmarks.

This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements of the target device. The optimization objectives include power consumption and resource usage. This paper presents a two-stage synthesis approach consisting of the following: (1) core to router mapping and (2) custom topology and route generation. In particular, it presents an optimal technique for core to router mapping [stage (1)] and a factor-2 approximation algorithm for custom topology generation [stage (2)]. The superior quality of the techniques is established by experimentation with benchmark applications and by comparisons with existing approaches.

The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, and block multi-threading. The paper presents an automated system-level design technique for process mapping on such architectures with an objective of maximizing the worst case throughput of the application. As this mapping must be done in the presence of resource (processors and code size) constraints, this is an NP-complete problem (Ausiello et al., 1999). We present a polynomial time approximation algorithm guaranteed to generate solutions with throughput at least 1/2 that of optimal solutions. The proposed algorithm was utilized to map realistic applications on the Intel IXP2400 (NP) architecture, and produced solutions within 78% of optimal.

Network-on-chip (NoC) architectures with optimized topologies have been shown to be superior to regular architectures (such as mesh) for application specific multiprocessor system-on-chip (MPSoC) devices. The application specific NoC design problem takes as input the system-level floorplan of the computation architecture, characterized library of NoC components, and the communication performance requirements. The objective is to generate an optimized NoC topology, and routes for the communication traces on the architecture such that the performance requirements are satisfied and power consumption is minimized. The paper discusses a two stage automated approach consisting of i) core to router mapping, and ii) topology and route generation for design of custom NoC architectures. In particular it presents an optimal technique for core to router mapping (stage i), and a factor 2 approximation algorithm for custom topology generation (stage ii). The superior quality of the techniques is established by experimentation with benchmark applications, and comparisons with integer linear programming (ILP) formulations, and heuristic techniques.

Network processor architectures incorporate block multi-threading to alleviate the performance degradation due to memory access latencies. Application design on such architectures requires the determination of the number of threads, and mapping of data items to the various memory elements such that the overall throughput is maximized. The paper presents a quasi-polynomial time approximation algorithm for the multi-threading aware data mapping problem which can be shown to be NP complete. The algorithm generates solutions with throughput no less than 1 / 2(1+ε) of optimal and data memory requirements no more than (1 + ε) times the memory constraints. Experimental results obtained by mapping applications on the Intel IXP 2400 network processor demonstrate that the algorithm is able to generate solutions whose throughput is within 80% of the optimal when ε = 0.5.

Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to support the high performance requirements of networking applications. The paper presents an automated system-level design technique for application development on such architectures. The technique incorporates process transformations and block multi-threading aware data mapping to maximize the worst case throughput of the application. We propose integer linear programming formulations for process allocation and data mapping on SMP and block multi-threading based network processors. The paper presents experimental results that evaluate the technique by implementing representative network processing applications on the Intel IXP 2400 architecture. The results demonstrate that our technique is able to generate high-quality mappings of realistic applications on the target architecture within a short time

The paper addresses the problem of performance optimization for a set of periodic tasks with discrete voltage/ frequency states under thermal constraints.We prove that the problem is NP-hard, and present a pseudo-polynomial optimal algorithm and a fully polynomial time approximation technique (FPTAS) for the problem. The FPTAS technique is able to generate solutions in polynomial time that are guaranteed to be within a designer specified quality bound (QB) (say within 1% of the optimal). We evaluate our techniques by experimentation with multimedia and synthetic benchmarks mapped on the 70nm CMOS technology processor. The experimental results demonstrate our techniques are able to match optimal solutions when QB is set at 5%, can generate solutions that are quite close to optimal (≪ 5%) even when QB is set at higher values (50%), and executes in few seconds (with QB ≫ 25%) for large task sets with 120 nodes (while the optimal solution takes several hundred seconds). We also analyze the effect of different thermal parameters, such as the initial temperature, the final temperature and the thermal resistance.

We address power minimization of earliest deadline first and rate monotonic schedules by voltage and frequency scaling. We prove that the problems are NP-hard, and present (1+∈) fully polynomial time approximation techniques that generate solutions which are guaranteed to be within a specified quality bound (QB= ∈) (say within 1% of the optimal). We demonstrate that our techniques can match optimal solutions when QB is set at 1%, out perform existing approaches [1] even when QB is set at 10%, generate solutions that are quite close to optimal (< 5%) even when QB is set at higher values (25%), and execute in a fraction of a second (with QB > 5%) for large 100 node task sets.

Network processors incorporate several architectural features, including symmetric multiprocessing (SMP), block multithreading, and multiple memory elements, to support the high-performance requirements of current day applications. This article presents automated system-level design techniques for application development on such architectures. We propose integer linear programming formulations and heuristic techniques for process allocation and data mapping on SMP and block-multithreading-based network processors. The techniques incorporate process transformations and multithreading-aware data mapping to maximize the throughput of the application. The article presents experimental results that evaluate the techniques by implementing network processing applications on the Intel IXP 2400 architecture.

Network-on-chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale technologies. In future SoC architectures, minimizing power consumption continue to be an important design goal. In this paper, we present a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC. We demonstrate the quality of the solutions produced by our technique by experimentation with many benchmarks. Our technique has a low computational complexity, and consumes only 1.25 times the power consumption, and 0.85 times the number of router resources compared to an optimal MILP based technique whose computational complexity is not bounded

Application-specific system-on-chip (SoC) design offers the opportunity for incorporating custom network-on-chip (NoC) architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents novel mixed integer linear programming (MILP) formulations for synthesis of custom NoC architectures. The optimization objective of the techniques is to minimize the power consumption subject to the performance constraints. We present a two-stage approach for solving the custom NoC synthesis problem. The power consumption of the NoC architecture is determined by both the physical links and routers. The power consumption of a physical link is dependent upon the length of the link, which in turn, is governed by the layout of the SoC. Therefore, in the first stage, we address the floorplanning problem that determines the locations of the various cores and the routers. In the second stage, we utilize the floorplan from the first stage to generate topology of the NoC and the routes for the various traffic traces. We also present a clustering-based heuristic technique for the second stage to reduce the run times of the MILP formulation. We analyze the quality of the results and solution times of the proposed techniques by extensive experimentation with realistic benchmarks and comparisons with regular mesh-based NoC architectures.

We present SAGA, a novel genetic algorithm (GA) based technique for synthesis of custom NoC architectures that support guaranteed throughput traffic. The technique accepts as input a communication trace graph, amount of data, period, and deadline for each trace, interconnection network architecture elements, and generates a custom NoC topology, and routing and schedule of the communication traces on the architecture. SAGA minimizes both the energy consumption and area of the design by solving a multi-objective optimization problem. We present a detailed analysis of the quality of the results and the solution times of the proposed technique by extensive experimentation with realistic benchmarks and comparisons with optimal MILP solutions. SAGA is able to generate solutions that are as good as the optimal solutions produced by the MILP formulation. Whereas the MILP formulation run time rises exponentially for even moderately sized graphs, SAGA generates solutions for large graphs in reasonable time.

Network-on-chip (NoC) has been proposed as a solution to the communication challenges of system-on-chip (SoC) design in nanoscale technologies. Application specific SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. Custom NoC design in nanoscale technologies must address performance requirements, power consumption and physical layout considerations. This paper presents a novel three phase technique that i) generates a performance aware layout of the SoC, ii) maps the cores of the SoC to routers, and iii) generates a unique route for every trace that satisfies the performance and architectural constraints. We present an analysis of the quality of the results of the proposed technique by experimentation with realistic benchmarks.

Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh based topologies requires mapping of cores to router ports, and routing of traffic traces such that the bandwidth and latency constraints are satisfied. We present a novel automated design technique that solves the mesh based NoC design problem with an objective of minimizing the communication energy. In contrast to existing research that only take bandwidth constraints as inputs, our technique solves the NoC design problem in the presence of bandwidth as well as latency constraints. We compare our technique with a recent work called NMAP and an optimal MILP based formulation. We prove that the complexity of our technique is lower than that of NMAP. For the latency constrained case, while NMAP fails on most test cases, our technique is able to generate high quality results. In comparison to the MILP formulation, the results produced by our technique are within 14% of the optimal

Recently, we introduced a novel ARchitecture for Interactive Arts (ARIA) middleware that processes, filters, and fuses sensory inputs and actuates responses in real-time while providing various Quality of Service (QoS) guarantees. The objective of ARIA is to incorporate realtime, sensed, and archived media and audience responses into live performances, on demand. An ARIA media workflow graph describes how the data sensed through media capture devices will be processed and what audio-visual responses will be actuated. Thus, each data object streamed between ARIA processing components is subject to transformations, as described by a media workflow graph. The media capture and processing components, such as media filters and fusion operators, are programmable and adaptable; i.e, the delay, size, frequency, and quality/precision characteristics of individual operators can be controlled via a number of parameters. In [1, 4, 5], we developed static and dynamic optimization algorithms which maximize the quality of the actuated responses, minimize the corresponding delay and the resource usage. In this demonstration, we present the ARIA GUI and the underlying kernel. More specifically, we describe how to design a media processing workflow, with adaptive operators, using the ARIA GUI and how to use the various optimization and adaptation alternatives provided by the ARIA kernel to execute media processing workflows.

Networks-on-chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Innovative system-level performance models are required for designing NoC based architectures. This paper presents a VHDL based cycle accurate register transfer level model for evaluating the latency, throughput, dynamic, and leakage power consumption of NoC based interconnection architectures. We implemented a parameterized register transfer level design of the NoC architecture elements. The design is parameterized on (i) size of packets, (ii) length and width of physical links, (iii) number, and depth of virtual channels, and (iv) switching technique. The paper discusses in detail the architecture and characterization of the various NoC components. The paper presents results obtained by application of the model towards design space exploration, and power versus performance trade-off analysis of 4/spl times/4 mesh based NoC architecture.

Networks-on-a-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Real-time applications require multiple service levels to account for traffic with low delay jitter. As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced effects, that are likely to reduce the reliability of data. This paper addresses two important aspects of NoC architecture, QoS (Quality of Service) and Error Control and makes the following contributions: (i) It presents techniques for supporting guaranteed throughput and best-effort traffic quality levels in NoC router, (ii) It provides models for integrating error control schemes in the NoC router architecture, and (iii) It presents cycle accurate power and performance models of the two architecture enhancements for a 4x4 mesh based NoC architecture.

Network-on-chip (NoC) has been proposed as a solution for the communication challenges of system-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents novel linear programming based techniques for synthesis of custom NoC architectures. In the nanoscale regime, low power consumption would continue to be an important design goal. We first discuss an optimal mixed integer linear programming (MILP) formulation that synthesizes a low power NoC architecture subject to the performance constraints. The MILP formulation is limited by large run times. We next present heuristic techniques that exploit clustering, and 0-1 constraint relaxation to reduce the run times of the formulation. The techniques minimize power as the primary goal, and minimize the number of routers (area) as a secondary goal. We present an analysis of the quality of the results and the solution times of the proposed techniques by extensive experimentation with the realistic benchmarks. The clustering based heuristic generates results whose power consumption is within 11% of the MILP solutions and its average run time is 171.1 seconds. The average run time of the relaxation and rounding based techniques is less than 2 seconds, and the power consumption of their solutions is within 58% of the MILP result.

We are developing an adaptive and programmable media-flow ARchitecture for Interactive Arts (ARIA) to enable real-time control of audio, video, and lighting on an intelligent stage. The intelligent stage is being equipped with a matrix of floor sensors for object localization, microphone arrays for sound localization, beam forming and motion capture system. ARIA system provides an interface for specifying intended mappings of the sensory inputs to audio-visual responses. Based on the specifications, the sensory inputs are streamed, filtered and fused, actuate a controllable projection system, sound surround and lighting system. The actuated responses take place in real-time and satisfy QoS requirements in live performance. In this paper, we present the ARIA quality-adaptive architecture. We model the basic information unit as a data object with a meta-data header and object payload streamed between nodes in the system and use a directed acyclic network to model media stream processing. We define performance metrics for the output precision, resource consumption, and end-to-end delay. The filters and fusion operators are being implemented by quality aware signal processing algorithms. The proper node behavior is chosen at runtime to achieve the QoS requirements and adapt to input object properties. For this purpose, ARIA utilizes a two-phase approach: static pre-optimization and dynamic run-time adaptation.

Transformative applications are computation intensive applications characterized by iterative dataflow behavior. Typical examples are image processing applications like JPEG, MPEG, etc. The performance of embedded hardware-software systems that implement transformative applications can be maximized by obtaining a pipelined design. We present a tool for hardware-software partitioning and pipelined scheduling of transformative applications. The tool uses iterative partitioning and pipelined scheduling to obtain optimal partitions that satisfy the timing and area constraints. The partitioner uses a branch and bound approach with a unique objective function that minimizes the initiation interval of the final design. We present techniques for generation of good initial solution and search-space limitation for the branch and bound algorithm. A candidate partition is evaluated by generating its pipelined schedule. The scheduler uses a novel retiming heuristic that optimizes the initiation interval, number of pipeline stages, and memory requirements of the particular design alternative. We evaluate the performance of the retiming heuristic by comparing it with an existing technique. The effectiveness of the entire tool is demonstrated by a case study of the JPEG image compression algorithm. We also evaluate the run time and design quality of the tool by experimentation with synthetic graphs.