This article presents a 10-bit radiation-hardened-by-design (RHBD) SAR analog-to-digital converter (ADC) operating at 50 MS/s, designed for aerospace applications in high-radiation environments. The system- and circuit-level redundancy techniques are implemented to mitigate radiation-induced errors and metastability. A novel split coarse/fine asynchronous SAR ADC architecture is proposed to provide system-level redundancy. At circuits level, single-event effects (SEEs) error detection and radiation-hardened techniques are implemented. Our co-designed SEE error detection scheme includes last-bit-cycle (LBC) detection following the LSB cycle and metastability detection (MD) via a ramp generator with a threshold trigger. This approach detects and corrects radiation-induced errors using a coarse/fine redundant algorithm. The radiation-hardened latch comparators and D flip-flops (DFFs) are incorporated to further mitigate SEEs. The prototype design is fabricated using TSMC 65-nm technology, with an ADC core area of 0.0875 mm2and a power consumption of 2.79 mW at a 1.2-V power supply. Postirradiation tests confirm functionality up to 100-krad(Si) total ionizing dose (TID) and demonstrate over 90% suppression of large SEE under laser testing.

In this paper, we present a method for hardening memory and sequential cells against soft errors. The effect of the ionizing particle on the bulk potential is exploited to prevent the induced SET from propagating in the circuit. The proposed method requires a minimum number of extra transistors. The solution is applied to D Flip-Flop design, and alpha and heavy-ions test results are presented.

With shrinking process technologies, the likelihood of mid-life faults in combinatorial logic is increasing. Approximate logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating approximate logic functions. The algorithm considers the failure probabilities of the gates and it uses a sum of product (SOP) representation. The results on some circuits show that FIT rate can be reduced by 75% with an area penalty of 46% and inserting only two additional layers of logic.

With shrinking process technologies, the likelihood of mid-life logic faults is increasing. In this paper, we present an approach for mitigating the effects of faults in combinatorial logic through the selective addition of redundant logic. This approach can be applied to a generic digital circuit, protects against multiple fault models and offers a trade-off between area and fault coverage. The results show that fault coverage can be improved by 4x with an area penalty of 50% and only two additional layers of logic.