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FinFET technology has become an attractive candidate for high-performance and power-efficient applications. However, its susceptibility to defects increases due to the complexity of the process fabrications and smaller feature sizes. This article proposes compact and low-cost analytical models to evaluate the delay increase in FinFET-based circuits due to resistive open defects. The models rely on electrical simulations to precharacterize the circuit library. Analytical expressions are developed for the three types of resistive opens that may occur in FinFET-based logic cells using multifin and multifinger structures. These types of resistive opens include: a resistive open at the drain or source of the transistors (RODS), a resistive open affecting the gate of a single transistor, and a resistive open affecting the gates of both nMOS and pMOS transistors. Compact analytical models are also developed to evaluate the delay increase due to the resistive open defects under process variations. Independent and correlated process variations are taken into account. The analytical models have been validated against SPICE electrical simulations. The proposed analytical models can be used to evaluate the detectability of resistive open defects, significantly reducing the cost of dealing with different defect sizes. Potential applications of the developed analytical models are delineated. This work allows us to have higher quality and reliable electronic products.

This article proposes an electrical analysis of a new defect mechanism, to be named as b-open defect, which may occur in nanometer technologies due to the use of the Self-Aligned Double Patterning (SADP) technique. In metal lines making use of the SADP technique, a single dust particle may cause the simultaneous occurrence of a bridge defect and an open defect. When the two defects impact the same gates, the electrical effects of the bridge and the open combine and exhibit a new specific electrical behavior; we call this new defect behavior a b-open. As a consequence, existing test generation methodologies may miss defect detection. The electrical behavior of the b-open defect is first analyzed graphically and then validated through extensive SPICE simulations. The test pattern conditions to detect the b-open defect are finally determined, and it is shown that the b-open defect requires specific test generation.

In this paper, we analyze the electrical behavior of a new type of technological defect appearing in the most recent technological process achieving extremely high interconnection density by using the Self-Aligned Double Patterning technique (SADP). This totally new defect mechanism, which could not appear in conventional CMOS technologies, is structurally dependent of the SADP technique and can be considered as a simultaneous combination of Bridge and Open: we consequently named it B-open. The electrical behavior of the B-Open defect is analyzed and shown that the defect exhibits some classical electrical characteristics of Bridge defect and Open defect but also an unprecedented electrical mixed behavior of both defects.

FinFET technology is an attractive candidate for high-performance and power-efficient application and is currently used for several electronic products. FinFET technology incorporates new technologies in the manufacturing processes that may generate new defect topologies which need to be considered during test generation. This paper analyzes the electrical behavior of full open gate defects, i.e., a transistor gate with infinite resistance. It is shown that classical models, called single open (SO) and interconnect open (IO), that have been proposed in the past for CMOS technology are not sufficient in FinFET technology. The modern FinFET-based logic cells using multifin and multifinger design techniques give rise to new specific defect topologies called “subset full open gate defect.” The static and dynamic electrical behaviors of the two new topologies, subset SO (SOsub) and subset IO (IOsub), are analyzed, and the detectability of the defect in the context of Boolean testing and delay testing is derived. The detectability is analyzed taking into account process variation, temperature, and power supply control.

Spin-Transfer-Torque Magnetic RAM (STT-MRAM) is a promising memory technology due to its ultra-integration density capability; nanosecond read and write operation speeds and CMOS/FinFET fabrication process compatibility. As every silicon technology, STT-MRAMs may be affected by fabrication defects, which may be difficult to detect under process variability in deeply scaled transistor technology. This paper proposes a Design-For-Test (DFT) circuit to detect short defects in the STT-MRAM cells. The proposed methodology is based on the observation that a short defect makes different the amplitude of the current entering and leaving the memory cell. The proposed DFT circuitry is robust to process-induced parameters variations in the memory cell. In such way, defects detection probabilities are increased, and a high-quality product can be guaranteed.

Due to aggressive technology scaling in nanometer regime, the impact of process variations on IC design has become a challenge. Process variations are usually classified into two types: inter-die and intra-die variations. The focus of this paper is on intra-die variations, which were ignored in the past, and are now significantly impacting the performance of modern circuits. A novel statistical gate-sizing metric is proposed to enhance the performance of digital integrated circuits in the presence of local intra-die process variations. The metric selects the most beneficial gates to be resized for improving circuit performance at a lower area cost. The proposed gate-sizing metric provides a means to increase yield leading to better chip revenue.

Conventional clock guardbanding to assure a circuit’s reliable operation under device aging due to NBTI/PBTI and process variations introduce significant performance loss in modern nanometer circuits. Dynamic Frequency Scaling (DFS) is a more efficient technique that allows us to adjust the system clock frequency according to the process condition and aging deterioration of the circuit. At the design phase, the DFS technique requires the identification of the logic paths to be monitored to introduce the required circuitry to monitor their delay. However, critical path identification is a complex problem due to three major challenges: (1) The critical paths of the circuit depend on the stress duty cycle of the devices, which are unknown in advance at design phase; (2) the critical paths of the circuit depend on the process parameters variations, whose impact on delay depend on the spatial correlation due to proximity at the circuit layout; and (3) the critical paths reordering probability may change over time due to aging. This article presents a methodology for efficient selection of the critical paths to be monitored under a DFS framework, addressing the aforementioned challenges. Experimental results onISCAS85/89 benchmark circuits show the feasibility of the proposed approach to select a restricted path set while providing reliable aging monitoring.

FinFET technology has become the most promising alternative to continue CMOS scaling. However, Finfet design makes use of complex interconnect structures (e.g middle-of-line -MOL- interconnections), and multi-fin and multi-finger devices, which pose a challenge to test open defects. In this paper, open defects at gate locations in FinFET based cells are investigated. The parasitic capacitances of the cells are extracted using Raphael 3D Field Solver. The logic and dynamic behavior of the opens defects is analyzed, and possible defective topologies are defined. Some open locations present behaviors similar to those presented in planar CMOS based circuits. However, most of the open locations present new subtle behaviors. The use of multi-fin and multi-finger devices makes the opens more difficult to detect than in planar CMOS technology and non-detectable opens may pose reliability issues. Hence, a good understanding of the defect behavior is needed in order to develop new test strategies for FinFET based logic circuits to have circuits with higher quality.

Aging effects in advanced technologies produce significant performance degradation as time progresses. In order to guarantee safe operation, aging-delay monitors can be inserted at the output nodes of critical paths (CPs) to allow predictive error detection. However, online monitoring of a large number of CPs that can exist in the state-of-art designs is not feasible. The conventional statistical selection of CPs requires knowledge of the coordinates of each gate in the corresponding layout of the circuit to account for spatial correlation between devices' process parameters. This paper presents a nonspatial-correlation-dependent methodology to select the CPs for aging-delay monitoring for predictive error detection. Spatial correlation is bounded by a statistical approach maximizing CPs' coverage. The proposed early selection methodology is validated by comparing the obtained results with those obtained with the availability of spatial correlation information extracted from the circuit layout. The results clearly show that the set of CPs selected with the proposed early selection methodology is in good agreement with the one selected with the availability of layout information. Therefore, our proposed methodology is very attractive to be used in the early design stages, where detailed circuit layout is not available.

Interconnect opens are a major class of defects found in today's nanometer technologies. These defects present subtle behavior that could lead to test escapes and hence compromise test quality. Furthermore, they could become a reliability risk. Low-voltage testing has been suggested as a static test to improve the defect coverage of interconnect opens. In nanometer technologies, process variability is predominant and considering only the nominal value of parameters is not realistic. Hence, process variations should be considered to analyze the behavior of interconnect opens. In this brief, the detection capabilities of low-voltage testing for interconnect opens considering process variations is investigated. A statistical model is used for the interconnect open defect. Correlation between parameters of the affected gates and spatial correlation of the parameters for those gates tied to the defective floating node have been considered. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS85 benchmark circuits. Based on these results, it is suggested to use low VDD in conjunction with favorable logic conditions at the coupling lines to enhance the defect coverage of interconnect opens leading to better test quality and higher product reliability.

Process variations are imposing strong limits to performance of digital circuits at gigascale integration; they are classified in two types: inter-die and intra-die variations. Moreover, intra-die variations, which were ignored in the past, now have become significant. The present work proposes a statistical performance optimization methodology using a gate selection metric to enhance performance of digital integrated circuits in the presence of local intra-die process variations. The gate selection metric allows to select those gates to be re-sized for improving circuit performance at a lower area cost. This selection metric allows to optimize the circuit behavior using Lagrange method. The obtained results on ISCAS benchmark circuits show the benefits of the proposed methodology. The proposed optimization methodology allows to increases yield leading to better revenue.

Bias Temperature Instability (BTI) has become a major aging issue for circuit lifetime reliability in deeply scaled CMOS technologies. Due to BTI, circuit delay increases as time progress, which may lead to a timing constraint violation before the end of the expected lifetime. This paper proposes a new sizing approach to mitigate BTI induced delay degradation of digital circuits. The approach is based on the observation that the delay sensitivity to transistor sizing of a digital gate is composed by a nominal delay sensitivity and a delay degradation sensitivity components. By exploiting the differences between these two components, one can size some gates in the critical paths of a circuit, in such way that the delay degradation due to BTI is reduced while the nominal delay remains nearly unchanged. By using our sizing approach, the reduction of delay degradation allows to further extend the lifetime of a circuit with negligible area and power overhead.

This paper proposes an early resilience methodology to identify circuit output nodes where aging sensors should be inserted for an error prediction framework. The methodology is based in a pre-layout statistical estimation of the signal paths likely to become critical due to NBTI and/or Process Variations. To handle the fact that spatial correlation information is not available at early steps of the design flow, a statistical approach maximizing critical paths coverage is proposed. The results obtained with the early prediction methodology are compared with those obtained with spatial correlation information. The proposed methodology provides a good prediction of the set of critical paths to be monitored. Furthermore, location and number of aging sensors required to be inserted at critical paths output nodes are closely predicted.

IEEE 1149.1-2013 provides compatible IEEE 1500 Wrapper Serial Port access for on-chip DFT and instrumentation access. This presentation shows how IEEE 1149.1-2013 integrates with IEEE 1500 WSPs and adds new capabilities such as wrapper segmentation for low power designs. Example architectures are presented with BSDL descriptions of IEEE 1500 WIRs and wrappers.

Detection of Small Delay Defects (SDDs) is a major concern in modern circuits using nanometer technologies. They are difficult to test and an important source of test escapes, and even when SDDs do not produce functional failures, they represent a reliability risk. The detection of these defects aggravates in the presence of process variations. In this paper, a methodology to detect SDDs in the presence of process variations using delay correlation information between paths of a circuit is proposed. This methodology exploits the concept that for two highly correlated paths, an important part of the delay variance in one path can be described by the delay variance in the second path. The methodology has been further extended to consider multiple path correlation thus improving the detection of SDDs. This methodology is able to distinguish delay defects from process variations. A metric is also proposed to quantify the SDD screenable variance that represents the percentage of variance where a defect can be detected. A statistical timing analysis framework has been developed and implemented to compute timing information and Inter-Path Correlation (IPC). Spatial and structural correlation, and random dopant fluctuations are considered. Simulation results in 74LS85 and ISCAS85 benchmark circuits evince the feasibility of the proposed methodology.

This paper presents a new approach on aging sensors for synchronous digital circuits. An adaptive error-prediction flip-flop architecture with built-in aging sensor is proposed, performing on-line monitoring of long-term performance degradation of CMOS digital systems. The main advantage is that the sensor's performance degradation works in favor of the predictive error detection. The sensor is out of the signal path. Performance error prediction is implemented by the detection of late transitions at flip-flop data input, caused by aging (namely, due to NBTI), or to physical defects activated by long lifetime operation. Such errors must not occur in safety-critical systems (automotive, health, space). A sensor insertion algorithm is also proposed, to selectively insert them in key locations in the design. Sensors can be always active or at pre-defined states. Simulation results are presented for a balanced pipeline multiplier in 65 nm CMOS technology, using Berkeley Predictive Technology Models (PTM). It is shown that the impact of aging degradation and/or PVT (Process, power supply Voltage and Temperature) variations on the sensor enhance error prediction.

CMOS IC scaling has provided significant improvements in electronic circuit performance. Advances in test methodologies to deal with new failure mechanisms and nanometer issues are required. Interconnect opens are an important defect mechanism that requires detailed knowledge of its physical properties. In nanometer process, variability is predominant and considering only nominal value of parameters is not realistic. In this work, a model for computing a realistic coverage of via open defect that takes into account the process variability is proposed. Correlation between parameters of the affected gates is considered. Furthermore, spatial correlation of the parameters for those gates tied to the defective floating node can also influence the detectability of the defect. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS benchmark circuits. The proposed detection probability evaluation together with a test methodology to generate favorable logic conditions at the coupling lines can allow a better test quality leading to higher product reliability.

Electronic systems for safety-critical automotive applications must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is long-term performance degradation due to aging. For safe operation, aging monitoring should be performed on chip, namely using built-in aging sensors (activated from time to time). The purpose of this paper is to present a novel programmable nanometer aging sensor. The proposed aging sensor allows several levels of circuit failure prediction and exhibits low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Simulation results with a 65 nm sensor design are presented, that ascertain the usefulness of the proposed solution.

Interconnect imperfections have become an issue in modern nanometer technologies. Some of them cause Small Delay Defects (SDDs) which are difficult to detect. Furthermore, those SDDs not detected during testing may pose a reliability problem. Nanometer issues (e.g. process variations, spatial correlations) represent important challenges for traditional delay test methods. In this paper, a technique to compute the probability of detection of resistive opens causing SDDs considering process variations is proposed. This technique is used to estimate the Statistical Fault Coverage (SFC) of a circuit. In order to estimate the SFC of a circuit, the delays are propagated using statistical timing analysis, and the analyzed space of possible delay fault locations is obtained using stratified sampling techniques. This methodology is applied to some ISCAS benchmark circuits. The obtained results show the feasibility of the proposed methodology. Measures can be taken for those circuits presenting non-acceptable fault coverage in order to improve their test quality.

The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, which may occur in safety-critical systems (automotive, health, space). Error is prevented by detecting critical paths abnormal (but not fatal) propagation delays. A monitoring procedure and a programmable aging sensor are proposed. The sensor is selectively inserted in key locations in the design and can be activated either on user's requirement, or at pre-defined situations (e.g., at power-up). The sensor is optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Sensor limitations are analysed. A new sensor architecture and a sensor insertion algorithm are proposed. Simulation results are presented with a ST 65 nm sensor design.

In this paper, circuit failure prediction by timing degradation is used to monitor semiconductor aging, which is a safety-critical problem in the automotive market. Reliability and variability issues are worsening with device scaling down. For safe operation, we propose on-chip, on-line aging monitoring. A novel aging sensor (to be selectively inserted in key locations in the design and to be activated from time to time) is proposed. The aging sensor is a programmable delay sensor, allowing decision-making for several degrees of severity in the aging process. It detects abnormal delays, regardless of their origin. Hence, it can uncover ¿normal¿ aging (namely, due to NBTI) and delay faults due to physical defects activated by long circuit operation. The proposed aging sensor has been optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Moreover, the area overhead of the new architecture is significantly less than the one of other aging sensors presented in the literature. Simulation results with a 65 nm sensor design are presented, ascertaining its usefulness and its low sensitivity, in particular to process variations.

Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.

Resistive opens in vias and interconnection lines have become an issue in modern nanometer technologies. These defects may produce small delays which are difficult to detect and may pose a reliability problem. In this paper, a statistical timing analysis framework is used to analyze the detectability of small delays due to resistive opens considering process variations. A statistical methodology to estimate the fault coverage of these defects is proposed. Using the proposed methodology, the statistical fault coverage of resistive opens producing small delays is evaluated for some ISCAS benchmark circuits.

Complex electronic systems for safety or mission-critical applications (automotive, space) must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is to monitor long-term performance degradation due to aging in such harsh environments. For safe operation, or for preventive maintenance, it is desirable that such monitoring may be performed on chip. On-line built-in aging sensors (activated from time to time) can be an adequate solution for this problem. The purpose of this paper is to present a novel methodology for electronic systems aging monitoring, and to introduce a new architecture for an aging sensor. Aging monitoring is carried out by observing the degrading timing response of the digital system. The proposed solution takes into account power supply voltage and temperature variations and allows several levels of failure prediction. Simulation results are presented, that ascertain the usefulness of the proposed methodology.

The stuck-open fault (SOF) is a difficult, hard failure mechanism unique to CMOS technology. Its detection requires a specific 2-vector pair that examines each transistor in the logic gate for an open defect in its drain and/or source. In this work it is shown that this failure mechanism is very alive and relevant to modern technologies. The small nanometer technology capacitances and the increased leakage currents result in faster discharges of the floating high impedance node making fault detection more difficult. A test vector strategy is proposed to improve the detection of this fault for technologies with gate current leakage.

Process variations have become a critical issue influencing the performance of nanometer digital circuits at gigascale integration; variations are classified in two types: inter-die and intra-die. Whereas inter-die variations affect the deviation of performance distribution in a lot of chips, intra-die variations affect the media of performance distribution. The present work proposes a new design methodology for designing logic paths tolerant to local intra-die variations. A library of transistor structures with different degree of delay variability is defined. Transistors from the logic gates are replaced with these structures according to selection criteria to improve the delay tolerance to process variation on logic paths. Delay variability is reduced at the expense of circuit area. Results show a significant variability reduction for a moderate increment of area and power consumption.

In this paper, a design-for-testability (DFT) technique to test open defects in otherwise undetectable faulty branches in fully static CMOS latches and flip-flops is proposed. The main benefits of our proposal are: 1) it is able to detect a parametric range of resistive opens defects and 2) the performance degradation is very low. The testability of the added DFT circuitry is also addressed. The cost of the proposed technique in terms of speed degradation, area overhead, and extra pins is analyzed. Comparison with other previously proposed testable latches is carried out. Circuits with the proposed technique have been designed and fabricated. Good agreement is observed between the analytical analysis, simulations and experimental measures performed on the fabricated circuits.

Open defects in CMOS memory elements are investigated. The analysis has been carried-out in a class of symmetrical CMOS flip-flop. Main focus is given to high resistive opens in gates. These defects depend on initial conditions prior to the application of the test vectors. Test conditions influencing the detectability of opens in scan path chains are also analyzed. Some sequences of 1's and 0's may fail for detecting opens in gates. Conditions for the input sequences for scan path chains are stated. The dependence of the detectability of opens on the duty cycle is also investigated. Experimental results showing the dependence of the behavior of open gates with the initial conditions are shown.

The effect of the parasitic values on the ground bounce voltage and on the delay is investigated. Also the effect of ground bounce on the delay in depth paths is analyzed. A ground bounce attenuation proposal is investigated. This can be done using a circuitry to generate ground bounce before the activation of the main circuit. The impact on the circuit delay is observed.

Signal integrity verification is becoming an important issue as technological process features continues to shrink and logic speed increases. Advanced technologies permit a large number of integrated devices onto chip, this characteristic enable to have high performance systems which request good levels of signal integrity. A monitoring technique for the verification of the signal integrity is presented. Two monitors are proposed in order to sense signal undershoots and overshoots at high and low logic levels respectively. The cost of the proposed verification strategy has been estimated in terms of area, extra pins and delay penalisation. Using coherent sampling, the monitors detect signal integrity violations for high speed critical signals.

The behavior of a class of CMOS latches in the presence of resistive opens is investigated. The detectability of resistive opens by delay testing is analyzed. The resistive opens in the driver and inverter stages are classified according to its behavior. Opens occur in conducting paths, single open gates and multiple open gates. Opens in conducting paths are the easiest to detect and opens in single open gates are the most difficult to detect. Resistive opens in the clocked inverter deserves special attention. Some open locations in this stage are well known as undetectable by a traditional voltage test. A DFT (Design for Testability) approach is proposed for opens in conducting paths of the clocked inverter stage. The cost of the DFT approach in terms of speed degradation and area overhead is evaluated. A comparison is made with other testable latches structures proposed in the literature. Other two interesting cases of opens in the clocked inverter have been found.

The detectability of interconnection opens by logic and I/sub DDQ/ testing is investigated. Opens in interconnection paths disconnect the driven gate(s) from the driving gate. An electrical model for interconnection opens is used to predict the detectability of this type of open. Using the proposed model, explicit analytical expressions have been obtained to determine the conditions for reliable detection of this defect by logic and I/sub DDQ/ testing. The cases of full controllability and non-full controllability of the signals at the coupling lines have been analysed. The effect of the trapped charge during fabrication has also been investigated. In addition, it has been found that the detectability of interconnection opens depends on the metal level where the signals are laid-out. The detectability dependency of interconnection opens on the test generation process has been analyzed.

The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the precharge. Two techniques to test open defects producing data retention faults are proposed. In the first technique an initial condition is forced during the working phase. In this way, intermediate voltages appear during the memorizing phase. Hence, the quiescent current consumption (I/sub DDQ/) increases and the fault can be detected sensing the I/sub DDQ/. A second technique controlling the power supply level in conjunction with sequential access is proposed. This allows detection of open defects by I/sub DDQ/ testing. The cost of both proposed approaches is analyzed.

The logic detectability conditions of floating gate (FG) defects in sequential circuits are considered. It has been found that a FG defective sequential circuit may be able to memorize one or two logic states depending on the values of the defect parameters. I/sub DDQ/ testing may detect a large class of floating gate defects including some defective transistors located in logically untestable branches. Good agreement is observed between the theoretical and simulated results with experimental measurements performed on a typical scan path cell designed intentionally with floating gate defects.

The behavior of an MOS transistor with an open in the polygate path (floating transistor gate defect) is investigated and its effect on the quiescent power supply current I/sub DDQ/ is studied. The possible detection of this defect by current testing is explored in fully complementary CMOS circuits. The behavior of a transistor with its floating gate is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The poly-bulk and metal-poly capacitances are found to be two significant parameters in determining the degree of conduction on the affected transistor. The induced voltage in the floating gate and the quiescent current are estimated by analytical expressions. The model is compared with SPICE 2 simulations. Good agreement is observed between the simple analytical expressions, simulations and experimental measures performed on defective circuits. In addition, it is shown that the floating gate transistor can be modeled as a weakly conductive stuck-on transistor or as a stuck-open transistor depending on the values of the parameters characterizing the defect.>