The coprocessor computer architecture has a main processor and one or more coprocessors. The author proposes the use of the coprocessor computer architecture for realizing high-performance, application-specific parallel computers. The author presents a classification of coprocessor computer organization. Matching a coprocessor computer organization with a parallel algorithm is suggested. As an example, a lexical/parsing coprocessor, which can deliver tokens from lexical processing at the rate of one million per second and semantic-rule codes from parsing at the rate of 2.5 million per second is described. This coprocessor shortens compilation time, reduces compiler size, and lessens programmer effort. This result clearly shows the potential use of the coprocessor computer architecture for application-specific computers.>

This paper describes language constructs for creating a very high-level language as a tool for computer system design. In order to describe the complexity of a computer system, this language permits descriptions in a heirarchical manner at different levels of system detail and at various cross-sections of system structure. It allows descriptions of system hardware, system software, and the interactions between system hardware and software.

Data interpretation refers to the execution of the data declarations of a high-level language program which declare the data variables, the data types, and the data structures in the high-level language program. This paper introduces the direct-execution computer architecture and presents the architecture of a hardware data interpreter. The data interpreter scans the data declaration, and stores the type, structural, and referencing information about the data in an associative memory. It then interprets the data when the data name is referred to. It also performs the data operations of the data types of the high-level programming language.

A structured program is organized in modules of procedures; each procedure is constructed with single-in-single-out control constructs. The call and return structure among these procedures is often not described. Understanding this interprocedure structure, however, can contribute to a reliable program. This paper introduces the concept of "interprocedure structure" which describes the call and return structure of procedures. It also presents a technique by which the interprocedure structure can be described.

DATA INTERPRETATION REFERS TO THE EXECUTION OF THE DATA DECLARATIONS OF A HIGH-LEVEL PROGRAMMING LANGUAGE PROGRAM, WHICH DECLARE THE DATA TYPES AND THE DATA STRUCTURES IN THE PROGRAM. THIS PAPER PRESENTS A DATA INTERPRETER WITH A HIGH-LEVEL MEMORY STRUCTURE WHERE THE DATA IS STORED IN A RANDOM-ACCESS MEMORY, WHILE THE TYPE, STRUCTURAL, AND REFERENCING INFORMATION ABOUT THE DATA IS STORED IN AN ASSOCIATIVE MEMORY, WHEN THE HARDWARE DATA INTERPRETER SCANS THE DATA DECLARATION, IT MAKES ENTRIES INTO THE ASSOCIATIVE MEMORY. IT THEN INTERPRETS THE DATA WHEN THE DATA NAME IS REFERENCED. THE STORAGE STRUCTURES, CONTROL STRUCTURES, PROCESSORS AND DATA OPERATIONS OF THE HARDWARE DATA INTERPRETER ARE DESCRIBED. AN EXAMPLE OF INTERPRETING A STRUCTURE DATA DECLARATION IS USED TO ILLUSTRATE THE DATA INTERPRETER.

It is our habit in writing an English composition that, as we write each word, each phrase, each sentence, and each paragraph, we consciously or unconsciously check the syntax and the semantics of the composition just written. Writing a computer program in a high-level language could be made similar to writing a composition in English. In this case, a highly interactive highlevel language system checks the syntax and the semantics of the highlevel language program as each symbol, each expression, and each statement are being entered at the terminal. When the source program is completely entered, the program could have been debugged and could have run once.

This panel is composed of the chairmen of the task forces of the DISE (Digital Systems Education Committee). DISE is a project sponsored by the NSF and managed by University of Pittsburgh for the purpose of generation and dissemination of educational material on all aspects of digital system education. The panel members will discuss the current activities of these task forces and then seek the audience's participation in learning more about the status and need of current digital system education.

The paper presents a methodology for software engineering. This methodology recognizes the existence of two separate and distinctive phases (architecture and implementation) of a software engineering task. These two phases are interfaced by a formalized but descriptive design specification described by a language called ADL (architectural design language). This ADL description would serve a similar purpose as that served by the blueprint. Implementation can then be accomplished from the `software blueprint' in any of three possibilities: software, hardware, or microwave. Design of a lexical scanner is chosen as an example to illustrate this methodology.

This paper describes the use of a very high-speed scratch pad memory for directly executing programs in floating code with a single origin or multiple origins. When a program is being loaded into the magnetic core memory of a digital computer, there is no need of modifying the addresses of the original code. Neither the programmer, nor the operator, nor the program loader has to know where are the available locations in the magnetic core memory. During the subsequent execution of the program, the logical and physical correspondence of the addresses of the code is found by hardware address interpretation. The operations involved in address interpretation are described as well as the organization and control sequence of the computer. The use of the scratch pad memory can also be extended for dynamic allocation of magnetic-core memory locations and for memory protection of all programs which do not have to lie in physically contiguous areas of the memory.

The organization of an associative memory which makes use of conventional destructive-readout magnetic elements is presented. The associative memory described is word-organized; an example is an array of memory elements of 64 bits by 1024 bits. The memory is both location-addressable and content-addressable, and capable of bit-parallel search. A unique feature is its two-dimensional read/write capability, resulting (for the example) in a short-word length of 64 bits and a long-word length of 1024 bits. Such an associative memory is proposed mainly for nonnumerical data processing rather than for storage. The bit-parallel search logic is not embedded in each memory element, but is implemented for a long-word at the exterior of the memory array. As a result, this associative memory is less costly than an associative memory where parallel logic is built into each memory element. Because parallel-search logic is implemented for only one long-word, implementation of several varieties of search logic is practical. In addition to a bit-comparison logic, other logical operations (such as NAND, NOR, AND, OR) can be implemented relatively simply and less expensively.