We present a three-module pedagogical framework for structured AI integration in undergraduate programming labs. Rather than banning or freely permitting AI, the framework escalates AI access within a single lab: ask-only for concept learning (Module 1), syntax and error assistance only for student-authored code (Module 2), and agent mode with mandatory review for collaborative coding (Module 3). Deployed in an undergraduate data structures course at Stony Brook University, N = 128 survey responses show that 93.8% of students intend to use AI again, 78.9% could explain their solutions without AI help, and only 13.3% felt AI use resembled cheating.

Groups engaged in brainstorming undergo several types of ideation processes, some more effective than others. Current methods for characterizing the knowledge expressed in a group and its dynamics include embedding models and cosine distance between idea embeddings that do not find explicit semantic connections, or knowledge graphs that represent semantic connections but need large amounts of data to extract. We are proposing a novel idea graph model that combines embedding models and a graph representation of knowledge, together with a novel group problem-solving model. Using the graph representation and the evaluation measures, we identified and characterized more effective groups from experimental data and verified the main hypotheses derived from the theoretical model.

Studying the dynamics of research communities has been an important yet tedious topic. It is important for devising management policies that optimize the quality of research outputs by promoting a certain composition, structure, and interaction patterns for a community. While there has been significant attention to understanding the roles of individuals, there has been less focus on studying the roles that research groups perform and how roles relate to the characteristics of the community. This article presents an experimental study on the roles that research groups have in the idea flow through a community. The study analyzes two facets: the contribution of different kinds of groups to the impact research ideas make on other groups and the importance of specific groups to connect a community together. The results showed that research groups can be classified into four categories depending on the number of received citations. Groups of the mid-tier categories (called categories B and C in this article) are important in tying a community together as they improve the idea impact and bridging between groups. Policies that aggressively eliminate such groups reduce the effectiveness of idea flow, even though research communities include a certain amount of robustness for moderate levels of group removals.

Group learning offers novel yet intriguing opportunities to improve a community's effectiveness by obtaining insight into the emergence of new design problems and concepts. This article proposes a new computational model and the related algorithmic methods to characterize circuit design communities over time. The bottom-up model explains knowledge evolution using two operators, combination/improvement for knowledge expansion, and blocking for concept elimination. New metrics were proposed to describe the effect of the two operators. Experiments considered three large data sets of circuit designs (switched-capacitor filters, CMOS OpAmp/OTAs, and ΔΣ ADCs). Opportunities to improve the communities were discussed.

In creativity research a typical problem is that of assessing the novelty of ideas or solutions generated by many people to open ended problems. For datasets larger than a few hundreds, human assessment of novelty becomes time consuming and error prone. Existing novelty detection methods such as: distance based text similarity or language model approaches do not work well for small datasets. Moreover, when compared to human novelty ratings, these approaches fail to capture the same cognitive processes or biases. We are proposing a novel cognitive model inspired by a leaky accumulator decision making models for detecting novel ideas from short text. The model is applied on a collection of ideas generated in a group brainstorming experiment. It evaluates an idea term by term and it accumulates surprise and relevance. The final novelty decision is taken at the end of each idea by means of a threshold. An important component of the model is a small domain dataset which is used to evaluate the surprise of a term's context compared to common domain knowledge. The model is compared with other methods: feature based classifiers, tf-idf similarity distance, and pretrained language models (ULMFIT).

Automated analog circuit synthesis algorithms are conceptually different from manual design procedures mainly because of their limited learning capabilities, including understanding the causal justifications for certain design decisions. However, the causal information is critical for activities like constructing new circuit topologies, incrementally updating existing designs, circuit verification, and improving design optimization. This paper presents a model to represent the causal elements embedded in an analog circuit design and the methodology and algorithms to automatically extract the causal information. Experiments discuss the methodology for two state-of-the-art OpAmp/OTA circuits.

This paper presents InnovA, a cognitive architecture for creative problem solving in analog circuit design, e.g., topology creation (synthesis), incremental topology modification, and design knowledge identification and reuse. The architectural modules attempt to replicate cognitive human activities, like concept formation, comparison, and concept combination. The architecture uses multiple knowledge representations organized using topological similarity and causality information. Solutions are clustered, so that each cluster represents a specific set of performance tradeoffs, thus a fragment of the Pareto front in the solution space. New structural features are created through variation of existing features. New solutions are created by combining features from the same cluster, distinct clusters, and features that originate a new cluster. The related algorithms are discussed in this paper too. The architecture also incorporates modules mimicking the using of human emotions in memory formation and decision making, but these modules are still under development and are a main direction for our future work. This paper presents a number of examples to illustrate its using in various analog circuit design activities that are hard to be realized with traditional computational methods.

This paper describes three learning methods to acquire new insight and knowledge on how structural features relate to performance and constraints. Learning is at the feature-, concept-, and constraint-level. Experiments present the three learning types for a set of modern analog circuits and illustrate the using of the gained information for circuit synthesis.

This paper presents a method to design optimized local control strategies for Cyber-Physical Systems that produce reliable data models for social applications. Data models have different semantics and abstraction levels. The local control strategies manage ad-hoc nano-clouds of embedded computing and communication nodes (CCNs) used for data collection, modeling, and communication. Control strategies consider tradeoffs defined by the resource constraints of embedded CCNs (e.g., computing power, communication bandwidth, and energy), assurance requirements (e.g., robustness) of the models, and privacy of users. Experiments evaluate and demonstrate the effectiveness of the control strategies for nano-clouds composed of smart voice-based interaction-tracking badges.

Label Propagation is a semi-supervised learning algorithm typically applied to partially labeled graph data sets for classifying unlabeled nodes. Similar to the Personalized PageRank algorithm, Label Propagation is in essence a random walk on a graph, resting on the assumption that similar nodes are more likely to form edges. Graph based models and analysis inform companies about their customers and help make recommendations for targeted ad placement when databases are sparse. We generalize the concept of label propagation to constrain the random walk to regions of the search space where the true solution may lie based on prior knowledge. Specifically, we reformulate the label propagation algorithm as a minimum energy control problem that embraces traditional label propagation as a special case. We apply the formulation to (i) benchmark data sets, and (ii) the Yelp challenge data set. Results indicate the approach is comparable to competing methods for the benchmark data. For the Yelp data, our experiments show a promising 20%-50% improvement over the baseline for select business features.

This paper introduces a three stage low voltage, low power amplifier created by a design knowledge-intensive circuit topology synthesis methodology. The synthesis method flow begins with a set of starting ideas and then continues with a sequence of justified, causal design steps. Starting ideas combine physical and abstract features from either previous design or new insight. After combining the starting ideas, the related design sequence is identified step by step, so that each step either improves performance or relaxes design constraints. The created Opamp is a novel low voltage, low power circuit with better setting time (small signal characteristic) and slew rate (large signal characteristic). The proposed Opamp is realized in 0.2-μm CMOS technology. At 1-V supply voltage, it consumes less than 70μW static power. When driving a 5-pF capacitive load, the amplifier achieves 24MHz gain-bandwidth-product (GBW) and 5.1-V/μs average slew rate.

Mining engineering metaknowledge from electronic documents is important in devising new design solutions for emerging applications as well as in identifying new business opportunities. Continuously and comprehensively reviewing and assessing the entire technical literature to find the most relevant ideas and solutions is cumbersome as engineering innovations are constantly being proposed. In particular, high performance analog circuit design has been at the forefront of technological innovations given their importance in applications, like telecommunications, mobile applications, and health care. This paper proposes a model and mining techniques for representing analog circuit design metaknowledge. The metaknowledge representation includes three components: an associative component presenting the conceptual hierarchy of the considered circuits, a component expressing the performance capabilities (e.g., tradeoffs and bottlenecks) of the circuits, and a causal modeling part describing the more likely starting ideas and design plans used to create a circuit. Knowledge structures can be used to tackle new applications, identify opportunities to improve existing circuits, and validate design correctness. A case study illustrates the proposed knowledge structure for a set of 30 modern, high-frequency analog circuits.

This paper presents a reasoning-based approach to analog circuit synthesis using ordered node clustering representations (ONCR) to describe alternative circuit features and symbolic circuit comparison to characterize performance tradeoffs of synthesized solutions. Case studies illustrate application of the proposed methods to topology selection and refinement.

Creating accurate data models describing the dynamics of physical phenomena in time and space is important in optimized control and decision making. Models highlight various trends and patterns. However, producing accurate models is challenging as different errors are introduced by sampling platforms with limited resources, e.g., insufficient sampling rates, data loss due to buffer overwriting, reduced communication bandwidth, and long communication delays. Furthermore, the dynamics of the environment, like mobile energy sources and sinks, might further increase errors as resources must be shared between the sampling and communication activities. This paper presents a procedure to systematically construct robust data models using samples acquired through a grid network of embedded sensing devices with limited resources, like bandwidth and buffer memory. Models are in the form of ordinary differential equations. The procedure constructs local data models by lumping state variables. Local models are then collected centrally to produce global models. The proposed modeling scheme uses a linear programming formulation to compute the lumping level at each node, and the parameters of the networked sensing platform, i.e., best data communication paths and bandwidths. Two algorithms are described to predict the trajectories of mobile energy sources/sinks as predictions can further reduce data loss and delays during communication. The computed parameters and trajectory predictions are used to configure the local decision making routines of the networked sampling nodes. Even though the procedure can be used to model a broader set of phenomena, experiments discuss the effectiveness of the method for thermal modeling of ULTRASPARC Niagara T1 architecture. Experiments show that the presented method reduces the overall error between 58.29% and 76.91% with an average of 68.87%, and communication delay between -11.49% and 57.62% with an average of 21.85%.

This paper presents a dual-process architecture for reasoning in design innovation problems. The architecture includes (i) a uniform mechanism to create various associations among concepts and (ii) a procedure to construct rule-based reasoning flows through abstraction of associated concepts. Three reasoning procedures are discussed based on the architecture. Two case studies show that the dual-process architecture can be utilized for various innovation-related tasks, like searching the solution space search beyond the capabilities of statistical methods and identifying hints to improve the novelty of designs, hence exiting fixation.

In this paper we study the effect of external ideas on brainstorming by means of two computational models: a transient emergent attractors model (TEAM) and a probabilistic associative model (PAM). New behavioral experimental results show that hints or others' ideas can either hinder or enhance ideas generated during exposure period, while they consistently enhance the quantity of ideas produced after exposure. The TEAM model consists of a neural network of concept nodes connected by means of category membership and relatedness. Ideas emerge dynamically from the activity of the network by temporarily strengthening the connections between co-active nodes. Local inhibition inactivates current idea nodes and allows another idea to form. Active nodes prime connected inactive nodes depending on the recent activity of the node. The model shows that hindering of the number of ideas during hint presentation depends on the strength of hints and that the speed and duration of priming is essential for the long-term priming effect of hints observed in experiments. For comparison purposes, a PAM model originally proposed by Brown and Paulus (1998) is used to explain the same experimental data.

This paper proposes an automated technique for systematically generating comparison data between two analog circuits. The comparison data presents the similar and distinguishing performance characteristics of the circuits with respect to DC-gain, bandwidth, common-mode rejection ratio, noise, and sensitivity. The comparison data is important for getting insight into the common and unique benefits of a circuit, selecting fitting circuit topologies for system design, and refining and optimizing circuit topologies. The technique utilizes matching of the topologies and symbolic expressions of the compared circuits to find the nodes with similar electric behavior. The impact on performance of the unmatched nodes is used to express the differentiating characteristics of the circuits. Experiments illustrate the technique for a pair of analog circuit designs.

Cyber-physical systems (CPS) are large, distributed embedded systems integrated with various sensors and actuators. CPS are rapidly emerging as an important computing paradigm in many modern applications. Developing CPS applications is currently challenging due to the sheer complexity of the related functionality as well as the broad set of constraints and unknowns that must be tackled during operation. This article presents a novel high-level programming model and the supporting optimization and middleware routines for executing applications on physically-distributed networks of reconfigurable embedded systems. The proposed model describes the optimization goals, sensing inputs, actuation outputs, events, and constraints of an application, while leaving to the compiler and execution environment the task of optimally implementing the derived functionality. Experimental results discuss the additional performance optimizations enabled by the proposed model, and the timing and power consumption of the middleware routines, and present a temperature monitoring application implemented on a network of reconfigurable, embedded processors.

This paper presents a technique for automated generation of hierarchical classification schemes to express the main similarities and differences between analog circuits. The produced classification schemes offer insight about the uniqueness and importance of specific design features in setting various performance attributes as well as the limiting factors of designs. Hence, the classification schemes serve as a systematic way of relating one circuit design to alternatives. The automatically produced classification schemes for a set of OpAmps are discussed.

This paper proposes two new heuristic methods for real-time distributed traffic monitoring through video cameras. The goal is to minimize the field-of-view (FOV) loss of the cameras due to dynamic obstacles while considering the timing constraints of the application. The methods utilize different cost functions to select the cameras used in FOV loss recovery. The cost functions are based on a new stochastic model for traffic monitoring, including the dynamics of mobile obstacles, unreliable communication, and resolution and timing constraints. The first cost function addresses deterministic situations by capturing the tradeoff between the quality of recovery and the imposed timing constraints. The second cost function captures stochastic aspects, such as a camera being obstructed by obstacles or experiencing data losses due to unreliable communication. Experiments show that the two methods offer reliable FOV loss recovery for a large variety of conditions. The methods are fast and scale well with the number of monitored cars and cameras. The average FOV loss recovery of the deterministic heuristic is 52%, but the resulting coverage remains close to 100% most of the time, whereas without the recovery scheme, the coverage drops to about 60% about half the time. For time-constrained unreliable communication, the stochastic heuristic offers coverage that is only about 15% less than if communication is unrestricted.

Cyber Physical Systems are distributed systems-of-systems that integrate sensing, processing, networking and actuation. Aggregating physical data over space and in time emerges as an intrinsic part of data acquisition, and is critical for dependable decision making under performance and resource constraints. This paper presents a Linear Programming-based method for optimizing the aggregation of data sampled from geographically-distributed areas while satisfy timing, precision, and resource constraints. The paper presents experimental results for data aggregation, including a case study on gas detection using a network of sensors.

This paper presents a systematic methodology for designing the adaptation policies of reconfigurable sensor networks. The work is motivated by the need to provide efficient sensing, processing, and networking capabilities under tight hardware, bandwidth, and energy constraints. The design flow includes two main steps: generation of alternative design points representing different performance-cost trade-offs, and finding the switching rates between the points to achieve effective adaptation. Experiments studied the scaling of the methods with the size of the networks, and the effectiveness of the produced policies with respect to data loss, latency, power consumption, and buffer space.

This paper presents a systematic methodology for developing structural macromodels expressing the linear and weakly nonlinear performance of analog circuits. The models are in the frequency domain. The methodology includes two steps. First, building-block behavioral (BBB) concept is used to describe the basic building blocks of a circuit, and a decoupling technique is used to generate uncoupled BBB structural circuit models. Then, a nonlinear system is represented as a system with nonlinear inputs and linearly coupled blocks, and the linear couplings are removed. Experiments are offered for single-stage OpAmp, three-stage OpAmp, and operational transconductor amplifier (OTA) circuits. The produced models are tunable for the required accuracy, offer insight into the circuit operation, and offer simulation time speedup as compared to SPICE simulation.

This paper presents a systematic methodology for producing reconfigurable ΔΣ modulator topologies with optimized flexibility in meeting variable performance specifications. To increase their flexibility, topologies are optimized for performance attributes pertaining to ranges of values rather than being single values. Topologies are implemented on switched-capacitor reconfigurable mixed-signal architectures. As the number of configurable blocks is very small, it is extremely important that the topologies use as few blocks as possible. A case study illustrates the methodology for specifications from telecommunications area

This paper proposes a systematic methodology for designing reconfigurable continuous-time DeltaSigma modulator topologies. Topologies are optimized by minimizing the complexity of the topologies, maximizing the sharing of circuits between the different modes, maximizing the topology robustness with respect to circuit nonidealities, and minimizing the total power consumption. This paper presents a case study for designing topologies for a three-mode reconfigurable DeltaSigma modulator and compares the obtained topologies with a state-of-the-art design and topologies obtained using the DeltaSigma Toolbox

This paper presents a stochastic approach for bus arbiter design. Arbiter design includes policy design, buffer insertion, and optimal buffer sizing. The methodology uses continuous-time Markov decision processes (CTMDPs) to get optimal arbitration policies and buffer space distribution. The mathematical formulation of this problem in terms of a CTMDP framework leads to a linear programming problem for bus architectures without bridges, and to a nonlinear formulation for bus architectures with bridges. In the second case, the methodology splits the nonlinear problem into several smaller, linear subsystems by introducing buffers at the bridges, and then solves the linear subsystems. In our experiments, we found that stochastic policies provide efficient arbitration for bus architectures with redundant buses for communication between processors. The size of buffers in some cases was reduced by 90%, and by 50% in the average sense. Data loss was reduced by 20% to 50% with redistribution of the buffer space

This paper presents a systematic methodology for developing structural nonlinear macromodels for analog circuits. The methodology includes two steps: first, a nonlinear system is represented as a system with nonlinear inputs and linearly coupled blocks. Then, the linear couplings are removed. The methodology also uses a novel description of circuit nonlinearities as a successive composition of three operators. The generated nonlinear models are scalable, tunable according to the required accuracy, and offer insight into the circuit operation.

This paper proposes a methodology for designing reconfigurable continuous-time DeltaSigma modulator topologies. The methodology is based on the concept of generic topology that expresses all possible signal paths in a reconfigurable topology. Topologies are optimized for minimizing the complexity of the topologies, maximizing the sharing of circuitry for different modes, maximizing the topology robustness with respect to circuit nonidealities, and minimizing total power consumption. The paper presents a case study for designing topologies for a three mode reconfigurable DeltaSigma modulator, and compares topologies with state-of-the-art design

This paper describes an original methodology for accurately modeling MOSFET process parameter variations. As compared to other process parameter variation modeling methods, the proposed methodology is capable of correctly modeling not only differences of process/model parameters, but also the process parameter variations for individual devices. This capability is very important for popular analog circuits like current biasing circuits, voltage reference circuits, and single-ended output amplifiers

The design of reconfigurable DeltaSigma modulators requires cumbersome circuit-level simulations. Besides the challenges inherent to high-performance analog-to-digital converter (ADC) design, the gap between system-level specification and circuit-level implementation makes the design even more difficult and inefficient. Circuit macromodels are an efficient way of tackling these problems by speeding up simulation and offering insight into circuit design. This paper presents a library of structural macromodels customized for cells used in DeltaSigma modulator design. We present original structural macromodels for two operational amplifier (opamp) and one operational transconductor amplifier (OTA) circuits. These cells are used to implement the loop filter in continuous-time DeltaSigma modulators. The proposed library helps the designer capture circuit-level constrains and tradeoffs before doing circuit implementation. It also makes top-down design of analog circuits more efficient by meaningful abstracting circuit-level parameters to a higher design level

This paper proposes a novel topology-synthesis methodology for single-loop single-bit /spl Delta//spl Sigma/ modulators. The goal is to explore all possible topologies and to obtain the optimal topology under various design considerations, such as hardware complexity, modulator sensitivity, and power consumption. A generic modulator architecture that incorporates all possible feedback and feedforward signal paths was defined and the symbolic noise transfer function (NTF) and signal transfer function (STF) for the generic topology were derived. The symbolic functions were then used to formulate the topology-exploration problem as a mixed-integer nonlinearly constrained programming (MINLP) problem that simultaneously generates and selects the optimal modulator topology with respect to the cost function. Experiments show the superiority of synthesized topologies as compared to traditional modulator topologies.

This paper presents a novel algorithm for synthesis of continuous-time analog filters. The goal is to find as many "very good" design points as possible without requiring feasible designs as starting points or any other additional designer knowledge as input. This problem is challenging for present exploration-based analog-synthesis methods, including existing commercial tools, which have difficulties in locating diverse constraint-satisfying designs. The proposed algorithm conducts a three-step refinement process, in which poor-quality solution-space regions are eliminated through different strategies. It starts with the step of parameter-domain pruning, which identifies parameter subdomains that are more likely to produce many feasible solution points. Domains are found using interval arithmetic and the proposed simplified affine transformation operators. In the second step, selected variable subdomains are searched using plateau search, a novel exploration technique described in this paper. The algorithm addresses the three main types of solution-space regions: 1) convex, quasi-convex, and /spl delta/-convex regions; 2) rifts; and 3) plateau. The technique expands descendant-gradient-based search with a systematic way of sampling plateau. Finally, promising regions that remained after step 2 are further refined during the step of search with adaptive-sampling step length. Using four filter examples, experiments observed the quality of results and convergence of synthesis. Plateau search was also experimented for synthesis of two /spl Delta//spl Sigma/ modulators.

This paper presents a systematic methodology to create customized structural macromodels for a specific analog circuit. The novel contributions of the method include definition of the building block behavioral concept and two original algorithms to generate structural models. Experiments are offered for two-stage opamp and operational transconductor amplifier (OTA) circuits. The automatically produced models are accurate, offer design insight, and require low modeling effort.

We have presented an optimal buffer sizing and buffer insertion methodology which uses stochastic models of the architecture and continuous time Markov decision processes CTMDP. Such a methodology is useful in managing the scarce buffer resources available on chip as compared to network based data communication which can have large buffer space. The modeling of this problem in terms of a CTMDP framework lead to a nonlinear formulation due to usage of bridges in the bus architecture. We present a methodology to split the problem into several smaller though linear systems and we then solve these subsystems.

The paper proposes a novel architecture synthesis algorithm for single-loop single-bit /spl Delta//spl Sigma/ modulators. We defined a generic modulator architecture and derived its noise and signal transfer function (NTF/STF) in symbolic forms. We then used the TF in MINLP (mixed integer nonlinearly constrained programming) to generate optimal topologies for a variety of design requirements, such as modulator complexity, sensitivity and power consumption, which appeared as cost functions. Experiments show the superiority of the synthesized topologies as compared to traditional solutions.

We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer space and presents a method to distribute this finite space in an optimal fashion. Such a methodology is useful in managing the scarce buffer resources available on chip as compared to network based data communication which can have large buffer space. The methodology also uses Continuous Time Markov Decision Processes CTMDPs. The modeling of this problem in terms of a CTMDP framework lead to a nonlinear formulation due to usage of bridges in the bus architecture. We present a methodology to split the problem into several smaller, though linear systems and we then solve these subsystems.

This paper presents substrate noise macro-models for standard digital cells, like INV, NAND and BUFFER. The macro-models are based on a scalable substrate network template and a compact MOSFET model equivalent to EKV model. Our models and simulator predicted the substrate voltage, injection currents, and output voltage of each primary digital cell. Proposed models are close to device physics and valid for different processing technology and input transition. They are more accurate as compared to macro-models generated from curve fitting. Our macro-model accuracy is within 5-10% from SPICE simulation with MOSFET level49 models, and at least 4 times faster. This model can be used to predict spatially and temporally the occurrence of substrate noise peaks in a digital design.

This paper presents a layout-conscious approach for hardware/software codesign of systems-on-chip (SoCs) optimized for latency, including an original algorithm for bus architecture synthesis. Compared to similar work, the method addresses layout related issues that affect system optimization, such as the dependency of task communication speed on interconnect parasitic. The codesign flow executes three consecutive steps: 1) combined partitioning and scheduling: besides partitioning and scheduling, this step also identifies the minimum speed constraints for each data link; 2) IP core placement, bus architecture synthesis, and routing: IP cores are placed using a hierarchical cluster growth algorithm; bus architecture synthesis identifies a set of possible building blocks and then assembles them for minimizing bus length and complexity; poor solutions are pruned using a special table structure and select-eliminated method; and 3) rescheduling for the best bus architecture. This paper offers extensive experiments for the proposed codesign method, including bus architecture synthesis for a network processor and a JPEG SoC.

System-level design has a disadvantage in not knowing important aspects about the final layout. This is critical for SoC, where uncertainties in communication delay by very deep submicron effects cannot be neglected. This paper presents a layout-aware bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. BA synthesis includes finding bus topology and routing individual buses, so that constraints like area, bus speed and length, are tackled at the physical level. The paper presents the BA automatically synthesized for a network processor and a JPEG SoC.

A system level design methodology is applied to the embedded system design for a typical sensor network application: face detection for security purpose. The tradeoff analysis is performed for hardware and software implementations of the tasks in this application. The best system design is achieved with limited hardware resources.

This paper presents a synthesis methodology for analog systems described using VHDL-AMS language. Synthesis produces net-lists of analog components that are selected from a library, and sized so that specified objectives (like AC response, signal to noise ratio, dynamic range, area) are optimized. The gap between abstract specifications and implementations is bridged using a two-layered methodology. The first layer is architecture generation. The second layer is component synthesis and constraint transformation. Architecture generation employs the branch-and-bound algorithm to create architectural alternatives for a system. Component synthesis and constraint transformation use a directed interval based genetic algorithm that operates on parameter ranges. The performance estimation engine embeds technology process parameters, SPICE models for basic circuits, and symbolic composition equations for basic structural configurations. The paper discusses the VHDL-AMS subset for synthesis. The subset offers the composition semantics. As a result, specifications offer sufficient insight into the system structure to allow automated architecture generation. To justify the flexibility of the methodology, the paper presents results for three case studies, a signal conditioning system, a filter, and an analog to digital converter. Experiments show that constraint-satisfying designs can be synthesized in a short time, at a low cost, and without requesting broad knowledge on analog circuits.

This paper presents our experience on high-level synthesis of Σ - Δ analog to digital converters (ADC) from VHDL-AMS descriptions. The proposed VHDL-AMS subset for synthesis is discussed. The subset has the composition semantics, so that specifications offer enough insight into the system structure for automated architecture generation and optimization. A case study for the synthesis of a fourth order Σ - Δ ADC is detailed. Compared to similar work, the method is more flexible in tackling new designs, and more tolerant to layout parasitic.

This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ̿Δ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.

System level design always has a disadvantage of not possessing detailed knowledge of the communication subsystem. This is a crucial issue for system-on-chip design, where uncertainty in communication by very deep submicron effects cannot be neglected. We present a bus architecture (BA) synthesis algorithm for designing the communication subsystem of an SoC. The algorithm is part of a hardware-software codesign methodology for resource constrained embedded applications. BA synthesis includes finding the bus topology, and routing the individual buses so that various constraints, like bus length, topology complexity, potential for communication conflicts over time, are addressed. We present BA synthesis results for a network processor, and a JPEG SoC.

This paper presents a new technique for automatically creating analog circuit models. The method extracts piecewise linear models from trained neural networks. A model is a set of linear dependencies between circuit performances and design parameters. The paper illustrates the technique for an OTA circuit - an amplifier circuit widely used in filters and A/D converters for which models for gain and bandwidth were automatically generated. As experiments show, the obtained models have simple form that accurately fits the sampled points and the behavior of the trained neural networks. These models are useful for fast simulation of systems with non-linear behavior and performances.

High-level synthesis is highly demanded for managing the complexity of analog and mixed-signal system designs. However, synthesis methods are currently in their infancy. The absence of a high-level specification notation is an important limitation for the development of efficient synthesis methods. This paper presents a behavioral model and a VHDL-AMS subset for high-level synthesis of analog and mixed-signal systems. The model (named aBlox) offers a composition semantics for functionality description and an orthogonal declarative mechanism for expressing the performance requirements of a system. The model was developed after analyzing a large number of systems for telecommunication, signal processing, control engineering, and analog computing. The model expresses the meaning of: 1) analog and digital data; 2) continuous and event-driven functionality (behavior); 3) analog performance attributes; and 4) analog-digital interactions. The aBlox model serves as a foundation for defining a semantically sound VHDL-AMS subset for synthesis. Also, the VHDL-AMS subset is identified so that its constructs can be mapped to architectures of circuits. We introduce several restrictions to the VHDL-AMS instructions, such that their semantics match that of the aBlox model. To motivate the usefulness of the model and the VHDL-AMS subset, we present a case study that uses VHDL-AMS inputs.

This paper presents a methodology for high-level synthesis of continuous-time linear analog systems. Synthesis results are architectures of op-amps, sized resistors and capacitors such that their ac behavior and total silicon area are optimized. Bounds for op-amp dc gain, unity-gain frequency, input, and output impedances are found as a byproduct of synthesis. Subsequently, a circuit synthesis tool can be used to synthesize the op-amps of an architecture. The paper details the architecture generation technique. Architecture generation produces alternative architectures for a system specification using the tabu search heuristic. Its main advantages over traditional methods is that it is application independent, does not require a library of block connection patterns, and is simple to implement. The paper also discusses the hierarchical, two-step parameter optimization that guides architecture generation. Experiments showed that linear analog systems operating at low/medium frequencies (like telecommunication systems and filters) can be synthesized in a reasonably long time and with reduced effort.

This paper discusses aBlox - a specification notation for high-level synthesis of mixed-signal systems. aBlox addresses three important aspects of mixed-signal system specification: (1) description of functionality and (2) performance issues and (3) expression of analog-digital interactions. The semantics of aBlox embeds concepts and rules of a functional computational model, and uses a declarative style to denote performance elements. The paper shows some mixed-signal specifications that we developed in aBlox. Finally, we describe a high-level analog synthesis experiment that used aBlox specifications as inputs.

This paper presents a CAD methodology and a tool for high-level synthesis (HLS) of digital hardware for mixed analog-digital chips. In contrast to HLS for digital applications, HLS for mixed-signal systems is mainly challenged by constraints, such as digital switching noise (DSN), that are due to the analog circuits. This paper discusses an integrated approach to HLS and power net routing for effectively reducing DSN. Motivation for this research is that HLS has a high impact on DSN reduction, however, DSN evaluation is very difficult at a high level. Integrated approach also employs an original method for fast evaluation of DSN and an algorithm for power net routing and sizing. Experiments showed that our combined binding and scheduling method produces better results than traditional HLS techniques. Finally, DSN evaluation using the proposed algorithm can be significantly faster than SPICE simulation.

This paper presents an integrated approach to hardware software co-synthesis and HLS for design of low-power embedded systems. The main motivation for this work is that fine trade-offs between latency and power can be explored at the system level only with a detailed knowledge of used hardware resources. Integrated method was realized as a simulated annealing based solution-space exploration. Exploration is guided by Performance Models, that exactly capture the relationship between performances i.e. power consumption and latency and design decisions i.e. binding and scheduling. The proposed approach permits nor only a more accurate latency and power estimation but also the exposure of RTL-level design decisions at the system level. As a result, more effective power-latency trade-offs are possible during co-synthesis as compared to traditional task-level methods.

Summary form only given. The main challenge for any symbolic analysis method is the exponential size of the produced symbolic expressions (10/sup 11/ terms for an op amp). Current research considers two ways of handling this limitation: approximation of symbolic expressions and hierarchical methods. Approximation methods retain only the significant terms of the symbolic expressions and eliminate the insignificant ones. The difficulty, however, lies in identifying what terms to eliminate and what the resulting approximation error could be. Hierarchical methods tackle the symbolic analysis problem in a divide-and-conquer manner. They consider only one part of the global network at a time and then recombine partial expressions for finding overall symbolic formulas. Existing hierarchical methods have a main limitation in that they are not feasible for addressing networks that are built of tightly coupled blocks, i.e. operational amplifiers. The originality of our research stems from exploiting regularity aspects for addressing the exponential size of produced symbolic expressions. As a result, polynomial-size models are obtained for any network, including networks formed of tightly coupled blocks. Two kinds of regularity aspects were identified.

This paper presents a heuristic technique for automatically generating different architectures for an analog system. The AG iteratively produces various system net-lists as distinct implementations can realize the signal processing and flow in a system. Area and power for resulting net-lists are rapidly evaluated with High-Level Performance Estimator (HPE), a simplified estimation module. The AG algorithm is simple to implement. It does not require an extensive pattern library as traditional AG techniques do.

In this paper, we concentrate on aspects related to the synthesis of distributed embedded systems consisting of programmable processors and application-specific hardware components. The approach is based on an abstract graph representation that captures, at process level, both dataflow and the flow of control. Our goal is to derive a worst case delay by which the system completes execution, such that this delay is as small as possible; to generate a logically and temporally deterministic schedule; and to optimize parameters of the communication protocol such that this delay is guaranteed. We have further investigated the impact of particular communication infrastructures and protocols on the overall performance and, specially, how the requirements of such an infrastructure have to be considered for process and communication scheduling. Not only do particularities of the underlying architecture have to be considered during scheduling but also the parameters of the communication protocol should be adapted to fit the particular embedded application. The optimization algorithm, which implies both process scheduling and optimization of the parameters related to the communication protocol, generates an efficient bus access scheme as well as the schedule tables for activation of processes and communications.

This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications.We implemented this approach in the VASE behavioral-synthesis tool.The synthesis process produces a netlist of electronic components that are selected from a component library and sized such that the overall area is minimized and the rest of the performance constraints such as power, slew-rate, bandwidth, etc. are met.The gap between system level specifications and implementations is bridged using a hierarchically-organized, design-space exploration methodology.Our methodology performs a two-layered synthesis, the first being architecture generation, and the other component synthesis and constraint transformation.For architecture generation we suggest a branch-and-bound algorithm, while component synthesis and constraint transformation use a Genetic Algorithm based heuristic method.Crucial to the success of our exploration methodology is a fast and accurate performance estimation engine that embeds technology process parameters, SPICE models for basic circuits and performance composition equations.We present a telecommunication application as an example to illustrate our synthesis methodology, and show that constraint-satisfying designs can be synthesized in a short time and with a reduced designer effort.

This paper presents a complete method for automatically translating VHDL-AMS behavioral-specifications of analog systems into op amp level net-lists of library components. We discuss the three fundamental aspects, that pertain to any behavioral synthesis environment the specification language, the rules for compiling language constructs into a technology-independent, intermediate representation, and the synthesis (mapping) of representations to net-lists (topologies) of library components, so that performance constraints are satisfied. We motivate the effectiveness of the method by presenting our synthesis results for 5 examples.

We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared buses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

This paper presents a list-scheduling algorithm for graphs with data and control dependencies. We assume that tasks are partitioned between hardware resources as scheduling takes place after partitioning in our co-synthesis tool. Control dependencies are introduced by if statements, and model complementary functionalities. A detailed discussion of our algorithm is presented. Extensive experimental work shows the effectiveness of our method for generating close-to-optima schedules in short run-times.