With the emergence of all-inclusive AI/ML applications, hardware solutions, commonly known as AI-Accelerators (AIA), are now being widely adopted to emulate deep neural networks (DNN) to facilitate faster and large-scale data analytics. An AIA-chip comprises a 2D systolic array of identical processing units (PEs), registers, and glue logic. These arrays may be implemented with traditional digital logic or with analog primitives such as memristors. As the packing density of AIA-chips increases, they become vulnerable to various manufacturing defects thereby compromising yield and the accuracy of prediction. In this review article, we summarize various methods that have been recently proposed for expediting Automatic Test-Pattern Generation (ATPG) for stuck-at and transition faults in AIA-arrays. Other relevant issues such as fault-criticality, self-test, fault-recovery, and the asymmetry of fault behavior, are also discussed.

The demand for small, multifunctional electronic products with high performance is an important requirement now a days. 3-D-stacked integrated circuits (ICs) that employ through-silicon vias (TSVs) to connect multiple dies is the promising solution to meet this demand. However, TSV based interconnections invite some new problems such as TSV defects which may arise during the assembly process of 3D SIC. Therefore, defects could lead to reduced service life of 3D ICs. To overcome this problem, efficient repair solutions are needed. The popular method is to use redundant TSVs. Most of the existing TSV redundancy strategies consider uniformly distributed TSV faults and use of neighboring TSVs to be replaced by faulty TSVs. However, the presence of a defective TSV may likely create faulty TSVs in its neighboring. Due to the presence of such clustering effect, most of the TSV repair techniques are less effective. To resolve this problem, we propose an efficient and flexible TSV redundancy strategy based on diagonal routing which explores the ways to improve the existing scheme for repairing faulty TSVs by establishing additional diagonal flows in the TSV grid apart from the existing traditional flows (west to east and north to south). For this purpose, we examine the advancements of introducing diagonal flows into existing TSV architecture. We investigate the improvements in repair length due to shortening of the repair route. We also want to see whether this advancement leads to an increase in yield. This approach maximizes the use of spare TSVs to repair faulty systems, with minimal impact on area.

The development of electrostatically doped graphene PN-junctions shows promise for creating efficient low-power, high-speed circuits. In recent years, there has been a considerable interest in the synthesis of graphene PN junction logic circuits. However, existing synthesis methods lack assessment based on technology-specific cost metrics (e.g., the number of graphene PN junction gates, constant inputs), leading to insufficiently addressed design objectives. In this paper, we introduce synthesis approaches for graphene PN-junction circuits based on Sum-of-Products (SoP) and Exclusive Sum-of-Products (ESoP) function representations. Experimental results indicate that ESoP-based synthesis significantly reduces the number of graphene PN junction gates, constant inputs, and switching activity compared to SoP-based approaches. Overall, ESoP-based synthesis is deemed more suitable than SoP-based methods for designing graphene PN-junction logic circuits.

The possibility of 3D integrated circuit (3D IC) has been considered as a choice to overcome the difficulties faced by two-dimensional integrated circuits (2D IC). Several technologies exist to connect the layers in 3D IC. Among these technologies through-silicon vias (TSVs) is the promising one since it helps to reduce interconnect length, delays and power consumption. In spite of the advantages it introduces different types of defects which ultimately make an entire IC faulty. Thus, testing of TSVs is an important necessity. Depending on the timing, the testing may be of two types -pre-bond and post-bond. In pre-bond TSV testing TSVs are tested in sessions. In this paper our objective is to reduce the pre-bond TSV test sessions as much as possible, so that overall testing time decreases. To reduce test sessions we need to reduce the individual TSV testing and increase group wise TSV testing.

With extreme miniaturization of traditional CMOS devices in deep sub-micron design levels, the delay of a circuit, as well as power dissipation and area are dominated by interconnections between logic blocks. Interconnect today is causing major problems such as delay, power dissipation, and so on. In an attempt to search for alternative materials, Graphene nanoribbons have been found to be potential for both transistors and interconnects due to its outstanding electrical and thermal properties. Graphene nanoribbons provide better options as materials used for global routing trees in VLSI circuits. However, certain special characteristics of Graphene nanoribbon prohibit direct application of existing VLSI routing tree construction methods. In this article, we address this issue and propose heuristic methods for construction of Graphene nanoribbon--based minimum hybrid cost and minimum-delay Steiner trees. We compute the delays for the trees using Elmore delay approximation. Experimental results demonstrate the effectiveness of our proposed methods, which are quite encouraging.

Quantum circuits have recently been developed thanks to the global companies like IBM, Google, Microsoft and Intel. The physical realization of quantum circuits motivates to explore new areas of research. Testing of quantum circuits is one such area which needs significant attention in order to detect faulty gate operations in the circuits. To this end, first we need to identify the different types of faults that can result due to some unwanted physical failures during the implementation of the gate operations. This paper investigates those possibilities of physical failures in realizing the quantum operations and introduces a new family of fault models for quantum circuits. Experimental results include the actual number of newly proposed faults that can occur at the physical level of any quantum circuit.

The emerging technology of reversible circuits offers a potential solution to the synthesis of ultra low-power quantum computing systems. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k-CNOT), k ≥ 1. While analyzing testability issues in a reversible circuit, the missing-gate fault model is often used for modeling physical defects in quantum k-CNOT gates. In this paper, we propose a new design for testability technique for quantum reversible circuits in which the gates of a circuit are grouped into different sets and the gates from each set are attached to an additional input line via an extra control. Such arrangement makes it possible to test the gates belonging to a set separately. Our algorithm exploits the feature of many reversible circuits in which the high quantum cost gates have target on the same line and this line is devoid of any control of other gates. All these gates skip addition of extra control for testing. The proposed technique offers less quantum cost in comparison to other DFT techniques published so far.

Minimization of power dissipation of VLSI circuits is one of the major concerns of recent digital circuit design primarily due to the ever decreasing feature sizes of circuits, higher clock frequencies and larger die sizes. The primary contributors to power dissipation in digital circuits include leakage power, short-circuit power and switching power. Of these, power dissipation due to the circuit switching activity constitutes the major component. As such, an effective mechanism to minimize the power loss in such cases often involves the minimization of the switching activity. In this paper, we propose an intelligent rule-based algorithm for reducing the switching activity of the digital circuits at logic optimization stage. The proposed algorithm is empirically tested for several standard digital circuits with Synopsys EDA tool and the results obtained are quite encouraging.

With extreme miniaturization of traditional CMOS devices in deep sub-micron design levels, the delay of a circuit, as well as power dissipation and area are dominated by interconnections between logic blocks. In an attempt to search for alternative materials, Graphene nanoribbons (GNRs) have been found to be potential for both transistors and interconnects due to its outstanding electrical and thermal properties. GNRs provide better options as materials used for global routing trees in VLSI circuits. However, certain special characteristics of GNRs prohibit direct application of existing VLSI routing tree construction methods for the GNR-based interconnection trees. In this paper, we address this issue possibly for the first time, and propose a heuristic method for construction of GNR-based minimum-delay Steiner trees based on linear-cum-bending hybrid delay model. Experimental results demonstrate the effectiveness of our proposed methods. We propose a novel technique for analyzing the relative accuracy of the delay estimates using rank correlation and statistical significance test. We also compute the delays for the trees generated by hybrid delay heuristic using Elmore delay approximation and use them for determining the relative accuracy of the hybrid delay estimate.

In this article, we introduce a novel method of synthesizing symmetric Boolean functions with reversible logic gates. In contrast to earlier approaches, the proposed technique deploys a simple, regular, and cascaded structure consisting of an array of Peres and CNOT gates, which results in significant reduction with respect to the quantum cost. However, the number of circuit inputs may increase slightly when such cascades are used. In order to reduce their number, we next propose a postsynthesis optimization phase that allows judicious reuse of circuit lines. In addition to offering a cost-effective synthesis methodology, the proposed reversible logic structure supports elegant testability properties. With respect to all single or partial missing gate faults (SMGFs and PMGFs), or repeated gate faults (RGFs) in such an n -input circuit module, we show that it admits a universal test set of constant cardinality (=3) for any value of n . Thus, considering both the cost and testability issues, this approach provides a superior option for synthesizing symmetric functions compared to existing designs.

The emerging technology of reversible circuits offers a potential solution to the synthesis of ultra low-power quantum computing systems. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k-CNOT), k ⩾ 1. While analyzing testability issues in a reversible circuit, the missing-gate fault model is often used for modeling physical defects in quantum k-CNOT gates. In this paper, we propose a new design-for-testability (DFT) technique for quantum reversible circuits that deploys bit-swapping using Fredkin gates. It is shown that in an (n x n) circuit implemented with k-CNOT gates, addition of only two extra inputs along with a few Fredkin gates yields easy testability in the circuit. The modified design admits a universal test set of size (n + k + 2) that detects all detectable missing gate faults in the original circuit, where k is the maximum number of controls used among all k-CNOT gates. The DFT overhead in terms of quantum cost is also much less compared to previous approaches.

Quantum reversible circuit is a new emerging technology attracting the researchers. A reversible circuit is composed of reversible gates only. A reversible Toffoli gate has two components - the control and the target. The missing gate fault model is used for modelling defects in quantum k-CNOT gate. This work introduces Boolean Difference technique for deriving the test set for detecting all faults in a reversible circuit implemented with k-CNOT gates. Then a optimizing algorithm is used to derive optimal test set to detect all possible partial missing faults in a circuit.

Reversible logic synthesis has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate faults (MMGF), are likely to be more suitable for modeling defects in quantum k-CNOT gates. This work proposes an algorithm for deriving the test set for the detection of all single missing gate faults in a reversible circuit implemented with k-CNOT gates. Instead of deriving test set directly for the detection of missing gate faults, a Boolean generator is developed by Boolean difference method to derive the test set and to detect all the single missing gate faults of a reversible circuit. Experimental results on some benchmark circuits are also reported.

In this paper, we introduce a new method to realize symmetric Boolean functions with reversible logic based on unate decomposition. In contrast to earlier synthesis methods, our solution uses a simpler circuit structure of reversible gates, which enables a significant reduction with respect to quantum cost. The resulting design offers an improved solution to reversible synthesis of symmetric Boolean functions.

Logic synthesis of reversible circuits has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. This article presents an efficient algorithm to derive an optimal test set (OTS) for detection of multiple missing-gate faults in a reversible circuit implemented with k-CNOT gates. It is shown that the OTS is sufficient to detect all single missing-gate faults (SMGFs) and all detectable repeated gate faults (RGFs). Experimental results on some benchmark circuits are also reported.

Testing of bridging faults in a reversible circuit is investigated in this paper. The intra-level single bridging fault model is considered here, i.e. any single pair of lines, both lying at the same level of the circuit, may be assumed to have been logically shorted in order to model a defect. For an (n · n) reversible circuit with d levels realized with simple Toffoli gates, the time complexity of the test generation procedure is O(nd2 log2n). A test set of cardinality O(d log2n) is found to be sufficient for testing all such detectable faults. A minimal test set can also be easily derived by using the concept of test equivalence.

Testable design for detecting stuck-at and bridging faults in Programmable Logic Arrays (PLAs) based on Double Fixed-Polarity Reed-Muller Expression (DFPRM) is proposed. DFPRMs are generalized expressions of FPRM. It has advantages of compactness and easy testability. The EXOR part in the proposed design is implemented with tree structure that admits a universal test set. For an n-variable function, this design can be tested by (2n+8) test vectors, which are independent of the function and the circuit-under-test (CUT). Excepting a few intergate bridging faults in the EXOR-tree, it detects all other single bridging (both OR-and AND-type) and all single stuck-at faults. This tree based implementation reduces circuit delay significantly compared to cascaded EXOR-part.

This paper reports an efficient state encoding scheme for synthesis of large FSMs with enhanced BIST quality. A metric, referred to as degree-of-freedom (DOF) [5] in FSM states has been employed to quantify the BIST quality. Analysis of DOF enables efficient encoding of FSM states and gives solution to the problem of handling unreachable/ hard-to-exit/ hardto- reach state codes of an FSM. The synthesis of a large FSM is realized through decomposition. DOF analysis for the individual component sub-FSM states is done to reduce the complexity of synthesis. A scheme is proposed for encoding the sub-FSM states that significantly improves testability of the synthesized resultant FSM, displaying the terminal behavior as the original FSM.

The paper uses the concept of time expansion model (Innoue et al., 2000) to find the test generation for acyclic sequential circuits. It identifies a class of sequential circuits called as max-testable sequential circuits, where test generation can be obtained using a combinational test generator with the capability of detecting multiple faults on a kernel of combinational circuit. Any acyclic sequential circuit without hold registers belongs to this class. For the sequential circuits having hold registers, a subset of such circuits is found to be belonged to max-testable class. The paper also suggests an algorithm to find such class of circuits.

A technique for implementing totally symmetric Boolean functions using hierarchical modules is presented. First, a simple cellular module is designed for synthesizing unate symmetric functions. The structure is universal, admits a recursive design and uses only 2-input AND-OR gates. General symmetric functions are then realized following a unate decomposition method. The synthesis procedure guarantees complete and robust path-delay fault testability in the circuit. Experimental results on several symmetric functions reveal that the hardware cost of the proposed design is low, and the number of paths in the circuit is reduced significantly compared to those in earlier designs. Results on circuit area and delay for a few benchmark examples are also reported.

This paper presents an efficient BIST solution for VLSI circuit testing based on GF(2p) CA (Cellular automata on an extended Galois Field). The novel architecture of GF(2p)) CA permits the BIST structure to be highly customized to the circuit under test (CUT). A methodology has been proposed to optimize the design of GF(2p) CA structure to maximize the fault coverage in a given CUT. In addition, an innovative scheme based on logic folding is presented to reduce the BIST overhead and make it more effective for large circuits.

Designing a BIST structure for sequential circuits is rather a complex problem as some states remain unreachable and some act as the sink under any input sequence. This paper reports an efficient scheme to provide uniform mobility, referred to as degree of freedom, in a sequential machine by enhancing the reachability as well as the emittability of the states. The uniform mobility of states ensures higher fault efficiency in a BIST structure of the circuit. Moreover, as a non-scan scheme, the technique provides lower test application time and at-speed testing.

We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e., the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can also be performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.

Design of irredundant and fully testable nonscan sequential circuits is a major concern of logic synthesis, as the presence of undetectable faults may render an ATPG intractable. This paper outlines some intriguing properties of isomorph faults, which are sequentially undetectable as well as redundant. An isomorph fault in a sequential circuit makes the state diagram of the faulty machine identical to that of the fault-free machine under certain renaming of states. Examples of reduced sequential machines whose circuit realization is combinationally irredundant, but isomorph-redundant, are hard to construct and very little is known about them. In this paper, many curious examples of such sequential circuits are presented wherein a single stuck-at fault causes isomorphic faulty machines. An infinite family of such circuits may, in fact, be constructed. It is shown that even two-level irredundant circuits obtained by synthesis tools may admit isomorph-redundancy under multiple stuck-at faults. Various classifications and related properties of isomorph faults are also reported. These results reveal new insight and understanding of redundancy in sequential circuits.

A new technique of synthesizing totally symmetric Boolean functions is presented that achieves complete robust path-delay fault testability. We show that every consecutive symmetric function can be expressed as a logical composition (e.g., AND, NOR) of two unate symmetric functions, and the resulting composite circuit can be made robustly path-delay fault testable, if the constituent unate functions are synthesized as two-level irredundant circuits. Nonconsecutive symmetric functions can also be synthesized by decomposing them into a set of consecutive symmetric functions. The circuit cost of the proposed design can further be reduced by a novel algebraic factorization technique based on some combinatorial clues. The overall synthesis guarantees complete robust path-delay fault testability, and can be completed in linear time. The results shows that the proposed method ensures a significant reduction in hardware, as well as in the number of paths, which in turn, reduces testing time, as compared to those of the best-known earlier methods.

Design of an adaptive built-in-self-test (BIST) scheme for detecting multiple stuck-open faults in a CMOS complex cell is proposed. The test pattern generator (TPG) adaptively generates a subset of single-input-change (SIC) test pairs based on the past responses of the circuit under test (CUT). The design is universal, i.e., independent of the structure and functionality of the CUT. The average length of the test sequence (TS) in an n-input CUT is (n+1).2/sup n/ [(n+1).2/sup n-1/] in a fault-free [faulty] condition. The response analyzer (RA) is also simple to design. All robustly testable multiple stuck-open faults (occurring simultaneously both in n- and p-parts) can be detected using the proposed BIST scheme.

As opposed to scan schemes, a non-scan DFT allows at-speed testing. This paper suggests three techniques on non-scan DFT of sequential circuits. The proposed techniques guarantee 100% fault efficiency by using a combinational ATPG tool. In all techniques, an additional circuit called CRIS is proposed to reach unreachable states on the state register of a machine. The second and third techniques use an additional hardware called differentiating logic (DL), that uniquely identifies a state appearing in a state register. The design of DL is universal, i.e., not dependent on the circuit structure. Hardware overhead of DL and CRIS is lower than that of full scan. Test generation and application time are found to compare favorably with those of earlier designs.

A new concept of interchangeability of boolean functions under stuck-at faults in logic circuits is introduced in this paper. Two boolean functions F/sub 1/ and F/sub 2/ are said to be interchangeable if there exist two irredundant combinational networks N/sub 1/ and N/sub 2/ realizing F/sub 1/ and F/sub 2/ respectively, such that under some single/multiple stuck-at fault f/sub 1/(f/sub 2/) in N/sub 1/(N/sub 2/), the faulty network realizes F/sub 2/(F/sub 1/). It has been shown that an infinite family of such interchangeable pairs of functions exist, and they play an important role in determining several new types of redundancy in combinational and sequential circuits.

An isomorph fault in a sequential circuit makes the state diagram of the faulty machine identical to that of the fault-free machine, under the renaming of states. However, no example of a reduced sequential machine whose circuit realization is combinationally irredundant but isomorph-redundant, is yet known. This paper shows that an infinite family of such circuits can be constructed with isomorph-redundancy. Isomorph faults are then classified into various types. Their properties reveal new insight and understanding of redundancy in sequential circuits.

Design of irredundant and fully testable non-scan synchronous sequential circuits is a major concern of logic synthesis. The presence of sequentially redundant faults (SRFs) makes test generation complicated, and hence their removal is highly desirable to enhance testability. In this paper, we propose a novel technique for testable design which is significantly different from scan designs, or testability-targeted synthesis approaches. We show that addition of some extra logic and a control input to an arbitrary sequential circuit can eliminate all equivalent and isomorph SRFs, even under the multiple stuck-at-fault model. Every pair of states can easily be distinguished in the modified machine, thus making it easily testable. The augmented logic is also universal, i.e., independent of the state diagram or the circuit structure of the given machine. Analysis of benchmark circuits reveals that its hardware overhead is much less compared to that of full scan design.