The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

The traditional screening method of using non-layout aware port level fault based scan ATPG tests, traditional toggle patterns, and IDDQ based stress patterns for digital logic has been an industry standard for the last few decades to achieve very low outgoing Defective Parts Per Million (DPPM) integrated circuits in the semiconductor industry. In addition to catching defects that already exhibit catastrophic behavior directly after manufacturing, latent defects need to be accelerated through stress so that they can also be caught before the affected parts are sold. As the FinFET technology process nodes keep shrinking to single digits (especially at 7nm and below), the challenges of creating and measuring transistor level stress patterns for SoC designs increases exponentially. This paper will present the motivation, need, and details of on-going research on Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM generation and targeted scan stress pattern creation to continue achieving zero defect automotive chips in single-digit FinFET process nodes. This new flow enabled quantification of 3 new defect-oriented stress coverage metrics and highlighted the inadequacy of the current toggle coverage metric that overestimates the actual stress coverage achieved.

Mission-critical systems often require some testing to occur while the system is running. In many cases, this involves taking parts of the system off-line temporarily to apply the tests. However, hazards that occur during regular processor execution require the addition of stall cycles to maintain program correctness. These stall cycles generally perform no other function. In this paper, we focus on testing the ALU during those stall cycles to identify new errors or defects that arise during program execution due to aging and increased temperature that may slow down the circuitry or cause permanent defects. We investigate the time to detection of a fault (both stuck-at and transition) that may have caused silent data corruption. In addition, we identify the relationship between the programs running and the list of functional faults and how this impacts the test set length. Finally, we discuss area and performance impacts for the physical implementation of the approach.

Abstract Test sets that target standard fault models may not always be sufficient for detecting all defects. To evaluate test sets for the detection of unmodeled defects, n-detect test sets (which detect all modeled faults at least n times) have previously been proposed. Unfortunately, n-detect test sets are often prohibitively long. In this paper, we investigate the ability of shadow flip-flops connected into a MISR (Multiple Input Signature Register) to detect stuck-at faults fortuitously multiple times during scan shift. We explore which flip-flops should be shadowed to increase the value of n for the least detected stuck-at faults for each circuit studied. We then identify which circuit characteristics are most important for determining the cost of the MISR needed to achieve high values of n. For example, circuits that contain a few flip-flops with upstream fault cones that cover a large percentage of all faults in the circuit can often achieve high n-detect coverage fortuitously with a low-cost MISR. This allows a DFT engineer to predict the viability of this MISR-based approach early in the design cycle.

Excessive test power can cause multiple issues at manufacturing as well as during field test. To reduce both shift and capture power during test, we propose a DFT-based approach where we split the scan chains into segments and use extra control bits inserted between the segments to determine whether a particular segment will capture. A significant advantage of this approach is that a standard ATPG tool is capable of automatically generating the appropriate values for the control bits in the test patterns. This is true not only for stuck-at fault test sets, but for Launch-off-Capture (LOC) transition tests as well. It eliminates the need for expensive post processing or modification of the ATPG tool. Up to 37% power reduction can be achieved for a stuck-at test set while up to 35% reduction can be achieved for a transition test set for the circuits studied.

Embedded instruments are responsible for aiding in a wide range of tasks engineers must perform on integrated circuits (ICs), including testing, debugging, and analysis. The IEEE 1687 IJTAG standard provides efficient access to these instruments without specifying proper measures to establish access control to sensitive data on the ICs. Previously, the impact of this exposure was generally limited to local attackers obtaining proprietary information from a device to which they have physical access. However, newer endeavors such as IEEE P1687.1 aim to extend IJTAG access to other serial ports, broadening the attack surface to additional local and remote attackers alike. In order to protect these components from local and remote attackers, we describe a lightweight and low-cost protocol to authenticate users that offers solutions to access control, key distribution, and insecure secrets stored on-chip.

The term CyberSecurity means many different things to many people - some think of data security, some think of identity protection, some think of intrusion attacks on the internet or USB ports. In reality, CyberSecurity represents any type of attack on computing machines. One of the type of attacks that is often overlooked are attacks by the supply chain to inject malfeasant circuitry into semiconductor devices as they are made. This is the one aspect of Design-for-Security and Design-for-Trust that is usually ignored. This innovative practice session will highlight three talks on hardware CyberSecurity attacks and defenses from both industry and academia.

During scan shift, high simultaneous toggling of sequential logic on a System-on-Chip (SoC) can result in increased Power Supply Noise (PSN). The problem gets exacerbated when the switching logic is present in neighboring blocks on the SoC that share the same power rails. To solve this voltage noise problem, we propose a new graph coloring algorithm that assigns staggered shift-clocks to the SoC blocks such that (i) no two neighboring blocks use the same shift-clock (to reduce local hotspots), and (ii) the number of scan cells toggling per shift clock is equalized (to reduce global noise). The new algorithm takes into account the total number of scan flops per block, and the assignment of stagger clocks is done such that the total number of scan flops that toggle per staggered shift-clock is balanced at the power rail-level. Using silicon data from NVIDIA's recently taped-out chips, we show that the stagger assignment using our new algorithm results in at 70% PSN reduction compared to conventional scan shift and around 21% PSN reduction compared to the previously proposed stagger assignment solutions.

The JTAG port is a well-known vector for attacks that attempt to gain access to a chip's internal circuitry. Such attacks may modify or extract proprietary data and can lead to misconfigured chips and IP theft. This paper uses a hash-based signature created through the history of the data shifted into and out of a device via IJTAG to provide a measure of continuous authentication and guard against malicious modification of data sent to/from the device under test. The proposed approach also provides evidence of tampering through the JTAG port as unauthorized access attempts will change the recorded signature.

To meet high performance requirements, System-on-Chips (SoCs) may include multiple replicated copies of functional embedded cores. To reduce the time required to apply identical test data to these replicated cores, we designed a novel broadcast network architecture that harnesses IEEE Std 1687 (IJTAG). Our architecture provides highly configurable broadcast/multicast and daisy modes, allowing one to selectively apply test data to any combination of embedded modules. The broadcast network is also scalable, supports hierarchical network architectures, and can be easily interfaced with other IJTAG-compliant test architectures. The new broadcast network provides a trade-off between network reconfigurability and the programming overhead of the network reconfiguration bits. It saves up to 70–80% of the test time in a sample test data broadcast scenario compared to serial and prior broadcast IJTAG networks. Compared to a serial network, our broadcast network requires only one extra reconfiguration bit.

Variations in test fallout during the testing of high-volume devices may arise from a variety of sources. Some of these, such as process variations and design marginalities, correspond to actual problems with the devices being tested and should lead to those devices being scrapped and/or changes being made to the fabrication process. However, in other cases, the test equipment itself could be unreliable or require an alteration in the test procedure, leading to either bad chips tested as good or good chips failing the test. Thus, a real-time monitor of the yield data and the quality of the test result data is essential for assuring high test quality and for ruling out possible issues arising from the test hardware. The real-time monitoring of the yield can save the chip manufacturer time and cost by finding issues with the testing system in the early stages of production (or as soon as those issues arise), avoiding the scrapping of good devices, and preventing the penalty of sending bad units to the customer. In this paper, a low-cost algorithm to monitor the yield of multiple test sites is presented. The method is capable of being implemented in the test program of a standard tester, and the ability of the approach to provide early warning of test site problems during wafer test is demonstrated through an industrial case study.

The number of on-chip embedded instruments required for testing, debugging, and monitoring integrated circuits (ICs) has increased dramatically. The IEEE 1687 (IJTAG) standard can allow efficient access to these embedded instruments by dynamically reconfiguring the scan chain using Segment Insertion Bits (SIBs). Unfortunately, instruments that require a large amount of test data and several accesses during test mode still result in long test times when the test data is shifted through the scan path serially. To provide high bandwidth access to the embedded instruments, we describe a SIB-based Parallel-IJTAG network architecture that can significantly reduce test times. The SIB programming access time overhead is equal to that of the corresponding serial network. Different ways of implementing Parallel-SIBs (P-SIBs) and the security implications of a Parallel-IJTAG network are explored. We show that despite the increased bandwidth of the scan path, the security provided by Locking SIBs can be maintained in a parallel network. For example, the expected amount of time for successful random brute force attacks on Locking Parallel SIBs of sufficient key sizes is over 12,000 years.

Probabilistic approaches to the detection of untargeted defects, such as n-detect and standard LBIST (logic built-in-self-test), generally suffer from the need to apply very long test sets to achieve good coverage. However, more targeted approaches that attempt to explicitly model new types of defects, such as cell-aware faults, so that they can be deterministically detected may also lead to unacceptably long test sets. Generally, when tests are applied to circuits that contain scan chains, test results are only captured once the entire pattern has been shifted in and the desired deterministic pattern has been applied. Intervening shift cycles serve only as overhead. This is done because capturing data in the circuit's scan flip-flops during scan shift would destroy the pattern being shifted in. However, if data is captured in shadow flops in a MISR instead, those shift cycles could be used to obtain additional fault coverage. In this paper, we investigate the ability of the intervening shift cycles to achieve high static cell-aware fault coverage using only the test patterns generated to detect stuck-at faults. We also investigate reducing the number of shadow flops required. Our results show that high cell-aware coverage is achievable even when only a stuck-at test set is applied — in some cases equal to the coverage obtained by a dedicated cell-aware test set.

IEEE 1149.1-based top-level access to IEEE 1500-compliant IP cores is commonly used in industrial designs as the underlying infrastructure to provide test access, control, instrumentation, and ease of use. Validating the test infrastructure and its usage in the early design stages is critical to the success of the project. The new Internal Joint Test Action Group (IJTAG or IEEE 1687-2014) standard is a valuable component of this test infrastructure and is designed to promote efficient embedded instrument access. This paper describes one of first comprehensive applications of an IJTAG-based method to a state-of-the-art server microprocessor design from specification to production. We leveraged IJTAG to automate design modeling, enable faster and more advanced verification, and optimize manufacturing test access. In this work, we demonstrate a very high degree of optimization and automation, which is cost-efficiently enabled by IJTAG, and goes beyond the capabilities of typical in-house IJTAG-like system, currently in use in industry.

Today's chips often contain a wealth of embedded instruments, including sensors, hardware monitors, built-in self-test (BIST) engines, etc. They may process sensitive data that requires encryption or obfuscation and may contain encryption keys and ChipIDs. Unfortunately, unauthorized access to internal registers or instruments through test and debug circuitry can turn design for testability (DFT) logic into a backdoor for data theft, reverse engineering, counterfeiting, and denial-of-service attacks. A compromised chip also poses a security threat to any board or system that includes that chip, and boards have their own security issues. We will provide an overview of some chip and board security concerns as they relate to DFT hardware and will briefly review several ways in which the new IEEE 1687 standard can be made more secure. We will then discuss the need for an IEEE Security Standard that can provide solutions and metrics for providing appropriate security matched to the needs of a real world environment.

3-D die-stacks hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3-D stack are leading to yield issues and slowing the large scale manufacturing of these devices. In many cases, a single defective die will kill the entire stack. To help mitigate this issue, we explore the possibility of repairing a stack that contains a defective die by utilizing an field programmable gate array (FPGA) that has already been included in the stack for other purposes, such as performance enhancement. Specifically, we propose bypassing the defective portion of a nonprogrammable die by replacing the defective functionality with functionality on the FPGA. In this paper, we discuss what additional logic must be added to an Application-Specific Integrated Circuit (ASIC) die to allow such a bypass to occur. We then show through detailed simulation of a 2.5-D Xilinx FPGA how bypassing of logic can be achieved and throughput maintained even when the two different dies involved operate at different frequencies. Finally, we explore the performance of this technique in a superscalar, out-of-order processor, where different functional units are marked for replacement. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the FPGA can allow us to regain performance even when the latency of the units in the FPGA is longer than that of the original defective copy.

Today's chips often contain a wealth of embedded instruments and data, including sensors, hardware monitors, built-in self test (BIST) engines, and chip IDs, among others. IEEE P1687 was specifically designed to provide access to such instruments in an efficient manner, and some companies are already implementing the proposed standard on their chips. However, while instruments provide valuable information and features to authorized users who need to harness them for test, debug, diagnosis, and possibly counterfeit detection, it may be desirable to restrict unauthorized access to certain instruments through the P1687 network. Previous work proposed replacing some of the segment insertion bits (SIBs), which add scan path segments in a P1687 network, with locking SIBs (LSIBs). LSIBs use the data that is naturally scanned through the network as keys to hide instruments from attackers. However, that previous work did not investigate many of the techniques and structures that can be used to significantly increase the time an attacker is likely to need to unlock LSIBs and gain access to hidden instruments. In this work, we explore some of these techniques and show how simple modifications to a P1687 network protected with LSIBs can significantly increase the difficulty an attacker faces in attempting to access protected instruments.

Circuit boards are especially vulnerable to security attacks. Many routes and pins can be probed directly. Other pins may be controlled and observed through the JTAG boundary scan port. The JTAG port may also provide access to each chip's internal scan chains. Furthermore, modern chips may include embedded instruments that can be accessed through the chip's JTAG port and an internal IEEE P1687 scan network. If accessed by an attacker, these instruments may allow data to be leaked from the chips themselves or allow the attacker to drive other chips on the board. Finally, FPGA firmware is often stored in on-board memories and must be protected to prevent IP theft. In this paper, we describe some of the security issues facing boards. We then describe new chip access protocols that harness the use of licensed software and locking segment insertion bits (LSIBs) for secure Chip ID extraction. These methods enable authorized access while helping to prevent unauthorized access and counterfeiting of chips and IP on the board.

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IEEE P1687 is a valuable tool for accessing on-chip instruments during test, diagnosis, debug, and board configuration. However, most of these instruments should not be available to an end user in the field. We propose a method for hiding instruments in a P1687 network that utilizes a “locking” segment insertion bit (LSIB) that can only be opened when pre-defined values, corresponding to a key, are present in particular bits in the chain. We also introduce “trap” bits, which can further reduce the effectiveness of brute force attacks by permanently locking an LSIB when an incorrect value is written to the trap's update register. Only a global reset will allow the LSIB to become operable again. In this paper, we investigate the cost and effectiveness of LSIBs and traps in several different configurations and show that these relatively small modifications to the P1687 network can make undocumented instrument access exceedingly difficult.

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Power supply noise (PSN) has become a critical issue during high-quality at-speed testing. Discrepancies between the circuit's switching activity during functional and test mode can cause overtesting and lead to yield loss. Alternatively, reduced PSN effects around critical paths can result in undertesting the chip, causing test escapes. To achieve a high-quality at-speed test, it is necessary to solve these problems simultaneously. Our previous work introduced a noise index model (NIM), which can be used to predict the mismatch between expected and real path delays. This paper quantitatively investigates and compares NIM values for critical paths during functional and test mode. We then propose a test pattern modification method that harnesses the NIM. The method fills a subset of the don't care bits in partially specified test vectors such that the worst observed functional NIM for the targeted critical path is replicated during test mode.

As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection techniques, including logic implication-based checker hardware, are capable of detecting at least some of these errors as they occur. However, recovery may be expensive, and the underlying problem may lead to multiple failures of a core over time. In this article, we will investigate the diagnostic capability of logic implications to identify possible failure locations when an error is detected online. We will then utilize this information to select a highly efficient test set that can be used to effectively test the identified suspect locations in both the failing core and in other identical cores in the system.

We propose using logic implications as a source of online diagnostic data for on-chip test set selection by taking advantage of their ability to automatically identify a restricted set of faults as the potential cause of an observed error. This information will be used to dynamically choose a test set to detect systematic latent defects or wear out in a multi core system.

Obtaining fault coverage information for functional input sequences is often very difficult. Although many simulation-based techniques have been proposed, they are generally computationally expensive, and if the input sequence changes, new expensive simulations must be run. In this paper, we propose a new type of hardware monitor for the probabilistic determination of how many times a fault was likely to have been covered during functional test or program execution. In addition to providing coverage information for functional test sequences - even those that have never been simulated - these monitors can also be used to determine the relative criticality of faults for the applications a user is running in real time. Thus, in the future, this method has the potential to provide new dynamic optimization capabilities for on-chip field testing.

We present a new method to identify multi-site implications that can significantly increase the fault coverage of error-detecting hardware without increasing the area overhead. This method intelligently divides the input space about the functions of internal circuit sites and finds new valuable implications that can share gates in checker logic.

As CMOS technology continues to scale, the accurate prediction of silicon timing through the use of pre-silicon modeling and analysis has become especially difficult. These timing mismatches are important because they make it hard to accurately design circuits that meet timing specifications at first-silicon. Among all the parameters leading to the timing discrepancy between simulation and silicon, this paper studies the effect of dynamic IR-drop on the delay of a path. We propose a noise index model, NIM, which can be used to predict the mismatch between expected and real path delays. The noise index considers both the proximity of switching activity to the path and physical characteristics of the design. To evaluate the method, we performed silicon measurements on randomly selected paths from an industrial 65 nm design and compared these with Spice simulations. We show that a very strong correlation exists between the noise index model and the deviations between simulations and silicon measurements.

In this paper, we propose the use of logic implications to enhance online error detection capabilities and to improve the testing efficiency of an integrated circuit. These logic implications are implemented in hardware and help to verify that expected invariant circuit relationships are satisfied during field operation. Thus, any implication violation will indicate the presence of an error due to some faulty circuit behavior. In addition, checking these logic implications in hardware will create additional circuit outputs, which may be useful for compacting $n$-detect test sets. Our results show that logic implications can provide significant error detection and test pattern count reduction with very limited hardware overhead.

When testing resources are severely limited, special attention must be paid to critical faults so that important or frequent field failures arising from test escapes can be minimized. We present a new algorithm to optimize test sets that considers the criticality of potential undetected defects throughout the testing process and dramatically reduces the criticality of test escapes.

Power dissipation in digital circuits during scan-based test is generally much higher than that during functional operation. Unfortunately, this increased test power can create hot spots that may damage the silicon, the bonding wires, and even the package. It can also cause intensive erosion of conductors-severely decreasing the reliability of a device. Finally, excessive test power may also result in extra yield loss. To address these issues, this paper first presents a detailed investigation of a benchmark circuit's switching activity during different modes of operation. Specifically, the average number of transitions in the combinational logic of a benchmark circuit during scan shift is found to be approximately 2.5 times more than the average number of transitions during the circuit's normal functional operation. A DFT-based approach for reducing circuit switching activity during scan shift is proposed. Instead of inserting additional logic at the gate level that may introduce additional delay on critical paths, the proposed method modifies the design at the register transfer level (RTL) and uses the synthesis tools to automatically deal with timing analysis and optimization. Our experiments show that significant power reduction can be achieved with very low overhead.

This paper investigates the use of logic implication checkers for the online detection of errors. A logic implication, or invariant relationship, must hold for all valid input conditions; therefore, any violation of this implication will indicate an error due to an intermittent fault. Techniques are presented to efficiently identify the most useful logic implications to include in checker hardware such that the probability of error detection is maximized while minimizing the additional hardware and delay overhead. Results show that significant error detection is possible-even with only a 10% area overhead-while minimizing impact on delay and power.

Ensuring reliable computation at the nanoscale requires mechanisms to detect and correct errors during normal circuit operation. In this paper we propose a method for designing efficient online error detection schemes for circuits based on the identification of invariant relationships in hardware. More specifically, we present a technique that automatically identifies multi-cycle gate-level invariant relationships-where no knowledge of high-level behavioral constraints is required to identify the relationships-and generates the checker logic that verifies these implications. Our results show that cross-cycle implications are particularly useful in discovering difficult-to-detect errors near latch boundaries, and can have a significant impact on boosting error detection rates.

As the complexity of integrated circuits has increased, so has the need for improving testing efficiency. Unfortunately, the types of defects are also becoming more complex, which in turn makes simple approaches for testing inadequate. Using n-detect testing can improve detect coverage; however, this approach can greatly increase the test set size. In this proof-of-concept paper we investigate the use of logic implication checkers, inserted in hardware, as an aid in compacting n-detect test sets. We show that checker hardware with minimal area overhead can reduce test set size by up to 25%. In addition, this implication checker can serve a dual purpose for online error detection.

In this paper, we investigate the use of logic implications for the online detection of intermittent faults and hard-to-detect manufacturing defects. We present techniques to efficiently identify the most powerful circuit implications that can be checked for violations so that the fraction of errors detected can be maximized while minimizing the additional hardware overhead. Importantly, our approach does not require re-synthesis of the targeted logic; the checker logic is added off the critical path and is run in parallel with the regular control logic. Trade-offs can be easily made between additional coverage of errors and additional area overhead. Our results show that significant error detection is possible - even with only a 10% area overhead.

Power consumption during scan-based test becomes a concern in nanometer technologies. Previous test power reduction techniques that insert additional logic in gate-level circuits may result in timing violations. In this paper, we show that the problem can be solved at the RTL instead so that the timing and area constraints will be handled automatically by synthesis tools. Using a signal probabilistic approach proposed previously, we identify power-sensitive scan cells at the prototyping gate level, and we map these cells to their corresponding signal/variable bits at the RT-level. Additional RTL code is added to freeze these power- sensitive bits in order to reduce scan shift power consumption. Experimental results on ITC99 benchmarks show that on average more than 22% power reduction can be achieved when we only freeze the top 1% of power-sensitive bits at RTL. The flow is more practical in terms of timing closure than doing the same at the gate-level.

Traditionally, test set quality has been estimated through fault coverage. However, even with 100% fault coverage, some defects may escape the testing process - making defect level a more accurate estimate of the quality of test. However, even the defect level may not truly capture the reliability experience of the customer. Specifically, different undetected defects will produce different failure rates in the user's environment. Depending on the user's application, this may mean the difference between a part that is acceptable and never fails, one that rarely fails and can be tolerated, and one that experiences frequent, catastrophic failures. This paper explores the effect of circuit functionality and a user's application on the field failure rates that result from various faults and surrogate defects. We then propose a simple optimization procedure to create test sets that significantly reduce the field failure rates of test escapes without significantly increasing (and sometimes even decreasing) the final defect level.

Fortuitous detection increases with multiple site observations and good excitation balance. However, this increases test data volume. The authors investigate weighted random patterns generated with partial fault targeting and show that they may be equally or more effective at fortuitous detection than an ATPG set with the same minimal site observations.

Major sources of transient errors in microprocessors today include noise and single event upsets. As feature sizes and voltages are reduced to create faster, more efficient, and computationally more powerful processors, these errors will increase significantly. We show that (contrary to conventional wisdom) error correction codes (ECC) can be efficiently utilized to handle these errors as instructions are being processed through the microprocessor pipeline. We will analyze some of the tradeoffs involved in a hardware implementation of ECC for the instruction queue with respect to performance, power, area, and reliability. Specifically, for an environment with high error rates, we show that we can correct all single bit errors with a negligible drop in performance. Our approach can be generalized to other data structures within the microprocessor, including the register file and reorder buffer.

Dynamic defects are less likely to be fortuitously detected than static defects because they have more stringent detection requirements. We show that (in addition to more site observations) balanced excitation is essential for detection of these defects, and we present a metric for estimating this degree of balance. We also show that excitation balance correlates with the parameter /spl tau/ in the MPG-D defective part level model.

In previous work, we have shown that optimizing the number of site observations leads to more defect detection. However, for increasingly difficult defects, optimizing patterns for balanced random excitation also enhances test effectiveness. We can also reduce the effect of undetected defects by choosing tests that minimize the likelihood of field failures.

In conventional delay testing, the test clock is a single pre-defined parameter that is often set to be the same as the system clock. This paper discusses the potential of enhancing test efficiency by using multiple clock frequencies. The intuition behind our work is that for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out the potential defective chips. Then, by using a smarter test clock scheme and combining with a second set of AC delay patterns, the overall quality of AC delay test can be enhanced while the cost of including the second pattern set can be minimized. We demonstrate these concepts through analysis and experiments using a statistical timing analysis framework with defect-injected simulation.

Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of each fault site lead to increased test set size and require more tester memory. In this paper we propose a new ATPG algorithm to find a near-minimal test pattern set that detects faults multiple times and achieves excellent defective part level. This greedy approach uses 3-value fault simulation to estimate the potential value of each vector candidate at each stage of ATPG. The result shows generation of a close to minimal vector set is possible only using dynamic compaction techniques in most cases. Finally, a systematic method to trade-off between defective part level and test size is also presented.

In conventional delay testing, two types of tests, transition tests and path delay tests, are often considered. The test clock frequency is usually set to a single pre-determined parameter equal to the system clock. This paper discusses the potential of enhancing test effectiveness by using multiple test sets with multiple clock frequencies. The two intuitions motivating our analysis are 1) multiple test sets can deliver higher test quality than a single test set, and 2) for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out potentially defective chips. Hence, by using multiple test sets, the overall quality of AC delay test can be enhanced, and by using multiple-clock schemes the cost of adding the additional pattern sets can be minimized. In this paper, we analyze the feasibility of this new delay test methodology with respect to different combinations of pattern sets and to different circuit characteristics. We discuss the pros and cons of multiple-clock schemes through analysis and experiments using a statistical delay evaluation and delay defect-injected framework.

Uses data collected from benchmark circuit simulations to examine the relationship between the tests which detect stuck-at faults and those which detect bridging surrogates. We show that the coefficient of correlation between these tests approaches zero as the stuck-at fault coverage approaches 100%. An enhanced version of the MPG-D model, which is based upon the number of detections of each site in a logic circuit, is shown to be superior to stuck-at fault coverage-based defective part level prediction. We then compare the accuracy of both predictors for an industrial circuit tested using two different test pattern sequences.

Predicting the final value of the defective part level after the application of a set of test vectors is not a simple problem. In order for the defective part level to decrease, both the excitation and observation of defects must occur. This research shows that the probability of exciting an as yet undetected defect does indeed decrease exponentially as the number of observations increases. In addition, a new defective part level model is proposed which accurately predicts the final defective part level (even at high fault coverages) for several benchmark circuits and which continues to provide good predictions even as changes are made an the set of test patterns applied.

If many potential defects exist at each site in an integrated circuit, then as the number of applied test patterns increases, the number of defects which remain undetected decreases monotonically. Modeling this rate of decline in defective part level is a non-trivial problem. We show that the number of times each site is observed serves as a significantly superior basis for modeling this phenomenon when contrasted with the number of faults detected. This "site observation-based" predictor not only increases the accuracy of defective part level prediction, it also provides the first quantitative method for comparing the effectiveness of various ATPG strategies to reduce the defective part level.

For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective part level can be estimated based upon surrogate detection when test patterns target stuck-at faults in the circuit. For the first time, test pattern generation techniques that attempt to maximize non-target defect detection have been used to test a real, 100% scanned, commercial chip consisting of 75 K logic gates. In this experiment, the defective part level for REDO-based patterns was 1,288 parts per million lower than that achieved by DC stuck-at based patterns generated using today's state of the art tools and techniques.