Camouflaged object detection segments objects with intrinsic similarity and edge disruption. Current detection methods rely on accumulated complex components. Each approach adds components such as boundary modules, attention mechanisms, and multi-scale processors independently. This accumulation creates a computational burden without proportional gains. To manage this complexity, they process at reduced resolutions, eliminating fine details essential for camouflage. We present SPEGNet, addressing fragmentation through synergistic design. The architecture integrates multi-scale features via channel calibration and spatial enhancement. Boundaries emerge directly from context-rich representations, maintaining semantic-spatial alignment. Progressive refinement implements scale-adaptive edge modulation with peak influence at intermediate resolutions. This design strikes a balance between boundary precision and regional consistency. SPEGNet achieves $0.887~S_{\alpha } $ on CAMO, 0.890 on COD10K, and 0.895 on NC4K, with real-time inference speed. Our approach excels across scales, from tiny, intricate objects to large, pattern-similar ones, while handling occlusion and ambiguous boundaries. Code, model weights, and results are available at https://github.com/Baber-Jan/SPEGNet.

The rapid adoption of cloud computing has introduced critical security challenges in the cloud, with evolving cyberattacks exposing vulnerabilities in conventional intrusion detection systems (IDS). Existing approaches often struggle with high false-positive rates, poor handling of imbalanced traffic, and computational overhead in dynamic cloud environments. To address these issues, we propose SLCAE-BiLSTM, a deep learning-based IDS which enhances feature extraction and sequential learning. The Single-Layer Contractive Autoencoder (SLCAE) ensures efficient data representation by minimizing redundancy while preserving critical attack patterns. Meanwhile, the Bidirectional Long Short-Term Memory (BiLSTM) captures temporal dependencies in network traffic, improving the detection of rare attacks. Experimental evaluations on two benchmark datasets demonstrate SLCAE-BiLSTM's superiority, achieving 99.91% and 99.87% accuracy in binary classification and 97.73% and 91.22% in multi-class classification, surpassing state-of-theart models such as SCAE-SVM, SAE-SVM, and SDAE-SVM. These high accuracy rates indicate a significant reduction in misclassification and improved detection of both common and rare cyber threats. Furthermore, its reduced computational overhead and faster inference time makes it an efficient solution for enhancing cloud security against emerging threats.

With the widespread adoption of unmanned aerial vehicles (UAVs) in various applications (e.g., aerial transportation, traffic monitoring), there have been apprehensions regarding the associated risks of employing UAVs in both civilian and military contexts, including concerns about privacy infringement, safety issues, and security threats. Although several methods have been proposed to detect UAVs, a pressing open challenge is posed by varying adverse weather conditions that could degrade the performance of many existing methods. To address these limitations, this work proposes a YOLO-based (You Only Look Once) novel model,YOLO-RAWthat exhibits improved performance in adverse weather conditions and considers different scales of UAVs. Furthermore, to facilitate a more comprehensive evaluation of the proposed model’s effectiveness in UAV detection, we have curated a complex background dataset and introduced three distinct test sets affected by adverse weather conditions. These three test sets comprise the Rainy Test Set (RTS), the AWGN (Additive White Gaussian Noise) Test Set (ATS), and the Motion Blurred Test Set (MBTS). The comprehensive experiments demonstrate the effectiveness of the proposed YOLO-RAW model over its counterparts in detecting UAVs under adverse conditions. The code and datasets could be found at: https://github.com/AdnanMunir338/YOLO-RAW.

With fabrication technology reaching nanolevels, systems are becoming more prone to manufacturing defects with higher susceptibility to soft errors. This paper is focused on designing combinational circuits for soft error tolerance with minimal area overhead. The idea is based on analyzing random pattern testability of faults in a circuit and protecting sensitive transistors, whose soft error detection probability is relatively high, until desired circuit reliability is achieved or a given area overhead constraint is met. Transistors are protected based on duplicating and sizing a subset of transistors necessary for providing the protection. In addition to that, a novel gate-level reliability evaluation technique is proposed that provides similar results to reliability evaluation at the transistor level (using SPICE) with the orders of magnitude reduction in CPU time. LGSynth'91 benchmark circuits are used to evaluate the proposed algorithm. Simulation results show that the proposed algorithm achieves better reliability than other transistor sizing-based techniques and the triple modular redundancy technique with significantly lower area overhead for 130-nm process technology at a ground level.

Due to current technology scaling trends, digital designs are becoming more sensitive to radiation-induced particle hits resulting from radioactivity decay and cosmic rays. A low-energy particle can flip the output of a gate, resulting in a soft error if it propagates to a circuit output. Thus, soft error tolerance has become an important criterion in digital system design. In this work, we propose a simulation-based approach to reduce the soft error probability of circuit failure in combinational logic circuits. The proposed method is based on maximizing the probability of logical masking when a soft error occurs. This maximization is done by extracting sub-circuits from an original multi-level circuit, and then re-synthesizing each extracted sub-circuit to increase fault masking against a single fault. We present a two-level synthesis scheme to maximize soft error masking on each extracted sub-circuit. This scheme provides a heuristic that finds the best set of cubes to cover the input patterns of an extracted sub-circuit. A Fast Extraction (FX) algorithm is used to enhance the area overhead of synthesized two-level sub-circuits. Experimental results on some MCNC combinational benchmarks show that, on average, a probability of circuit failure reduction of 32% is achieved compared to the original circuit. The average area overhead is 40% of the original circuit.

A new scheme of test data compression, namely equal-run-length coding (ERLC) scheme is presented, which is based on run-length. It first considers both types of runs of 0's and 1's, then it further explores the relationship between two consecutive runs on the basis of the traditional characteristic of run coding which uses shorter codeword to represent longer symbol (run-length). This scheme uses two shorter codewords to represent the whole second run of two consecutive runs, the lengths of which are the same. Compared with other already known schemes this scheme has some characteristics, such as high compression ratio, easy control and implementation. The performance of the algorithm is mathematically analyzed and its merits are experimentally confirmed on the larger examples of the ISCAS89 benchmark circuits.

The paper presents a novel approach to increase the performance and/or throughput of iterative belief propagation (BP) decoding of low density parity check (LDPC) codes. The proposed approach is based on utilizing the decoder idle time by introducing two queue s: one at the decoder input and the other at the decoder output. At the presence of an input queue, the decoder runs extra iterations beyond the maximum allowable iterations as long as the input queue is not full. The function of the output queue is to preserve decoder timing, guaranteeing frames to be decoded within a fixed time similar to a conventional LDPC decoder, making it practical for real time applications. Simulation results for a rate ½ (1024,512) progressive edge-growth (PEG) LDPC code show that the proposed approach can increase the decoder performance up to 69% keeping the same throughput, or doubling the throughput while keeping performance almost the same.

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by quadded-transistor structure that guarantees defect tolerance of all single defects and a large number of multiple defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to 4 to 5 times more transistor defect probability) and at reduced area overhead.

An effective reconfigurable broadcast scan compression scheme that employs test set partitioning and relaxation-based test vector decomposition is proposed. Given a constraint on the number of tester channels, the technique classifies the test set into acceptable and bottleneck vectors. The bottleneck vectors are then decomposed into a set of vectors that meet the given constraint. The acceptable and decomposed test vectors are partitioned into the smallest number of partitions while satisfying the tester channels constraint to reduce the decompressor area. Thus, the technique by construction satisfies a given tester channels constraint at the expense of increased test vector count and number of partitions, offering a tradeoff between test compression, test application time and test decompression circuitry area. Experimental results demonstrate that the proposed technique achieves better compression ratios compared to other test compression techniques.

In this paper, we present a new test data compression technique based on block merging. The technique capitalizes on the fact that many consecutive blocks of the test data can be merged together. Compression is achieved by storing the merged block and the number of blocks merged. It also takes advantage of cases where the merged block can be filled by all 0's or all 1's. Test data decompression is performed on chip using a simple circuitry that repeats the merged block the required number of times. The decompression circuitry has the advantage of being test data independent. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique compared to previous approaches.

In this paper, we address the problem of FSM state assignment to minimize area and power. The objectives are targeted as single/independent as well as multi-objective optimization (MOP) problems. Methods for estimating area and power of an FSM are presented. A fuzzy-based aggregation function is employed to combine the two objectives. The work employs genetic algorithm for search space exploration. Experimental results demonstrate the effectiveness of the proposed measures.

The authors present efficient reverse-order-restoration (ROR)-based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vector-by-vector fault-simulation-based restoration of test subsequences, the authors' technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to the compacted test sequence, as in previous approaches, or merged with it. Furthermore, it allows the removal of redundant vectors from the restored subsequences using a state traversal technique and incorporates schemes for increasing the fault coverage of restored test subsequences to achieve an overall higher level of compaction. In addition, test relaxation is used to take ROR out of saturation. Experimental results demonstrate the effectiveness of the proposed techniques

In this paper we present efficient Reverse Order Restoration (ROR) based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vector-by-vector fault-simulation based restoration of test subsequences, our technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to the compacted test sequence, as in previous approaches, or merged with it. Furthermore, it allows the removal of redundant vectors from the restored subsequences using State Traversal technique and incorporates schemes for increasing the fault coverage of restored test subsequences to achieve an overall higher level of compaction. In addition, test relaxation is used to take ROR out of saturation. Experimental results demonstrate the effectiveness of the proposed techniques.

Testing systems-on-a-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Test-set relaxation can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify self-initializing test sequences for synchronous sequential circuits. In this paper, we propose an efficient test-relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.

Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester Relaxing test sequences can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify self-initializing test sequences for synchronous sequential circuits. In this paper we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.

Testing system-on-chips involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the chip under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and memory requirements for the tester. In this article, a new approach to static compaction for combinational circuits, referred to as test vector decomposition (TVD) , is proposed. In addition, two new TVD based static compaction algorithms are presented. Experimental results for benchmark circuits demonstrate the effectiveness of the two new static compaction algorithms.

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.

In this paper we employ fuzzified simulated evolution and stochastic evolution algorithms for VLSI. standard cell placement targeting low power dissipation and high performance. Due to the imprecise nature of design information at the placement stage, the various objectives and constraints are expressed in fuzzy domain. The search is made to evolve towards a vector of fuzzy goals. The proposed algorithms are compared with genetic algorithm.

The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper we introduce a novel and very efficient lossless compression technique for testing systems-on-a-chip based on geometric shapes. The technique exploits reordering of test vectors to minimize the number of shapes needed to encode the test data. The effectiveness of the technique in achieving high compression ratio is demonstrated on the largest ISCAS85 and full-scanned versions of ISCAS89 benchmark circuits. In this paper, it is assumed that an embedded core will be used to execute the decompression algorithm and decompress the test data.

This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times.

Recently, it has been shown that retiming has a very strong impact on the run time required for sequential, structural automatic test pattern generators (ATPG's), as well as the levels of fault coverage and fault efficiency attained. In this paper, we show that, for circuits with no hardware reset or a global reset state, retiming preserves testability with respect to a single stuck-at fault test set by adding a prefix sequence of a predetermined number of arbitrary input vectors. We show that this result holds for test sets derived based on structural and functional methods, and based on the conventional and multiple observation time testing strategies. Furthermore, we derive the conditions under which synchronizing sequences are preserved under retiming. We show that a structural synchronizing sequence for a circuit drives any of its corresponding retimed circuits to an equivalent state. In addition, we show that functional synchronizing sequences are preserved under retiming by adding a prefix sequence of a predetermined number of arbitrary input vectors. The impact of retiming on ATPG complexity and test-set preservation under retiming suggest a new approach for enhancing the performance of structural, sequential ATPG's. Experimental results show that high fault coverages can be achieved on high-performance circuits optimized by retiming with much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.

The research reported in this paper has been conducted to identify those attributes, of both sequential circuits and structural, sequential automatic test pattern generation algorithms, which can lead to extremely long test generation times. The retiming transformation is used to create families of circuits which have the same sequential depth and number and length of cycles, but a significantly different percentage of valid states. It was observed for three different sequential test pattern generators that the increase in complexity of test pattern generation is related to a new circuit attribute, termed density of encoding, and not to the sequential depth or number and length of cycles-i.e., those circuit parameters to which the complexity of test pattern generation has traditionally been attributed.

Abstract| Recently, it has been shown that retiming has a very strong impact on the run time of sequential, structural automatic test pattern generators (ATPGs), as well as the levels of fault coverage and fault eciency attained.In this paper, we show that retiming preserves testability with respect to a single stuck-at fault test set by adding a pre x sequence of a pre-determined number of arbitrary input vectors.Experimental results show that high fault coverages can be achieved on high performance circuits optimized by retiming with a much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.

In this paper, we study the testability preservation of the concurrent decomposition and factorization transformations under several delay-fault testing constraints. We show that all transformations, except dual extraction of multiplexor structures, preserve testability with respect to a general Robust Path-Delay-Fault (RPDF) test set, Validatable Nonrobust (VNR) delay-fault test set, and Delay Verification (DV) test set. In addition, we provide new, sufficient conditions for the algebraic resubstitution with complement transformation to preserve RPDF, VNR, and DV testability, that cover a larger class of complementary expressions than was known previously. Experimental results on a set of Berkeley PLA's and MCNC benchmark circuits show that dual extraction of multiplexor structures is utilized in only 2 out of 50 benchmark circuits. We demonstrate that while disabling this transformation has negligible effect on area, it results in an efficient test-set preserving multilevel logic synthesis algorithm, that preserves testability with respect to RPDF, VNR, and DV test sets.>

Recently, a new, very efficient method of multilevel logic synthesis based on factorization and decomposition of Boolean expressions has been introduced. It has been shown that the transformations used by this method preserve the single stuck-at testability of two-level circuits. This paper shows that single-cube extraction, double-cube extraction, and dual-extraction of double-cubes/spl isin/D/sub 1,1,2/ and D/sub 2,2,2/ preserve testability with respect to a general robust path-delay-fault (RPDF) test set. However, the authors show that while dual-extraction of double-cubes/spl isin/D/sub 2,2,3/ preserves RPDF testability of paths through the extracted divisors with respect to a single-input-changing test set, it does not guarantee RPDF testability preservation of unmodified paths. Furthermore, the authors provide sufficient conditions for algebraic resubstitution with complement to preserve RPDF testability that cover a larger class of complementary expressions than was known previously. The testability preservation of these transformations is demonstrated on a set of RPDF testable Berkeley PLAs.>

The primary consideration in the entire logic synthesis process is the quality of the resulting circuit measured by its speed, chip area, and recently also testability. The crucial phase in automatic logic synthesis, where all these parameters are determined, is the process of decomposition and factorization which generates multilevel Boolean equations for the synthesized circuit. There are a number of various aspects of testability. These aspects depend on the fault models and testing strategies used. One of the basic objectives is to synthesize circuits that are completely testable for a given class of faults.>