This paper introduces a novel cognitive multipath multi-channel routing protocol (CMMRP) for mobile ad-hoc networks. It is designed for a multi-channel environment where nodes can simultaneously use multiple interfaces to transmit packets over different frequencies. It employs cognitive functions to make nodes intelligently select multiple node-disjoint, edge-disjoint and frequency- disjoint paths. Neural network machine learning is adopted to make nodes aware of history. CMMRP employs a modified path discovery protocol which can be divided into two parts, a space discovery and spectrum discovery. Simulation results show that CMMRP significantly improves network reliability and performance.

This paper introduces a novel scalable cognitive routing protocol (SCRP) for mobile ad-hoc networks. It is an on-demand cognitive routing protocol. It employs an intelligent flooding protocol, a novel approach for scalable flooding. A neural network machine learning method is adopted to make nodes aware of history. The intelligent flooding protocol saves routing overhead because nodes selectively flood RREQ packets along predicted strong links and over predicted good frequencies. The intelligent flooding protocol can be divided into two parts, the space flooding protocol and the spectrum flooding protocol. Simulation results show that SCRP scales well by network size, network dynamics and network spectrum.

This paper provides a novel spectrum-aware routing protocol (SARP) for cognitive ad-hoc networks. It consists of two parts. One is the intelligent multi-interface selection function, which is used to assign an appropriate interface to a route to efficiently allocate the channels. The other is the intelligent multi-path selection function, which is used to select an appropriate path to route packets. This novel multi-channel multi-interface routing protocol is aware of both spectrum and space. Based on simulation results, SARP is able to improve network performance significantly.

There has been increasing interest in incorporating sensing systems into objects or the environment for monitoring purposes. In this work we compare approaches to performing fully-distributed anomaly detection as a means of detecting security threats for objects equipped with sensing and communication abilities. With the desirability of increased visibility into the cargo in the transport chain and the goal of improving security, we consider the approach of equipping cargo with sensing and communication capabilities as a means of ensuring the security of the cargo as a key application. We have gathered real sensor test data from a rail trial and used the collected data to test the feasibility of the anomaly detection approach. The results demonstrate the effectiveness of our approach.

The software defined radios movement is revolutionizing radio design by separating function from specific implementation. Like traditional software systems, software defined radio systems use a common operational definition that may be realized across numerous platforms. This paper describes initial efforts at realizing the promise of software defined radios by synthesizing radios to multiple implementation fabrics from a common Rosetta specification. We outline the approach by describing specifications used at each abstraction level, the operations implemented to synthesize radios, and various analysis techniques used to provide assurance in the resulting radio.

In this paper, we present a quantitative comparison of two agile modulation techniques employed by cognitive radio transceivers operating in a dynamic spectrum access (DSA) network. One of the modulation technique is non-contiguous orthogonal frequency division multiplexing (NC-OFDM), which is designed to avoid interference with the transmissions of incumbent users by deactivating subcarriers within their vicinity. The other modulation technique under study is a variant of multicarrier code division multiple access (MC-CDMA). Although several studies comparing conventional OFDM and MC-CDMA has been conducted in literature to justify robust error performance of MC-CDMA, a quantitative performance evaluation of these schemes has not been performed when employed in a DSA network. Due to deactivated subcarriers in DSA networks, in this paper we showed their performance can be significantly different from the conventional setup. Analytical expressions for the error probability of an NC-OFDM transceiver have been derived and compared with computer simulation results. The results show that the error robustness of NC-OFDM is relatively constant regardless of the number of deactivated subcarriers, unlike MC-CDMA transmissions, whose error performance degrades with an increase in deactivated subcarriers. 1

Cognitive networks are the latest progression of cognitive functionality into the networking stack, an effort which began with a layer one and two focus on cognitive radios, and has lately been extended to layer three and beyond. In this paper we evaluate an approach to network layer independence in wireless cognitive networks, utilizing and extending HIP to provide host identity across a myriad of network layers that evolve to meet application and environmental constraints and requirements. We detail a use case for this type of flexibility, specifically, a disaster relief scenario with complex usage and security requirements, and present evaluations that validate this approach. This work is a part of COGNET, an architectural framework for research into architectural tradeoffs and protocol design approaches for cognitive radio networks at both local network and the global internetwork levels.

The 11 papers in this special issue focus on adaptive, spectrum agile and cognitive wireless networks. Some of the topics covered include: fundamental performance aspects of spectrum sharing; spectrum sensing capabilities in cognitive radios; detection and estimation approaches to spectrum sharing; MAC design in opportunistic spectrum access; and competitive spectrum sharing and resource allocation using concepts from game theory and pricing.

Abstract This paper presents a genetic‐algorithm driven, cognitive radio decision engine that determines the optimal radio transmission parameters for single and multicarrier systems. Determining the appropriate radio parameters, given a dynamic wireless channel environment is the primary feature of cognitive radios for wireless communication systems. Genetic algorithms (GAs) are designed to select the optimal transmission parameters by scoring a subset of parameters and evolving them until the optimal value is reached for a given goal. Although there have been implementations of GA‐based single carrier cognitive radio engines, the performance of these algorithms has not been thoroughly analyzed nor have the fitness functions employed by the algorithms been explored in detail. Multicarrier systems are common in today's communication environment, thus cognitive techniques that account for only single‐carrier systems neglect the practical issues of multiple carriers. A set of accurate single carrier and multicarrier fitness functions for our GA implementation that completely control the evolution of the algorithm have been derived. The performance analysis results illustrate the trade‐offs between the convergence time of the GA and the size of the GA search space. Copyright © 2007 John Wiley & Sons, Ltd.

Many high-performance distributed applications use only a small fraction of their available bandwidth. A common cause of this problem is not a flaw in the application design, but rather improperly tuned network settings. Proper tuning techniques, such as setting the correct TCP buffers and using parallel streams, are well-known in the networking community, but outside this community they are infrequently applied. In this paper, we describe a service that makes the task of network tuning trivial for application developers and users. Widespread use of this service should virtually eliminate a common stumbling block for high-performance distributed applications.

This paper presents some experiences with class of service (CoS) translation in IP and MPLS based networks. IP provides CoS in the form of eight priority classes that can be used to distinguish between a variety of traffic types. Since most of the layer-2 technologies provide support for strict QoS, an appropriate translation from the coarse grained IP CoS to the fine-grained layer-2 QoS is fundamental to obtaining desired end-to-end throughput. Multiprotocol label switching (MPLS), residing in between IP and layer-2 in the protocol stack, provides an interface to translate IP CoS to appropriate layer-2 QoS. This paper presents some of the results obtained by using MPLS CoS with relative and fixed bandwidth allocation to MPLS classes. Experiments were conducted to observe the effects of per-CoS weighted fair queuing (WFQ) and class based queueing (CBQ) inside the MPLS cloud on fixed size high bandwidth traffic and bursty traffic. It was found that MPLS CoS did relative allocation of bandwidth and prevented starvation of lower priority flows inside the MPLS core. This paper also discusses some of the experiments conducted to evaluate the effects of improper CoS mapping, as a packet traverses multiple networks.

Active monitoring of TCP connections aids in the study of the stability of such connections over a given setup. With the advent of access technologies aiming to provide solutions to the last mile problem, there needs to be a method by which an ISP can study TCP connections over such equipment. TCP in itself has been designed to be stable and has been proven to be stable over many access technologies. But in many cases, the connections are not stable enough from a customer's perspective. Our effort has been to develop a TCP connection monitoring methodology that the ISP can study the rate at which connections are lost. We develop a connection monitoring tool (ConMon) that measures round trip time and throughput apart from detecting connections drops. The path to the end point is also traced in order to study reasons for possible connection drops. We test this tool over wired LAN, cable modem and broadband wireless technologies.

Virtual private networks implemented in software provide an economic and accessible alternative to hardware VPN solutions. Software VPNs may have a significant impact on performance, producing high CPU usage and limiting network throughput. This paper presents the performance measurements of several VPN programs. The results over a 100 Mb/s Ethernet link show that the transference speed can degrade in more than 65% while the CPU usage can reach 97%, when strong encryption is enabled. Compression implemented at the user level adds an additional CPU overhead that has a negative effect on the performance. The results over a low speed serial link show that the CPU usage is not significantly affected by the VPN. Furthermore, compression can be enabled without overhead, increasing the network throughput when the data is compressible.

The rapidly deployable radio network (RDRN) is an architecture and experimental system to develop and evaluate hardware and software components suitable for implementing mobile, rapidly deployable, and adaptive wireless communications systems. The driving application for the RDRN is the need to quickly establish a communications infrastructure following a natural disaster, during a law enforcement activity, or rapid deployment of military force. The RDRN project incorporates digitally controlled antenna beams, programmable radios, adaptive protocols at the link layer, and mobile node management. This paper describes the architecture for the RDRN and a prototype system built to evaluate key system components.

To assist in the design and understanding of future global networks, this paper describes the practical and simulation experiences gained from a TCP/IP on ATM network over a high speed satellite link and presents performance comparison studies of such networks with the same host/traffic configurations over local area (LAN) and wide area (WAN) networks. It was found that the satellite systems deliver performance similar to the terrestrial networks regardless of their path latencies in cases where the communication channels exhibit a low bit error rate (BER). NASA's Advanced Communications Technology Satellite (ACTS), with its special characteristics and high data rate satellite channels, and the ACTS ATM Internetwork (AAI) were used in these experiments to deliver broadband traffic. Network performance tests were carried out using application-level software (ttcp, Netspec) on OC-3 and OC-12 ATM satellite links.

Experiments in asynchronous transfer mode (ATM) wide area network (WAN) environments are discussed in this work. The lessons learned through practical experiences with ATM systems and how these can be applied to improving performance are presented. Factors ranging from the transport protocol to the equipment used and the network conditions are considered.

Most algorithms proposed for controlling traffic prior to entering ATM networks are based on static mechanisms. Such static control mechanisms do not account for the dynamics of the user traffic or the network state. Some dynamic control algorithms have been proposed, but most of these algorithms are extremely complex and may make it difficult to provide real time control. In this paper, we present an adaptive rate control algorithm that has been implemented in hardware. The algorithm controls the traffic submitted by a source based on the indirectly observed average rate and burst size for the source. The algorithm is highly efficient and thereby provides real time control at high speed. Our implementation, in concert with flow control in the local area network, provides the basis for ATM-based high performance distributed systems.

This paper describes performance measurements taken in the MAGIC gigabit testbed relating to the performance of TCP in wide area ATM networks. The behavior of TCP with and without cell level pacing is studied. In particular, we focus on results that indicate that the TCP rate control mechanism alone is inadequate for congestion avoidance and control in wide-area gigabit networks. We also present results showing that TCP augmented by cell-level pacing addresses these problems and allows the full bandwidth capacity to be utilized. These results demonstrate the viability of high performance distributed systems based on wide area ATM networks given the proper ATM traffic management infrastructure.

This letter describes a CAD system for automatic implementation of FIR filters on Xilinx field programmable gate arrays (FPGA). Given the frequency specifications, this software package designs an FIR filter, optimizes the filter coefficients in the power of two coefficient space, and implements it on FPGA chips. The FPGA specific mapping techniques used to increase speed are discussed. The performance of the typical filters that were implemented is presented.>

In this work, the performance scalability of ATM functions in the B-ISDN framework is explored. The aim is to identify the potential bottlenecks in designing circuits for ATM systems and to evaluate the effect of these limitations on system performance. Dependency relationships are used to illustrate and analyse the designs,given varying degrees of parallelism. The data flow in the receiver and transmitter sections are analysed to identify the critical delay paths. The design considerations imposed by SONET framing are also discussed. Limitations imposed by AAL-5, which is the preferred ATM adaptation layer for data networks, are identified. Finally, the results are combined to establish an overall limit on performance.>

Receive Path Termination in a SONET network is required to perform the path level functionality. The Synchronous Payload Envelope (SPE) of a SONET frame must first be located using the payload pointers in the SONET Line overhead. Once the SPE is located, the path termination device must keep track of it and provide information to higher level protocols about its location and status. While the most crucial functionality must be handled in hardware, the entire overhead information is stored for processing by a line card processor. The incoming SONET stream is processed in words of 32 bits each. The quadruple OC-3c mode (OC-12) occupies almost an entire Xilinx XC 3195 Field Programmable Gate Array (FPGA). The SONET OC-12c mode processing takes fewer gates but requires the large chip to perform a Bit Interleaved Parity (BIP) check on the SPE. The interface to both designs is physically identical and they can form a part of a line card that is capable of two distinct modes of operation.>

The Synchronous Optical Network (SONET) and Synchronous Digital Hierarchy (SDH) form a high speed data transmission standard used to transport various types of payloads. Asynchronous Transport Mode (ATM) cells are an increasingly important payload type. This paper describes two pipelined implementations of these mapping functions. The first implementation maps a stream of ATM cells into a SONET OC-12 synchronous payload envelope (SPE). The second circuit maps distinct ATM cell streams into four SONET OC-3c SPE's, which in turn can form a SONET OC-12 signal. Both of these implementations operate at 622 Mb/s. They have been implemented on a single, Xilinx XC3195 Field Programmable Gate Array (FPGA) and have an identical physical interface. This design is part of a system line card that can transmit and receive in the above mentioned modes.>

This paper describes a gigabit LAN/WAN gateway being developed for the MAGIC gigabit testbed. The gateway interfaces a gigabit LAN developed by Digital's Systems Research Center and the MAGIC SONET/ATM wide area network. The gateway provides 622 Mb/s throughput between the LAN and WAN environments, and supports either a single STS-12c or four STS-3c tributaries. Traffic measurement capability and support for multiple bandwidth management schemes are provided by this architecture.>

A priority knockout switch (PKS) architecture using priority based congestion control mechanisms is presented for broadband ISDN (BISDN) networks. This architecture provides the capability of assigning qualities of service to connections through per cell or virtual circuit priority mechanisms. Performance studies that use an analytical model for uniform traffic and simulation models for uniform and bursty traffic are presented. These studies indicate that the PKS architecture provides excellent cell loss rates for high priority traffic at minor expense to the low priority traffic. CMOS implementations of the switch modules that demonstrate the feasibility of the architecture are described.>

The implementation of digital signal processing algorithms often requires that a variety of conflicting criteria be satisfied. A signal processing system must provide the necessary processing gains, while various measures of the feasibility and efficiency of implementation, such as power and cost, are met. This paper reviews the motivation behind the development of low power signal processing algorithms, presents some methods for addressing these problems, and gives several examples of reduced complexity signal processing implementations.>

The performance of stochastic gradient based adaptive algorithms depends on the selection of a step size parameter which must balance the conflicting goals of fast convergence and small steady state error. The author presents a novel variable step size algorithm that performs as well as previously proposed algorithms but is less complex to implement. In particular, the memory savings is substantial. A convergence analysis for this algorithm is also presented.>

The implementation of a high-speed, programmable finite impulse response (FIR) filter using coefficients consisting of two power-of-two terms is presented. The area and speed performance figures for this application-specific IC (ASIC) demonstrate the superiority of this architecture for high-speed and high-density implementation. This implementation was developed using a relatively primitive CMOS process. Simple lambda -rule scaling suggests that by using a 1.25- mu m and double-level metal process of the same die size, this architecture will allow the implementation of a filter of approximately 200 taps operating at a 10-MHz sampling rate.>

The authors consider the implementation of the combined variable-step-size (VS)-power-of-two quantizer-multiplier (PTQ) algorithm in a 2.5- mu m CMOS process. A 7-MHz chip with four taps, using dedicated hardware for each tap, and a 32-kHz chip with 63 taps, using multiplexed processing hardware, are presented. The area and speed performance figures for these chips are comparable with recently published results when lambda -rule scaling is used; however, the performance of the VS-PTQ algorithm is superior.>

The application of adaptive filters in noise cancelling often requires the relative placement of the two transducers at a distance that necessitates a large order filter in order to obtain an adequate output signal-to-noise ratio. A new adaptive filter structure is introduced that permits a closer placement of the transducers and that allows the cancellation of noise in the presence of crosstalk. Algorithms are developed for the new transversal and lattice structures. Simulations show considerable improvement in mean-square error over that obtained with standard noise cancelling algorithms.